JP3306176B2 - Fault diagnosis device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a fault diagnosis apparatus, and more particularly to a fault diagnosis apparatus for diagnosing a stuck-at fault and a short-circuit fault of a logic circuit.

In recent years, with the miniaturization of processing technology, it has become important to shorten the design period and reduce costs when developing a semiconductor device such as a VLSI.

In developing a VLSI or the like, there are many cases where a plurality of faults are present in a circuit, and a device capable of efficiently diagnosing these faults is required to shorten the development time. VLS
Faults such as I include stuck-at faults as well as stuck-at faults, and fault diagnosis devices are required to be able to diagnose both stuck-at faults and short-circuit faults.

In order to minimize the number of prototypes of a chip, it is necessary to specify more failures from one chip.

[0005]

2. Description of the Related Art A conventional VLSI failure diagnosis apparatus includes VL
There are two types: one for performing fault diagnosis from the external output of the SI, and the other for performing fault diagnosis by directly observing the internal value of the chip with an electron beam.

[0006] As a device for performing fault diagnosis by an external output, see [H. Y. Chang, E. Manning and G. Metz:
“Fault diagnosis of digital systems”, Jahn Wil
ey & Sons, Inc (1970).], a fault dictionary method that registers fault output for each fault in a dictionary in advance and performs fault diagnosis by comparing the fault output with the observed output [Teriko Yamada, Yoshiyuki Nakamura: "A diagnostic method for single stuck-at faults in combinational circuits", IEICE, Vol. J74-DI, No.11, pp.
774-780 (November 1991)], a failure diagnosis limited to a single stuck-at fault or [M. Abramovic
i & M. A. Breuer: "Fault Diagnosis based on
Effect-Cause Analysis: an Introduction ", Proc.
17th DAC, pp. 69-76 (June 1980)]
In some cases, multiple stuck-at faults are diagnosed without using a dictionary by using a result cause analysis method in which faults are inferred from output observation values by an algorithm including backtracking, without using a dictionary.

A method of diagnosing a failure by directly observing a value inside the chip with an electron beam is disclosed in [T. Tamama an
d N. Kuji: "Integrating an Electron-Beam System
m into VLSI Fault Diagnosis ", IEEE D
esign & Test, 3,4, pp.23-29 (August 1986)], [Yoshizo Kinoshita, Xiaoqing Wen, S.M. Reddy: "N in observable environments
Diagnosis of Failure of AND Logic Circuit ", IEICE Techniques Vol.88, No.45
6, FTS88-33 (February 1989)], [Noboru Yamaguchi, Tsukasa Sato, Hideo Todokoro, Yoshimune Hagiwara, Takashi Sakamoto: "Basic study on fault finding method for VLSI using electron beam tester", IEICE Tech. Vol.8
9, No. 71, FTS-12 (June 1989)].

Further, as a diagnostic method capable of diagnosing multiple shrinkage faults by combining the above-mentioned method of detecting a fault with an external output and the method of diagnosing a fault with an electron beam, there are [Diamond Yamada, Shuji Hamada, Tatsuo Matsumoto, Toshihiko Takahashi, Takao Nakayama: "Diagnosis of multiple stuck-at faults in combinational circuits", IEICE (D-I), Vol.J74-DI, No.1, pp50-5
7 (January 1991)], and a method for diagnosing short-circuit faults has been proposed [Teriko Yamada, Koji Yamazaki: "Diagnosis of Single Short-Circuit Faults in Combinational Circuits" IEICE, DI .J
74-DI, No. 1, pp. 58-64 (January 1991)].

[0009]

However, among the conventional fault diagnosis apparatuses which use the fault dictionary method to diagnose a fault only from an external output without referring to the internal value of the circuit, there is a VLSI circuit scale. As the size of the dictionary grows, the number of dictionaries it owns becomes enormous, making it difficult to realize.In addition, a single stuck-at fault is diagnosed if it is proposed as a practical method for large-scale circuits. If multiple stuck-at faults or short-circuit faults are present, diagnosis cannot be performed, and the result cause analysis method uses an algorithm that includes backtracking. Was not the target. In a device that diagnoses a failure by observing a value inside a circuit by an electron beam, it is possible to diagnose each of a multiple stuck-at fault and a short-circuited fault, but when a stuck-at fault and a short-circuited fault are present at the same time, Since it is not possible to cope with it, it is extremely difficult to observe signal lines other than the surface layer because of the use of electron beams, the equipment is large, the cost is high, and the range that can be observed at one time is limited. Therefore, it is difficult to put the system into practical use, and the combination of external output diagnosis and electron beam diagnosis can only perform fault diagnosis for multiple stuck-at faults and single short-circuit faults. Was.

SUMMARY OF THE INVENTION The present invention has been made in view of the above points, and has as its object to provide a failure diagnosis apparatus capable of diagnosing multiple degeneration and short-circuit failure by observing an external output with a relatively simple configuration.

[0011]

FIG. 1 is a block diagram showing the principle of the present invention. A predetermined input pattern is supplied to the diagnosis target 1 from the input pattern supply means 2, and an output pattern corresponding to the supplied input pattern is output.

Assumed fault pattern generation means 3 generates a fault output pattern obtained from the connection information in accordance with an input pattern, for a fault presumed in the connection information of the diagnosis target 1.

The evaluation value calculating means 4 detects a difference between each logical value between the fault output pattern generated by the hypothetical fault pattern generating means 3 and the output pattern of the diagnosis target 1, and for each hypothetical fault according to the number of differences. Is calculated.

The failure diagnosis means 5 diagnoses a failure of the diagnosis target 1 in accordance with the evaluation value calculated by the evaluation value calculation means 4.

[0015]

A predetermined input pattern is supplied to the object to be diagnosed by the input pattern supply means, and an output pattern corresponding to the input pattern is obtained.

This output pattern is compared with the fault output pattern generated by the assumed fault pattern generating means, and the difference is detected. An evaluation value is determined for each assumed failure according to the number of differences detected for each assumed failure, and failures are diagnosed according to the evaluation values.

As described above, since the failure can be diagnosed by the input / output pattern of the object to be diagnosed, the diagnosis can be easily performed.

[0018]

FIG. 2 is a block diagram showing an embodiment of the present invention. In the figure, reference numeral 11 denotes a device under test (DUT: Device Under T).
est). The device under test 11 is an LSI, VLSI
And the like, a logic circuit is formed inside and the input pin PI
, The output data corresponding to the input data is output from the output pin PO.

An input pin PI and an output pin PO of the device under test 11 are connected to a tester 12. The tester 12 is connected to the device under test 11 and to the test input file unit 13 and the output pattern file 14. The tester 12 converts a test input signal supplied from the test input file unit 13 into an input pin P of the device under test 11.
I and output pin P of device under test 11
Output pattern file 1 for external output from O
4

The test input file unit 13 is a file storing a test input signal for testing the device under test 11, and is connected to the failure diagnosis unit 15 and performs a test according to a test input selection control signal from the failure diagnosis unit 15. An input signal is supplied to the tester 12. The output pattern file unit 14 is a file for storing a test output signal output from the device under test 11 via the tester 12 in accordance with the test input signal supplied from the test input file unit 13 via the tester 12, and is used for failure diagnosis. It is connected to the unit 15 and supplies an output pattern signal to the failure diagnosis unit 15 according to an output pattern control signal from the failure diagnosis unit 15.

The failure diagnosis unit 15 is connected to a netlist file unit 16, a diagnosis result file unit 17, an analysis result file unit 18, and a display unit 19 in addition to the test input file unit 13 and the output pattern file unit 14. The net list file unit 16 is a file storing a net list as connection information of the device under test 11, and stores the net list in response to a request from the failure diagnosis unit 15.
To supply.

The diagnosis result file section 17 is provided in the failure diagnosis section 15
In this file, the numbers of signal lines and the like are stored in descending order of the possibility of failure. The analysis result file section 18 is a file for storing the analysis result obtained by the failure analysis section 20 and supplies the stored analysis result to the failure diagnosis section 15 in response to a request from the failure diagnosis section 15.

The failure analysis unit 20 is configured to directly observe a signal line inside the circuit of the device under test 11 such as an electron microscope or an EB (electron beam) tester. Based on the data of the signal lines stored in the file unit 17 in the descending order of the possibility of failure, the signal lines that are considered to have a failure are observed directly in the descending order of the possibility of the failure, and the analysis result is analyzed. The data is supplied to the analysis result file unit 18. The failure diagnosing unit 15 controls each of the above file units, reads necessary data, diagnoses a failure according to a procedure described later, and displays the failure on the display device 19 or the like.

FIG. 3 is a diagram for explaining the operation of the failure diagnosis unit 15. In the failure diagnosis unit 15, first, the test input file unit 1
3 through the tester 12 to control the device under test 11
The test input signal is supplied to the input pin PI.

The device under test 1 according to the test input signal
An output pattern signal output from one output pin PO is obtained via the tester 12 and the output pattern file unit 14 (step S1). Next, from the output pattern signal, V (E∈
(0, 1)), the output pin PO is detected and output as a stuck-at fault to the diagnosis result file and excluded from the subsequent processing target (step S2).

Next, a test input signal to be performed next is selected centering on a test input signal having a difference between an output pattern signal to be obtained according to the test input signal and an actually obtained output pattern signal (step). S3).

Further, the output pin PO having a difference between the output pattern signal to be obtained in accordance with the test input signal and the actually obtained output pattern signal using the netlist filed in the netlist file section 16 is generated. A circuit requiring inspection is cut out based on the inspection (step S4).

FIGS. 4 to 6 show diagrams for explaining the circuit cutting operation. In FIG. 4, when PO1 is an external output pin where an error is observed, first, the external output pin PO1
Are cut out toward the input pin PI.

In the circuit as shown in FIG. 4, a circuit in a region shown by oblique lines in FIG. 5 is cut out, and external input pins PI1 to PI3 for supplying a signal thereto are cut out.

Next, a circuit affected by the input pins PI1 to PI3 affecting the output pin PO1 is referred to as an output pin PO1.
Cut out toward. For example, a circuit in a region indicated by satin in FIG. 6 is cut out. The fault diagnosis is performed on the circuit cut out as described above. This circuit extraction operation is executed according to the netlist of the device under test 11 stored in the netlist file unit 16. At this time, the value of the signal line fan-in to the gate in the cut circuit from outside the cut circuit is treated as an indefinite value X.

Returning to FIG. 3, the operation of the failure diagnosis unit 15 will be described.

After the circuit is cut out, a fault to be diagnosed is assumed for the cut out circuit (step S).
5). At this time, a failure is assumed for the signal lines except the input / output pins PI1 to PI3 and PI7 included in the hatched portions in FIG. The signal lines included in the cut-out circuit are analyzed by the failure analysis unit 20 in the analysis result signal file unit 1.
If the file is stored in the file No. 8, no fault is assumed for the signal lines confirmed to be normal among them.

Next, a logic simulation is performed on the circuit extracted in step S4 using the test input signal selected in step S3, an output pattern signal is obtained, and a fault circuit simulation is performed for the assumed fault assumed in step S5. Is performed, and the difference between the hypothetical fault theoretical value and the test output signal value is totalized for each evaluation item (step S6).

At this time, if there is a theoretical output value calculated in advance, the simulation is not performed and that value is used. The evaluation items are classified into, for example, pins for which an error has been observed in another pattern of the path patterns and pins for which no error has occurred, and pins of the fail pattern for which an error has been observed and pins which have not. When an analysis result is filed in the analysis result file unit 18 and a signal line confirmed to be faulty is included in the analysis result file unit 18, the fault signal is output using the netlist filed in the netlist file unit 16. An equivalent circuit corresponding to the line is inserted, and it is regarded as a normal circuit to obtain a theoretical value and perform processing.

Next, in step S6, a value corresponding to the difference between the theoretical value and the test output signal totalized for each signal line and for each hypothetical fault is assigned an appropriate weight for each hypothetical fault for each evaluation item. A final evaluation value is obtained by adding. At this time, for example, the weight is set so that the possibility of a failure increases when the evaluation value is large, and the hypothetical failures are sorted in descending order of the evaluation value.

When the weight is set so that the possibility of a failure increases when the evaluation value is small, the hypothetical faults are sorted in ascending order of the evaluation value (step S7).

The signal lines sorted in step S7 are sequentially filed in the diagnostic result file section 17 (step S7).
8).

Next, the operation of this embodiment will be described with reference to FIGS. FIG. 7 shows a specific circuit configuration diagram of the device under test 11. FIG. 7A shows a normal circuit, and FIG.
It is assumed that the signal line A has a stuck-at fault at '1' and the signal lines C and D have a short-circuit fault as shown in FIG.

FIG. 8A shows a test input.
8B shows external output signal lines N, H, I, J when the test input of FIG. 8A is applied to the normal circuit shown in FIG.
This is the expected value. FIG. 8C shows values observed on the external output signal lines N, H, I, and J when the test input of FIG. 8A is applied to the circuit under test shown in FIG. 7B. FIG. 9A shows a partial circuit assuming a failure and a partial circuit to extract, and FIG. 9B shows a circuit after the extraction. FIG.
0 (A) is the value on the external output signal lines H, I, J when each hypothetical fault is inserted into the circuit of FIG. 9 (B). FIG.
FIG. 10B shows the difference between the observed value and the theoretical value of each hypothetical fault, and FIG. 10C shows the evaluation value of each hypothetical fault.
0 (D) is a diagnosis result.

Here, it is assumed that when the signal line is short-circuited, a wired OR operation is performed. First, according to step S2 in FIG. 3, the external output N degenerated to 0 is detected, output to the diagnostic result file unit 17 as a diagnostic result of the signal line N, and excluded from the processing. Since the circuit is simple, the test input selection in step 3 in FIG. 3 has a small number of patterns, and thus all patterns are selected here. The output pattern of FIG. 8C is obtained from the input patterns t _{1 to} t ₄ of FIG. 8A and is compared with the expected value of FIG. The difference is seen. Therefore, as described in FIGS. 4 and 5, the external output H,
Fig. 9 shows a cone cut from I to the external input.
The hypothetical fault is selected from the signal lines included in the hatched portion as shown in FIG. Here, representative faults A / 1, B / 1, C / 1, D / 1, E /
0, E / 1, F / 1, G / 1 are selected. Further, when a circuit is extracted from the external inputs A, B, C, and D included in the hatched portion toward the external output, a circuit included in the hatched portion and the hatched portion in FIG. 9A is obtained. However, since the external output N is degenerated to 0, the partial circuit to be finally extracted is as shown in FIG. 9B, and the extraction of the circuit in step S4 in FIG. 3 ends. Next, the results of simulating external output values by inserting each hypothetical fault into the circuit of FIG. 9B are as shown in FIG. 10A. The observed values shown in FIG.
FIG. 10B shows the difference between the logical value in each hypothetical fault shown in FIG. 10A and the undefined value X in each of the patterns t _{1 to} t ₄ , and the number of matching values is counted. Then, the process of step S6 in FIG. 3 ends. FIG.
The number of effective pins in (B) is the total number of pins that did not take an undefined value X in both the observed value and the theoretical value. Step S7 in FIG.
In FIG. 10B, the evaluation value is obtained by dividing the number of matching pins by the number of valid pins, that is, the evaluation value of a signal line having a large number of matching pins with the assumed failure logic in the number of valid pins increases. The evaluation value of a device having a high possibility of failure is greatly expressed. The evaluation value of each hypothetical fault is as shown in FIG. If this is sorted in descending order of the evaluation value, the result shown in FIG. 10D is obtained. The signal lines are supplied to the diagnosis result file unit 17 in the order shown in FIG. FIG. 10D shows the result that the possibility of failure is high in order from the top. However, “*” in FIG. 10D indicates a stuck-at fault of the external output.

As shown in FIG. 7 (B), the faults inserted are a stuck-at-1 fault on the signal line A and a short-circuit fault on the signal lines C and D.
As shown in FIG. 10D, these faults are ranked higher in the diagnosis result. The failure analysis unit 20 may be operated based on the diagnosis result to confirm the failure. FIG.
FIG. 12 is a diagram for explaining the operation of the second embodiment of the present invention. This embodiment has the same configuration as that of FIG. 2, and differs from the first embodiment in the method of counting the difference between the observed value and the theoretical value in step S6 among the steps of the failure diagnosis unit 15 shown in FIG.

FIG. 11 shows the difference between the observed value and the theoretical value for each hypothetical fault described with reference to FIG. 10A of the first embodiment, by comparing the pass pattern with the fail pattern, and the fail pattern with the pass pin and the fail pin. This is the result of dividing and totaling. FIG. 12A shows evaluation values of each hypothetical fault.
FIG. 12B shows the diagnosis result.

The circuit and other conditions are the same as in the first embodiment. FIG. 11 shows the results obtained by tabulating the differences between the observed values and the theoretical values for each hypothetical fault in the following five cases. 1. Pins H and I for which an error was observed in another test in the path pattern. 2. Pin J of the path pattern for which no error was observed in another test. 3. Pins H and I for which an error was observed in any of the pass pins of the fail pattern. 4. Among the pass pins of the fail pattern, the pin J in which no error was observed in any of the tests. Five kinds of total results of fail pin of fail pattern are obtained.

The number of coincident pins is the total number of pins that do not take an indefinite value X in both the observed value and the theoretical value and that has a coincident value. The effective pin number is the number of pins in both the observed value and the theoretical value. FIG. 12A shows the total number of pins that did not take the indefinite value X.
The evaluation result by the following formula is shown.

[0045]

(Equation 1)

Where WPP _HI = 0.2, WPP _J = 0.2,
WFPP _HI = 0.1, WFPP _J = 0.4,

[0047]

(Equation 2)

Assume that In this case, the weight distribution is such that a fail pattern is more important than a pass pattern, and a fail pin is more important than a pass pin in the fail pattern. If the results of FIG. 12A are sorted in descending order of the evaluation value, the result that the possibility of failure is high in the order shown in FIG. 12B is obtained. However, FIG.
“B” in (B) indicates a stuck-at fault of the external output.

The inserted faults are a stuck-at-1 fault on the signal line A and a short-circuit fault on the signal lines C and D. In the first embodiment, A / A
1, B / 1, D / 1, and E / 0 have the same rank, but in the result of FIG. 12B, C / 1, D / 1, and A / 1 are shown in FIG. The three signal line faults corresponding to the faults shown are ranked in the top three places, indicating that fault diagnosis can be performed more accurately than in the first embodiment.

FIGS. 13 to 15 show the operation of the third embodiment of the present invention. The configuration of the present embodiment is the same as that of FIG.

FIG. 13 shows an analysis result obtained by performing a failure analysis by the failure analysis unit 20 based on the diagnosis result obtained in the diagnosis result file unit 17 obtained in the first embodiment in the analysis result file unit 18. , The content of which is signal line B
Is a normal circuit which is the target of the failure diagnosis unit 15 when it is assumed that the signal lines C and D have a short-circuit failure. FIG.
4 (A) is an observed value, which is the same as in the first embodiment. FIG. 14B is a theoretical value of the output for each hypothetical fault. FIG. 15A is a result of tabulating the difference between the observed value shown in FIG. 14A and the theoretical value for each hypothetical fault shown in FIG. 14B, and FIG. It is an evaluation value.

Here, a failure analysis based on the diagnosis result obtained in the first embodiment (assuming that signal line B is normal and signal lines C and D have a short-circuit failure) exists. An example of diagnosis is shown. It is assumed that the circuit to be diagnosed, the test input, the counting method of the difference between the observed value and the theoretical value in each hypothetical fault, and the like are the same as those in the first embodiment. When the short-circuit fault of the signal lines C and D in the analysis result is inserted into the normal circuit extracted in the first embodiment, the circuit shown in FIG. 13B is obtained. The theoretical value of the output for a hypothetical fault is as shown in FIG.
Here, since the states of the signal lines B, C, and D are known, they are not included in the assumed failure. The observed values shown in FIG.
4 (B) The difference is calculated from the theoretical value of the output for each hypothetical fault, as shown in FIG.
(B). As is clear from FIG. 15B, the one stuck-at fault of the signal line A, which was an undiscovered fault, is ranked first in the diagnosis result.

FIGS. 16 and 17 are explanatory diagrams of the operation of the fourth embodiment of the present invention. The configuration of the present embodiment is the same as that of FIG.

FIG. 16A is a circuit diagram of a normal circuit, and FIG. 16B is a circuit to be diagnosed in which the signal lines D and F are short-circuited in FIG. 16A. FIG. 16C is an equivalent fault circuit of FIG. FIG. 17A shows a test input, and FIG. 17B shows an external output signal line G when the test input of FIG. 17A is applied to the normal circuit of FIG. 16A. This is the expected value of A). FIG.
(C) is a value observed on the external output signal line G when the test input of FIG. 17 (A) is applied to the circuit under test of FIG. 16 (B). FIG. 17D shows each hypothetical fault in FIG.
This is the value on the external output signal line G when inserted in the circuit of FIG.

Here, the circuit shown in FIG.
A case where a short circuit fault occurs between the signal lines D and F as shown in FIG. Note that when the signal line is short-circuited, a wired OR operation is performed. The observed values are as shown in FIG. 17C, and since there is no degenerated external output, the processing in step S2 in FIG. 3 is skipped. In the test input selection in step S3, all the pattern targets are selected because the number of patterns is small. Further, since it is a single output circuit, step S4 for extracting a partial circuit is skipped. Here, the assumed faults in step S5 are representative faults A / 1, B / 1, C / 1, D / 1, E /
1, F / 1 is selected. In steps S6 and S7,
The result of simulating the external output value by inserting each hypothetical fault into the circuit of FIG. 16A is as shown in FIG. 17D, and the observed value of FIG. 17 is obtained by the same method as in the first embodiment, the result of the calculation is obtained as shown in FIG.
When the evaluation value is obtained from (E), the assumption fault A / 1, B /
The evaluation values of 1, C / 1, D / 1, E / 1 and F / 1 are shown in FIG.
7 (F), 0.4, 0.4, 0.
8, 0.8, 0.4, 1.0 and F / 1, ΔC / 1,
D / 1 可能, A / 1, B / 1, and E / 1 increase the likelihood of failure.

The inserted fault is a short-circuit fault between the signal lines D and F, and these faults are ranked first and second in the diagnosis result.

FIGS. 18 and 19 are explanatory diagrams of the operation of the fifth embodiment of the present invention. The configuration of the present embodiment is the same as that of FIG.

FIG. 18A is a circuit diagram of a normal circuit, and FIG. 18B is a circuit diagram of FIG. 18A in which the signal line H is degenerated to 1 and the signal lines B and C are short-circuited. This is the circuit to be diagnosed. FIG. 18C is an equivalent fault circuit of FIG. FIG. 19A shows a test input, and FIG.
(B) is an expected value of the external output signal line G when the test input of FIG. 19 (A) is applied to the normal circuit of FIG. 18 (A). FIG. 19C shows values observed on the external output signal line G when the test input of FIG. 19A is applied to the circuit under test of FIG. 18B. FIG. 19D shows values on the external output signal line G when each hypothetical fault is inserted into the circuit of FIG. 18A. FIG. 19 (E) shows the result of counting the difference between the observed value shown in FIG. 19 (C) and the output value for each fault shown in FIG. 19 (D), and FIG. 19 (F) shows the evaluation value of each hypothetical fault. It is.

Here, the circuit shown in FIG.
When the test input of (D) is applied, the observed value
An example of diagnosis when (C) is obtained is shown. The fault actually inserted is a short-circuit fault between the signal lines D and F, as shown in FIGS. 18B and 18C.
Shall be The observed values are as shown in FIG. 19 (C), and since there is no degenerated external output, step S2 in FIG.
Is skipped. In addition, the test input selection in step S3 is performed from t ₁ to t ₁ including the fail pattern here.
₄ shall be selected. Since it is a single output circuit, step S4, which is a process of extracting a partial circuit, is also skipped. Here, the assumed faults in step S5 are representative faults A / 1, B / 1, C / 1, D / 1, E / 1, F / excluding external outputs.
1, H / 1 is selected. In steps S6 and S7,
The results of simulating the external output values by inserting each hypothetical fault into the circuit of FIG. 18A are as shown in FIG. 19D, and the observed values shown in FIG. When the differences from the theoretical values for each of the assumed faults shown are tabulated in the same manner as in the first embodiment, the results are as shown in FIG. 19E, and the evaluation values are 0.0, respectively, as shown in FIG. 19F.
0, 0.75, 0.50 ,, 0.50, 0.25, 0.
25, 0.75, {B / 1, H / 1}, {C /
1, D / 1}, {E / 1, F / 1}, A / 1, the likelihood of failure is high.

The inserted faults are the stuck-at-1 fault on the signal line H and the short-circuit fault between the signal lines D and F, and these faults are ranked in the first and second places in the diagnosis result. Considering that short-circuit faults can inevitably be found if one of the short-circuited signal lines is found, in this case, all faults are found simply by analyzing the fault ranked first in the diagnostic results You can do it.

As described above, according to the first to fifth embodiments, the processing target is reduced by selecting the test input and extracting the partial circuit, thereby enabling high-speed processing. When a test input is cut out in the sequential circuit, the internal state of the storage element is started from an indefinite value in both normal and failure simulations, so that the sequential circuit can process only a part of the test inputs. Hypothetical faults contribute to high-speed processing by extracting a circuit, so that only the cone containing the fail pin can be assumed.In extracting a partial circuit, a cone is cut out from the fail pin toward the external input and included in the cone. By re-tracing from the external input to the external output, the normal pin is included in the partial circuit, and more accurate evaluation becomes possible. The simulation may be performed with the signal lines fan-in to the extracted partial circuit as indefinite values.
The evaluation value of each hypothetical fault can be obtained only from the circuit output value from the semiconductor tester, and observability inside the circuit is not required. By classifying the evaluation items into pass patterns, fail patterns, and the like, flexible evaluation can be performed, and diagnosis with multiple degeneration and short-circuit faults can be performed. The short-circuit degeneration can be handled, for example, in a positive (negative) logic circuit, since a short-circuited signal line forms a wired AND (OR), a logical value 0 (1) is inevitably generated easily.
(1) It can be pointed out as a stuck-at fault. By sorting the evaluation value as a key at the end of the diagnosis, signal lines having a high possibility of failure can be sequentially pointed out. If there is a result of the failure analysis of the DUT, the information is read at the time of the failure diagnosis, so that more accurate evaluation can be performed, and the undiscovered failure is positioned at a higher rank of the diagnosis result without reprototyping the chip.

The first to fifth embodiments are modified by using about 3,50 gates.
0, when applied to a circuit with about 7,500 signal lines, there are actually several failed signal lines in the top 100 signal lines indicated, and in many cases, There was one actual failure in the book. This did not depend on the fault multiplicity.

[0063]

As described above, according to the present invention, a difference between a hypothetical fault pattern and an output pattern is detected, an evaluation value of each hypothetical fault is calculated according to the difference, and an evaluation value is calculated according to the calculated evaluation value. In order to diagnose a fault, it is possible to diagnose the fault only from an external output that is easily observable.
Since the diagnosis is performed from the evaluation value for the assumed failure, the diagnosis can be realized with a relatively simple configuration, and therefore, it has features such that the failure diagnosis can be performed at high speed and at low cost.

[Brief description of the drawings]

FIG. 1 is a principle configuration diagram of the present invention.

FIG. 2 is a configuration diagram of a first embodiment of the present invention.

FIG. 3 is an explanatory diagram of an operation of a failure diagnosis unit according to the first embodiment of the present invention.

FIG. 4 is an explanatory diagram of a circuit cutting operation according to the first embodiment of the present invention.

FIG. 5 is an explanatory diagram of a circuit cutting operation according to the first embodiment of the present invention.

FIG. 6 is an explanatory diagram of a circuit cutting operation according to the first embodiment of the present invention.

FIG. 7 is an operation explanatory diagram of the first embodiment of the present invention.

FIG. 8 is an operation explanatory diagram of the first embodiment of the present invention.

FIG. 9 is an operation explanatory diagram of the first embodiment of the present invention.

FIG. 10 is an operation explanatory diagram of the first embodiment of the present invention.

FIG. 11 is an operation explanatory diagram of the second embodiment of the present invention.

FIG. 12 is an operation explanatory diagram of the second embodiment of the present invention.

FIG. 13 is an operation explanatory diagram of the third embodiment of the present invention.

FIG. 14 is an operation explanatory diagram of the third embodiment of the present invention.

FIG. 15 is an operation explanatory view of the third embodiment of the present invention.

FIG. 16 is an operation explanatory view of the fourth embodiment of the present invention.

FIG. 17 is an operation explanatory view of the fourth embodiment of the present invention.

FIG. 18 is an operation explanatory view of the fifth embodiment of the present invention.

FIG. 19 is an operation explanatory diagram of the fifth embodiment of the present invention.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 diagnosis target 2 input pattern supply means 3 assumed failure pattern generation means 4 evaluation value calculation means 5 failure diagnosis means 11 device under test (DUT) 12 tester 13 test input file section 14 output pattern file section 15 failure diagnosis section 16 netlist File section 17 Diagnosis result file section 18 Analysis result file section 19 Display device 20 Failure analysis section

Continuation of front page (56) References JP-A-3-89179 (JP, A) JP-A-3-120485 (JP, A) JP-A-4-55776 (JP, A) (58) Fields investigated (Int .Cl. ⁷ , DB name) G01R 31/28-31/3193

Claims (8)

(57) [Claims] 1. A failure diagnosis apparatus for supplying an input pattern to a diagnosis target (1) and diagnosing a failure based on an output pattern output from the diagnosis target (1) in accordance with the input pattern. An input pattern supply means (2) for supplying a predetermined input pattern to the object to be diagnosed (1); and a failure to be assumed in advance for the object to be diagnosed (1) in accordance with the input pattern. A hypothetical fault pattern generating means (3) for generating a fault output pattern to be output from 1); a fault output pattern generated by the hypothetical fault pattern generating means (3); and the output of the diagnosis target (1). The evaluation value calculation means (4) and the evaluation value calculation means (4) for detecting a difference between each logical value with the pattern and calculating an evaluation value for each of the hypothetical faults according to the number of the differences. According to the evaluation value And a failure diagnosis means (5) for diagnosing the failure of the diagnosis target (1). 2. The evaluation value calculation means (4) sets a plurality of evaluation items for each hypothetical fault and weights each evaluation item to calculate an evaluation value for each hypothetical fault. The fault diagnosis device according to claim 1, wherein 3. The fault diagnosis apparatus according to claim 1, wherein said hypothetical fault pattern generation means (3) is a pattern for detecting a single stuck-at fault in said diagnosis target (1). 4. The apparatus according to claim 1, wherein said provisional failure pattern generation means includes storage means for preliminarily storing said failure output pattern in accordance with said input pattern. Failure diagnosis device. 5. A circuit extracting means (S4) for extracting a circuit including a fault from the diagnosis target (1) according to the output pattern. The failure diagnosis device according to the above. 6. The input pattern supply means (2) supplies an input pattern corresponding to a circuit extracted by the circuit extraction means (S4) to the diagnosis target (1). The failure diagnosis device according to the above. 7. An analysis means (20) for analyzing the object to be diagnosed (1) in accordance with a diagnosis result of the failure diagnosis means (5).
The fault diagnosis device according to any one of claims 1 to 6, further comprising: 8. The fault diagnosis apparatus according to claim 5, wherein said circuit extracting means (S4) extracts a circuit according to an analysis result of said analyzing means (20).