JP3335839B2 - Electronic circuit device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electronic circuit device, and more particularly to a semiconductor integrated circuit device such as an LSI or an IC, and more particularly to an electronic circuit device for supplying a stable clock within or between these integrated circuit devices.

[0002]

2. Description of the Related Art Recently, among electronic circuit devices, in particular, LSI
Has been developed, and an LSI operating at 500 MHz or higher has already been announced (K. Suzuk).
i et al, ISSCC94p. 214-p. 2
15). Minimizing the phase shift within the LSI and between the LSIs, that is, the clock skew is an important key for speeding up. The problematic clock skew will be described with reference to FIG. The first and second logic circuits 64 and 65 operate in synchronization with the clock signal output from the clock buffer 60 via the output terminal 61.
Is located near the clock buffer, while the wiring 62 to the second logic circuit 65 is long, for example, from end to end of the chip, the signal 61-1 received by the first logic circuit 64 Compared to the signal 63-1, the signal 63-1 received by the second logic circuit 65 is delayed due to wiring delay as shown in the figure. The phase shift Δt of this signal is called clock skew.

One of the clock skew reduction methods conventionally known is a method of compensating for a wiring delay from a clock source to a receiver to which each clock is supplied by a delay circuit which generates a delay equivalent to the wiring delay. There is. However, the wiring delay and the delay of the delay compensation circuit differ due to variations in a process such as a semiconductor manufacturing process.

That is, for example, in the manufacturing process of a semiconductor device, the resistance R is affected by the variation in resistance due to the variation in the width and thickness of the wiring and the variation in the parasitic capacitance of the wiring due to the variation in the insulating film thickness above and below the wiring. The wiring delay determined by the capacitance C varies. On the other hand, for example, if the delay circuit is constituted by a series of CMOS inverters, the delay varies due to variations in threshold voltage, current driving capability, etc. due to variations in the gate length, impurity profile, gate oxide film thickness, etc. of the MOS transistor. . Since the cause of the above-described variation in the wiring delay and the variation in the delay of the delay compensation circuit are different from each other, the delay time is different in the semiconductor device manufactured even if the delay time is adjusted in a certain semiconductor device and the clock skew occurs. As a result, the circuit may not operate normally.

[0005]

As described above, the conventional LS
In semiconductor devices such as I and IC, there is no semiconductor device capable of stably supplying a clock with respect to process variation and the like, and guaranteeing normal operation of a circuit. An object of the present invention is to provide an electronic circuit device capable of supplying a clock within an LSI or between LSIs, which solves such a conventional problem.

[0006]

The gist of the first invention of the present application is an electronic circuit device having a main system unit and a sub system unit connected to the main system unit. A forward path and a return path connected to a point and arranged adjacent to each other, and a delay path for waveform shaping disposed before the forward path are continuously present, and a clock from the clock source is provided. A signal is input to one end of the delay path, and the clock wiring is connected to an arbitrary position of the forward path, respectively.
It is also connected in the return path portion adjacent to the arbitrary position, and has an arbitrary delay amount with respect to the clock signal from the clock source based on the delay level amount between the respective clock signals at the arbitrary position. A plurality of clock supply means for supplying a clock signal is provided in at least one of the main system unit and the subsystem unit. The gist of the second invention of the present application is a clock source, which is connected at an intermediate point between the clock source and a forward path and a return path, which are arranged adjacent to each other, and a waveform shaping disposed before the forward path. And a clock line from which a clock signal from the clock source is input to one end of the delay line is connected to an arbitrary position of the forward path portion, A clock signal having an arbitrary delay amount with respect to the clock signal from the clock source based on a delay level between respective clock signals at the arbitrary position. And a plurality of clock supply means.

[0007]

[0008]

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Before describing an embodiment of the first invention of the present application, a schematic configuration of a round-trip clock wiring as a premise of the present invention will be described with reference to FIGS. FIG. 1 is a schematic configuration diagram according to a first embodiment of the present invention. 1
Is a clock signal input terminal, and reference numerals 2 and 3 are wirings for transmitting the clock signal. In particular, 2 is a forward wiring, and 3 is a return wiring. Reference numeral 4 denotes a terminal, and reference numeral 5 denotes a turning point corresponding to a middle point of the wiring. 6-1 is a first input terminal of the first receiver 8 and is characterized in that it is connected to the outgoing wiring 2. 6-2 is a second input terminal of the first receiver and has a first input terminal. It is characterized in that it is connected to the return wiring in the physical vicinity of the input terminal 6-1. The receivers 8 and 14 are composed of phase detectors 11 and 17 and variable control delay circuits 9 and 10 and 15 and 16 respectively connected in series in pairs.

Next, the state of signals at the signal input terminals 6-1 and 6-2 will be described with reference to FIG. Where Ta
Is a delay time from the input terminal 1 of the clock to the turning point 5, and Tb is a delay time from the input terminal 1 to the first input terminal 6-1 of the receiver. Therefore, the signal at 6-1 is delayed by Tb from the input of the clock. For the second input terminal 6-2 point, the delay time from the turning point 5 to the end point 4 is equal to the time Ta from the input terminal 1 to the turning point 5 and from the second input terminal 6-2 point to the end point 4 Is equal to Tb because the second input terminal 6-2 is physically near the 6-1 first input terminal. Therefore, 6
The delay at the point -2 is 2XTa-Tb. 6-1 point Tb 6-2 points 2Ta-Tb Accordingly, if the average of the delay times of the 6-1 points and 6-2 points is obtained, the average value becomes (2Ta-Tb + Tb) / 2 = Ta, and Tb
, Ie, a constant value independent of the position of the input terminal. In other words, if two input terminals located physically close to each other are provided in each of the forward path and the return path, a substantially constant phase signal can be extracted from any place on the clock wirings 2 and 3. This indicates that signals of the same phase can be synthesized anywhere on the chip.

Here, another embodiment of the present invention, in which an input terminal located in the physical vicinity is provided, will be described with reference to FIG. Indeed when applied to a semiconductor device and electronic circuit devices such as LSI, a plurality through the receiver _81, 82, 8 ₃ the clock wirings 2 and 3 as shown in FIG. 3 (a) ~ (d) May be connected. In this case, the input terminal to the receiver _81, 82, 8 ₃ with respect to the clock line 2 6-1, 6-2
May be arranged on a straight line orthogonal to the clock wirings 2 and 3 as shown in FIG.
As shown in (b) and (c), they may be arranged so as to be shifted leftward or rightward by Δl ₁ and Δl ₂ as a whole. FIG. 3 (b),
In the case of (c), the wiring layout from the clock wirings 2 and 3 to the receivers 8 ₁ , 8 ₂ and 8 ₃ becomes easy.

Also, as shown in FIG.
Is not necessarily a point, and the distance between the forward path 2 and the return path 3 may be a predetermined distance L. In short, the first input terminal 6-1 and the second input terminal
It is important that the average of the clock phase or the clock delay at the input terminal 6-2 is substantially constant at any position on the clock wiring, and the physical vicinity here means one that satisfies such a positional relationship.

In FIG. 3D, L is intentionally increased, and a receiver is provided in a region surrounded by clock wirings 2 and 3.
Logic circuits can also be arranged. Further, as a modified example, when a clock signal having a phase shifted from the others is to be given to a specific logic circuit among a plurality of logic circuits,
The position of the input terminal of the specific logic circuit can be provided differently from the other input terminals. Next, a circuit for averaging the delay times will be described.

As shown in FIG. 1, the first input terminal 6-1 is
The signal is input to the variable delay circuit 9, and a variable delay circuit 12 is connected in series with the input. The sum of the delays of the variable delay circuits 9 and 12 and the phase of the signal after receiving the wiring delay of the second input terminal 6-2 are compared by the phase comparator 11, and the variable delay circuits 9 and 12 are adjusted so that the phases match. Adjust delay. Here, if the delay times of the variable delay circuits 9 and 12 are set to be equal, the output 13 of the variable delay circuit 9 has the first and second input terminals 6.
An output having an average delay time of -1 and 6-2 is obtained. Next, examples of the phase comparator and the variable delay circuit will be described.

FIG. 4 shows a phase comparator. When it is detected that both the input 31 and the input 32 have transitioned from the H level to the L level, the phase comparison is started. When the signal 32 falls first, the signal 34 becomes active, and when the signal 31 falls first, the signal 33 becomes active. Further, a period until the other signal falls is detected as a phase difference.

FIG. 5 shows an example of a variable delay circuit. If the output is delayed according to the output from the phase detector, the potential generator switch 37 for the variable delay circuit shown in FIG. 5A is turned on by the phase comparator output signal 33, and the output node (current modulation input).
Up 40 potential, and FIG. 5 (b) the variable delay transistor 44 ₁ of circuit delay unit, 44 _2, 44 ₃ the delay time for the current driving capability increases of decreases. On the contrary, when the output is early, the switch 38 of the potential generating circuit for the variable delay circuit shown in FIG. 5A is turned on by the output signal 34 of the phase comparator, and the potential of the output node 40 is reduced. transistor 44 ₁ of the delay section, 44 _2, 44 ₃ of the current drive capability is reduced delay increases.

As described above, the phases can be compared and the phases can be aligned. In FIG. 5A, 35 and 36 are the first.
And a second current source 39 is a low-pass filter;
5 in (b) 40 is current modulation input, 41 _1, 4
1 _2, 41 ₃ PMOS loads of each inverter, 42
_1, 42 _2, 42 ₃ nMOS driver of each inverter, 44 _1, 44 _2, 44 ₃ is a variable current source of each inverter 45 is the input of the first inverter, 46 an output of the first inverter, 47 The output of the second inverter, 48, is the output of the third inverter.

In FIGS. 4 and 5, only the NMOS side is controlled. However, it is easy to construct a complementary structure, and FIG. 6 shows an example. According to the schematic configuration of the round-trip clock wiring which is the premise of the first embodiment of the present invention described above, the wiring delay from the clock source to the receiver to which each clock is supplied can be compensated. However, in this method, it is important that the outgoing path and the return path have the same wiring delay and phase shift, respectively.Strictly speaking, in order to transmit the forward path signal to the return path, compared to the input signal waveform of the forward path, Adjustment of the phase may be difficult as a result of the waveform of the input signal on the return path being distorted.

That is, as shown in FIG. 7, although the same drive buffers 21 and 22 and the same clock lines 2 and 3 are used in FIG. On the other hand, the input waveform of the buffer 21 on the return path is a waveform which is distorted on the outward path 2. In other words, the output is different because the input waveform is different for the same configuration. As shown in the figure, the delay between the input 1 and the turning point 5 and the delay from the turning point 5 to the terminal 4 may be different. If the delays differ greatly, a receiver that operates by detecting the phases of the forward path and the return path cannot output a normal output, and in the worst case, there is a problem that the operation phase of the logic circuit shifts and malfunctions.

In order to solve such a problem, the configuration of the first embodiment of the present invention described below can be adopted. FIG. 8 is a schematic configuration diagram showing a first embodiment of the first invention of the present application.

Reference numeral 1 denotes a clock signal input terminal.
Reference numerals 2 and 3 are clock wires for transmitting a clock signal.
In particular, 26 is a first outward wiring, 2 is a return wiring, and 3 is a second outward wiring. Reference numeral 4 denotes a terminal, reference numeral 27 denotes a first turning point, and reference numeral 5 denotes a second turning point. 6-1 is a first input terminal of the first receiver 8 and is characterized by being connected to the return path 2. 6-2 is a second input terminal of the first receiver 8.
Of the second forward path 3 in the physical vicinity of 6-1.
It is characterized by being connected to

The receiver 8 comprises a phase detector 11 and a set of variable control delay circuits 9 and 10. Phase detector (comparator) 1
1 and 17 and the variable delay circuits 9, 10, 15, and 16 may have the same configuration as that described with reference to FIGS. 4 to 6, and thus a detailed description thereof will be omitted. Further, another receiver 14 having the same configuration and connected to the input terminals 7-1 and 7-2 is provided.

Next, the state of signals at the signal input terminals 6-1 and 6-2 will be described with reference to FIG. Here, Ta is a delay time from the input to the turning point, and Tb is a delay time from the second turning point to the first input terminal of the receiver. Therefore, the signal at 6-1 is delayed by 2Ta-Tb, and the signal at 6-2 is delayed by 2Ta + Tb. 6-1 point 2Ta-Tb 6-2 points 2Ta + Tb Therefore, if the average of the delay times at points 6-1 and 6-2 is averaged, the average value is (2Ta-Tb + 2Ta + Tb) / 2 = 2Ta, which is constant regardless of position, that is, Tb. Value. This indicates that signals of the same phase can be synthesized anywhere on the chip.

In the first embodiment, the result of the waveform shaping by the outgoing path 26 is input to the inbound path 2.
6 in that the output whose waveform has been shaped in the return path 2 is input to the second forward path 3. That is, since the delays of 2 and 3 also have the same or nearly the same waveforms through the wiring 26, the output delays can be equalized.

Here, the outward path 26 of the first embodiment basically has no positional information and only waveform shaping, so that it can be realized, for example, by making the wiring meandering to have the same length as a modification. . However, it is the first embodiment that is more resistant to process variations due to local interlayer insulating film variation and the like.

Next, FIG. 10 shows a second embodiment according to the first invention of the present application. The difference from the first embodiment is that a buffer 28 for driving the forward path, a buffer 29 for driving the return path, and a buffer 30 for driving the second forward path are provided. Here, the buffer circuit is, for example, one in which a plurality of ordinary CMOS inverters are connected in series, a current mirror type operational amplifier, or the like. As in the first embodiment, the design is made such that the forward path delay (correctly, the delay in the buffer plus the wiring delay) and the return path (correctly, the delay in the buffer plus the wiring delay) are equal. This configuration is preferable when the deterioration of the propagation waveform becomes a problem particularly with a long wiring compared to the first embodiment.

In this embodiment as well, the forward path 26 basically has no positional information and only performs waveform shaping, so that it can be realized, for example, by meandering to the same length. However, it is the second embodiment that is more resistant to process variations due to local interlayer insulation film variation and the like.

Next, FIG. 11 shows a preferred use example of the first invention of the present application. One round trip half wiring (or one half round buffer and wiring) is provided at substantially the center of the semiconductor chip 61, and a set of logic circuits 60a, 60b, 60c and receivers 8a, 8b, 8c whose phases are to be matched is formed in the chip 61. Arrange multiple units. By wiring in the center of the chip, it is possible to arrange such that it is easy to supply a substantially uniform clock to the entire chip.
In the embodiment of FIG. 11, the clock input is provided at the chip end, but the clock input may be started from the center of the chip and wired to the left and right of the chip from there. Furthermore, the first invention of the present application can be applied not only to a semiconductor chip but also to a board on which a plurality of LSI chips as shown in FIG.

FIG. 12 shows an embodiment of the second invention of the present application. This embodiment is significantly different from the previous ones.
The conventional one is basically provided with a waveform shaping input section for the round-trip wiring, but in this embodiment, two clocks having substantially the same wiring width from one clock source 70 on a substrate such as a chip are provided. Are provided in two directions, clockwise and counterclockwise. As a result, buffers 71 and 72 for driving any of the wirings 73 and 74 can output sharp waveforms.
And the waveform shaping as in the previous embodiments is not required. The delay of one round of the wiring is Tc, and the buffer 71 of the clockwise wiring 73 is connected to the receiver input 75
Assuming that the delay up to −2 is Td, the delay from the buffer 72 to the receiver input unit 75-1 is estimated to be Tc−Td. , A clock that does not depend on the location can be obtained. The receivers 77 and 78 may have the same configuration as the receiver of FIG. 1 described above.

FIG. 13 shows another embodiment of the second invention of the present application. The wiring is formed on the outer periphery of the LSI chip 80 as in the above embodiment. Thus, the phase can be adjusted regardless of the location on the chip, and a clock having no phase difference can be supplied to a plurality of circuits 79 such as logic circuits.

FIG. 14 shows a second embodiment of the second invention of the present application. This embodiment is an electronic circuit device including a main system unit 90 and a subsystem unit 92 connected to the main system unit 90 via a coupling unit 91.
In this embodiment, the subsystem 92 includes a main memory 93, a cache memory 94, and a logic circuit 95, each of which is provided by a single clock source as in the embodiment shown in FIG. Two lock wires 96 arranged in two directions, clockwise and counterclockwise.
a, 96b via receivers 97a, 97b, 97c.

According to such a configuration, a stable clock can be supplied to each integrated circuit device between integrated circuit devices having different functions. In this embodiment, an example in which the second invention of the present application is applied to a subsystem unit has been described.
4 may be applied to the main system unit 90. Further, the present invention may be applied to both the main and sub system units 90 and 92.

The main system section 90 includes an electronic circuit group 98 for achieving a predetermined function, such as a communication device, an image device, and a memory device. In FIG. 14, the clock is input to all the logic circuits and memories, but a part of the logic circuits and memories may be selectively used. Furthermore, when it is desired to operate the circuit on the subsystem 92 side faster than the circuit on the main system section 90 side, the clock on the main system section 90 side is made n times (n> 1) via an oscillator or the like. It can be realized by supplying it as a clock source of the subsystem 92. If the same clock is supplied to both the system units 90 and 92, the oscillator or the like need not be provided.

Next, another application example of the second invention of the present application is shown in FIG.
5 (a) and 5 (b). FIG. 15A shows an example in which a plurality of clockwise and counterclockwise pairs of clock wirings are provided on the base 100, in this case, two pairs 101a and 101b are provided. FIG. Clockwise and counterclockwise two clock wires 102a and 102 are provided in the upper central portion.
14B is an example in which various circuits 103 such as a logic circuit memory are disposed in a smaller area than in FIG. 14 or FIG. 15A. Here, the base 100 may be considered as an LSI chip or a board on which a plurality of LSI chips are mounted. For example, as shown in FIG. 14, the board may be considered as a board equipped with a main memory, a cache memory, and a logic circuit (such as a CPU). As described above, the arrangement of the clock wiring according to the present invention can be appropriately changed and implemented according to the layout of various circuits such as a logic circuit and a memory on the base 100. Also, FIGS.
In FIG. 15, an input clock buffer is provided for each of clockwise and counterclockwise clock wirings, but these are shared to form a single buffer, and its output is branched and wired. Is also good.

In the above-described first and second embodiments of the present invention, a single wiring clock is supplied. However, even when a clock is supplied by two wirings having complementary signals, two clocks are supplied.
The same phase matching effect can be obtained by combining books as one set and wiring the set.

Further, a Vcc line or a Vss line may be provided on the left and right or upper and lower sides of the clock wiring, respectively, and may be shielded from being affected by noise from an adjacent wiring.

[0037]

As described above, according to the present invention, a synchronized clock can be supplied to distributed circuits regardless of the positions of the circuits. Further, in the present invention, since the wiring delay is detected by the wiring delay, the effect does not deteriorate due to the process variation.

[Brief description of the drawings]

FIG. 1 is a schematic configuration diagram for explaining the outline of the present invention.

FIG. 2 is an explanatory diagram for explaining an outline of the present invention.

FIG. 3 is an explanatory diagram for explaining the outline of the present invention.

FIG. 4 is a circuit diagram of a phase comparator used in the embodiment of the present invention.

FIG. 5 is a circuit diagram of a variable delay circuit used in an embodiment of the present invention.

FIG. 6 is a circuit diagram of another variable delay circuit used in the embodiment of the present invention.

FIG. 7 is an explanatory diagram for explaining an embodiment of the first invention of the present application.

FIG. 8 is a schematic configuration diagram showing an embodiment of the first invention of the present application.

FIG. 9 is an explanatory diagram for explaining the first embodiment of the first invention of the present application.

FIG. 10 is a schematic configuration diagram showing a second embodiment of the first invention of the present application.

FIG. 11 is a schematic configuration diagram for explaining a usage example of the first invention of the present application.

FIG. 12 is a schematic configuration diagram showing one embodiment of the second invention of the present application.

FIG. 13 is a schematic configuration diagram showing an embodiment of the second invention of the present application.

FIG. 14 is a schematic configuration diagram showing a usage example of the second invention of the present application.

FIG. 15 is a schematic configuration diagram showing another application example of the second invention of the present application.

FIG. 16 is an explanatory diagram for explaining a conventional problem.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Signal input terminal, 2 ... Return path, 3 ... Second outward path, 4 ... Terminal, 5 ... Return point, 6-1 ... First of first receiver
6-2... Second input terminal of the first receiver, 7-1... First input terminal of the second receiver, 7-
2 ... second input terminal of second receiver, 8 ... first receiver, 9 ... first variable delay circuit of first receiver, 10 ... second variable delay circuit of first receiver, 11 ... Phase detection circuit of first receiver, 12: output of phase detection of first receiver, 13: output of first receiver, 14: second receiver, 15: first variable delay circuit of second receiver , 16: second variable delay circuit of second receiver, 17: phase detection circuit of second receiver, 18: output of phase detection of second receiver, 19: output of first receiver, 26: waveform Shaper (first outgoing path), 27 ... turning point

Continuation of front page (56) References JP-A-8-54957 (JP, A) JP-A-4-229634 (JP, A) JP-A-4-205326 (JP, A) JP-A-3-142553 (JP) JP-A-6-96001 (JP, A) JP-A-57-79536 (JP, A) JP-A-4-196462 (JP, A) JP-A-2-51252 (JP, A) JP-A-8-181586 (JP, A) JP-A-7-230336 (JP, A) JP-A-6-236922 (JP, A) JP-A-5-268206 (JP, A) A) JP-A-5-12223 (JP, A) JP-A-3-289813 (JP, A) JP-A-9-97123 (JP, A) JP-A 64-27722 (JP, U) −512935 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) G06F 1/10 H04L 7/00 H03K 5/00 H03K 19/0175 H01L 21/82 H01L 27/04

Claims (10)

(57) [Claims] 1. An electronic circuit device having a main system unit and a subsystem unit connected to the main system unit, wherein the clock source and the clock source are connected to an intermediate point of each other and arranged so as to be adjacent to each other. A clock path in which a forward path section, a return path section, and a delay path for waveform shaping arranged before the forward path section are continuously present, and a clock signal from the clock source is input to one end of the delay path And connected at an arbitrary position on the outward path, and also connected at the return path adjacent to the arbitrary position, based on a delay level between respective clock signals at the arbitrary position, A plurality of clock supply means for supplying a clock signal having an arbitrary delay amount with respect to a clock signal from a clock source; An electronic circuit device is provided in at least one of the subsystem units. 2. A forward path section and a return path section which are connected to a clock source at an intermediate point of each other and are disposed adjacent to each other, and a delay path for waveform shaping disposed at a stage preceding the forward path section. A clock line that exists continuously and is connected to a clock line from which a clock signal from the clock source is input to one end of the delay path at an arbitrary position on the outward path, and is adjacent to the arbitrary position. A plurality of clock supplies, which are also connected in the return path and supply a clock signal having an arbitrary delay amount with respect to the clock signal from the clock source based on the delay level between the respective clock signals at the arbitrary position. And an electronic circuit device. 3. A first input terminal connected to an arbitrary position on the outward path, a second input terminal connected to the return path adjacent to the arbitrary position, and one end of the first input terminal connected to the first input terminal. Two variable control delay circuits connected in series to an input terminal, the other end of which is connected to a phase comparator, for arbitrarily delaying a clock signal input from the first input terminal, and the second variable control delay circuit; A phase difference between a clock signal connected to an input terminal and input from the second input terminal and a clock signal delayed by the two variable control delay circuits is detected, and the two variable signals are detected in accordance with the phase difference. For the control delay circuit,
The electronic circuit device according to claim 1, further comprising a phase comparator that supplies a control signal for changing a delay amount. 4. The phase comparator supplies a control signal for changing a delay amount in the two variable control delay circuits so that the phase difference becomes 0 (zero). An electronic circuit device according to claim 1. 5. The electronic circuit device according to claim 1, wherein the delay path, the forward path section, and the return path section each have one input terminal connected to a drive buffer. 6. The electronic circuit device according to claim 1, wherein the clock wiring extends to a center of the main system unit or the sub system unit. 7. The clock line according to claim 1, wherein the clock line has two signal lines for supplying complementary signals.
Or the electronic circuit device according to 2. 8. The electronic circuit device according to claim 1, further comprising a power supply wiring Vcc and a power supply wiring Vss arranged in parallel with said clock wiring. 9. An oscillator for supplying a clock signal having a frequency n times (n> 1) of a clock signal of the main system unit or the sub-system unit to the main system unit or the sub-system unit. The electronic circuit device according to claim 1, wherein 10. The electronic circuit device according to claim 1, wherein a plurality of driving buffers are inserted at equal intervals in each of the clock wirings.