JP3482994B2 - Time code signal reader - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a time code signal reading device, and more particularly to a time code signal reading device for detecting a time code signal specifying a position of a video signal recorded on various recording media.

[0002]

2. Description of the Related Art In order to edit a video signal between an audio device which is an external device and another video device using a commercial video device, it is necessary to synchronize with each other. Usually, the signal required for this synchronization is recorded at a predetermined position of the video signal. This sync signal is used by the Society of Motion Picture and Television E
ngineers: Hereinafter abbreviated as SMPTE. ) And the European Broadcasting Union (EBU), respectively, and NTSC (National Televi)
sion System Committee) method and PAL (Phase Alt)
The signal format is defined as a time code (Longitudinal Time Code: hereinafter abbreviated as LTC) of the color image system of the “Ernation by Linecolor” system.

FIG. 7 and FIG. 8 show the outline of the structure of the LTC signal format of the NTSC color video signal defined by SMPTE. Figure 7
The format structure from the 0th bit to the 39th bit of the LTC signal is shown. FIG. 8 shows a format structure of the LTC signal from the 40th bit to the 79th bit. LT
The C signal is "BIT N" per frame of the video signal.
o. It is recorded in an 80-bit format from bit number 0 to address 79 indicated by "." In such an LTC signal, information to be arranged is determined for each one bit or a plurality of bits in advance.
For example, "FRAMS UN that specifies the number of frame units
ITS "is represented by 4 bits from bit number 0 to address 3. Also, bit number 64 to number 7
16 bits up to address 9 are synchronization words (SYNCHRONIZIN
G WORD BINARY BIT), "0011111111
A fixed pattern composed of 111101 ″ is arranged. The remaining 64 bits from bit number 0 to address 63 differ depending on the time information indicated by the LTC signal.

FIG. 9 and FIG. 10 show the outline of the structure of the LTC signal format of the PAL system color video signal specified by EBU. Figure 9 shows LT
The format structure from the 0th bit to the 39th bit of the C signal is shown. FIG. 10 shows a format structure from the 40th bit to the 79th bit of the LTC signal. The LTC signal in this system is also recorded in an 80-bit format from bit number 0 to address 79 indicated by "BIT No." per frame of the video signal. In particular, the 16 bits from the bit number 64 to the address 79 are the same as the sync signal (SYNCHRONIZINGWORD BINARY B) as in the LTC signal defined by SMPTE.
As IT), a fixed pattern composed of "0011111111111101" is arranged.

In such an LTC signal, a signal transition occurs at the start point in each bit period, and the bit value is recorded by the biphase mark modulation method. The bi-phase mark modulation method is a digital modulation in which when the bit value is "1", it is inverted at the center of the bit, and when the bit value is "0", it is not inverted at the center of the bit and is inverted at the bit value boundary. It is a type of method. Therefore, after the bi-phase mark demodulation, the above-mentioned fixed pattern is detected by the LTC signal reading device, whereby the time information specified by 64 bits from bit number 0 to address 63 is discriminated. This time information specifies the absolute position in the entire video signal by "hour / minute / second" and "frame".
Using the specified time information, various editing operations can be performed at the absolute position of the video signal recorded on the tape-shaped recording medium, for example.

[0006] A conventional L reading such LTC signal
The TC signal reader has a phase locked loop (Phase Locked).
Loop: Hereinafter, abbreviated as PLL. ) An LTC detection circuit for detecting an LTC signal from a signal whose phase is adjusted by the circuit,
A general-purpose microcomputer for discriminating time information from the LTC signal detected by the LTC detection circuit is provided. Further, for example, Japanese Patent Application Laid-Open No. 10-289535, "Time Code Signal Reading Device" discloses a technique relating to an LTC signal reading device that measures the pulse value by measuring the pulse width of all 80-bit LTC signals. ing. In this LTC signal reading device, attention is further paid to the continuity of time information to determine whether or not there is an error in the read LTC signal, and thus a large scale integrated circuit (hereinafter abbreviated as LSI). Higher speed general-purpose CPU (Central Processing U
nit: Hereinafter, abbreviated as CPU. ) Is used to disclose a technique with higher accuracy and improved reliability.

[0007]

However, the conventional L
Since the TC signal reading device has a complicated and expensive PLL circuit, it has a problem that the circuit configuration is complicated and the cost is increased. On the other hand, the technique disclosed in Japanese Patent Laid-Open No. 10-289535 makes it possible to read LTC signals with high accuracy and improved reliability by software processing using a general-purpose CPU that is faster than a dedicated LSI. However, in the pulse width measurement for determining each bit value of the detected LTC signal, the interrupt processing is performed by the edge detection up to twice for each bit.
That is, interrupt processing is required up to twice at the rising edge and the falling edge for each bit.
Therefore, a maximum of 16 for 80-bit LTC signals
There is a problem that the interrupt process must be performed 0 times, which limits the speedup due to the overhead at the time of interrupt.

SUMMARY OF THE INVENTION An object of the present invention is to provide an LTC signal reading device which can detect an LTC signal at low cost and at high speed.

[0009]

According to a first aspect of the present invention, there are provided: (a) first edge detecting means for detecting both rising and falling edges of a time code including predetermined time information; ) A pulse width measuring means for measuring the pulse width between both edges detected by the first edge detecting means, (c) a pulse width storing means for storing the pulse width, and (d) a first edge detecting means. Transfer request sending means for sending a transfer request each time both edges are detected by (e), and (e) the pulse width measured by the pulse width measuring means on the basis of the transfer request sent by the transfer request sending means. The pulse width storage means for transferring to the storage means for storage and (f) the transfer request sending means
The pulse width storage means responds to the transmitted transfer request.
The number of times the data was transferred was exceeded the predetermined number.
When a transfer end interrupt request is sent When a transfer end interrupt request is sent
Means, (g) second edge detecting means for detecting an edge of a predetermined frame synchronizing pulse signal, and (h) when an edge of the frame synchronizing pulse signal is detected by the second edge detecting means , or transfer End interrupt request transmission means
Bit value discriminating means for discriminating the bit value of each pulse width stored in the pulse width storing means and receiving the time information including the time code when the transfer end interrupt request sent by And the time code signal reading device.

That is, according to the first aspect of the present invention, the pulse width measuring means determines the pulse width between the rising and falling edges of the time code including the predetermined time information detected by the first edge detecting means. taking measurement. Then, each time the transfer requesting means detects the both edges by the first edge detecting means, a transfer request is sent out, and the pulse widths measured by the pulse width storing means are sequentially transferred to the pulse width storing means and stored therein. I chose After that, each time the second edge detecting means detects an edge of a predetermined frame synchronization pulse signal, the pulse width from the pulse width corresponding to each bit value of the time code for each frame transferred to the pulse width storage means is changed to each pulse width. The bit value of is determined and the time information including the time code is acquired.
In the invention according to claim 1, the transfer end interrupt request sender
A step is provided and is sent by the transfer request sending means.
It is transferred by the pulse width storage means in response to the transfer request.
When the number of times of transfer exceeds a predetermined number, the transfer is completed.
The end interrupt request is transmitted. In addition, a bit
This transfer end interrupt request or the second value is determined by the value determining means.
The edge of the frame sync pulse signal is detected by
When detected, each parameter stored in the pulse width storage means
When the time code is included by distinguishing the bit value of the loose width
I try to get the information. By this, 1x speed
Of the pulse width corresponding to the time code input over
LT at the maximum interval without overflowing the storage area
The C signal can be discriminated and the delay caused by the processing can be reduced.
Can be kept to a minimum.

[0011]

[0012]

[0013] In the second aspect of the present invention, a time code signal reading apparatus according to claim 1, wherein the pulse width measuring means includes a counting means for counting a clock of a predetermined frequency, time code by the first edge detecting means Holding means for holding the count value counted by the counting means when a rising or falling edge is detected, and the pulse width storage means stores the count value held in the holding means on the basis of the transfer request. It is characterized by being transferred to and stored in.

That is, in the invention described in claim 2 , the number of clocks of a predetermined frequency counted by the counting means
Holding means for expressing the pulse width between both edges and for holding the count value counted by this counting means when both edges of the time code are detected by the first edge detecting means. Then, the pulse width storing means transfers the data to the pulse width storing means. As a result, the pulse width corresponding to the bit value of the time code can be accumulated with a very simple configuration, which can contribute to speeding up of the time code discrimination processing.

[0015] In the present invention of claim 3, wherein, in the time code signal reading apparatus according to claim 2, wherein the first edge detecting means, characterized in that initializing the count value of the counting means each time the both edges are detected I am trying.

That is, according to the third aspect of the invention, the count means for measuring the pulse width of the time code initializes the count value each time both edges are detected. Therefore, the structure is very simple. It becomes possible to continuously measure the pulse width corresponding to the bit value of the time code.

[0017] In the invention of claim 4, claims 1
In the time code signal reading device as described in any one of the items 3 , the pulse width storing means is constituted by a direct memory access controller.

That is, according to the fourth aspect of the invention, since the pulse width is sequentially stored by using the direct memory access controller, the hardware scale can be reduced and the cost can be reduced.

[0019]

DETAILED DESCRIPTION OF THE INVENTION

[0020]

EXAMPLES The present invention will be described in detail below with reference to examples.

FIG. 1 shows an LTC according to an embodiment of the present invention.
1 is a diagram showing an outline of a configuration of a signal reading device. The LTC signal reading device 10 according to the present embodiment includes a CPU 12 and a read only memory (Read Only Me) via a bus 11.
mory: Hereinafter abbreviated as ROM. ) 13, Random Access Memory (hereinafter abbreviated as RAM) 14, Interrupt Controller (INTerrupt Contro)
ller: Abbreviated as INTC hereinafter. ) 15, synchronization detection circuit 1
6 and the LTC signal detection circuit 17 are connected to each other.

The CPU 12 can sequentially read and execute a predetermined LTC signal read control program stored in the ROM 13.

The ROM 13 stores in advance an LTC signal reading control program as a control program in the LTC signal reading device of this embodiment.

The RAM 14 is a ROM by the CPU 12.
The midway processing result and the processing result by the execution of the LTC signal reading control program stored in 13 are a work area in which writing or reading is appropriately performed. The RAM 14 in the present embodiment has a count value array of pulse widths of LTC signals detected by the LTC signal detection circuit 17,
A pointer for designating the address of the pulse width count value array is stored.

The INTC 15 is an interrupt request signal 1 input from the synchronization detection circuit 16 and the LTC signal detection circuit 17.
8 and 19 output to CPU 12 as an interrupt processing request 20. When the INTC 15 is preliminarily input by the interrupt request signals 18 and 19 in advance, it is determined which is given priority to request the CPU 12 for interrupt processing. The INTC 15 uses the interrupt request signals 18 and 1
When 9 is received, it is output to the CPU 12 as an interrupt processing request 20 for identifying only one of them.

The synchronization detection circuit 16 includes a first timer control unit (hereinafter, abbreviated as TCU) 21. The first TCU 21 has an edge detector 23 that detects a falling edge of a frame sync pulse 22 that is input in a frame unit of a video signal from an external device (not shown), and a predetermined clock signal generated by an external clock generator (not shown). A timer unit 24 that counts a frequency clock and a capture register 25 that holds the count value counted by the timer unit 24 when a predetermined edge is detected by the edge detector 23 are provided. Such a synchronization detection circuit 16 counts the cycle of the frame synchronization pulse 22 with a clock of a predetermined frequency generated by an external clock generator input to the timer unit 24 with reference to the input frame synchronization pulse 22. To do. The count value held in the capture register 25 corresponds to the frame cycle, and the frame cycle has the NTSC system (33.3 ms) and the PAL system (40 m).
s), the value obtained by dividing the frame period by 320 is used as the reference value for LTC bit detection.

The LTC signal detection circuit 17 includes a second TCU.
26 and the direct memory access controller (Direct Mem
ory Access Controller: hereinafter abbreviated as DMAC. ) 2
7 and 7. The second TCU 26 receives the input L
A predetermined edge is detected by the edge detector 29 that detects the rising edge and the falling edge of the TC signal 28, the timer unit 30 that counts the same clock as the clock input to the timer unit 24, and the edge detector 29. A capture register 31 that holds the count value counted by the timer unit 30 is provided. Further, the edge detector 29 sends out a DMA transfer request 32 to the DMAC 27 when detecting a rising edge and a falling edge of the input LTC signal 28.

The DMAC 27 receives a DMA transfer request 32 and performs a priority control with other transfer requests, and a register control unit for controlling registers for which a predetermined transfer setting is performed by the CPU 12. 34
And a bus interface unit 35 that performs predetermined transfer control instead of the CPU 12. In the DMAC 27 having such a configuration, the transfer source initial address, the transfer destination initial address, the transfer size, and the transfer count are set in advance by the CPU 12. The initial address of the transfer source or the initial address of the transfer destination is not limited to the memory address of the RAM 14, but an I / O (Input / Output: hereinafter abbreviated as I / O) device connected to the bus 11 is specified. O address can be set. here,
An I / O address that specifies the capture register 31 of the second TCU 26 is set as the transfer source initial address. A predetermined memory address for accumulating the transferred data in the RAM 14 is set as the transfer destination initial address. As the transfer size, for example, a data size which is a transfer unit of the data held in the capture register 31 is set. The number of transfers is set to the number of transfers required to transfer all the data that can be held in the capture register 31.

Further, the register control unit 34 sends an interrupt request signal 19 indicating a DMA transfer end interrupt processing request to the INTC 15 when the preset number of transfers within the frame synchronization pulse is exceeded. You can do it.

Such a DMAC 27 has a second TCU.
When the DMA transfer request 32 is received from 26, the request priority control unit 33 outputs a DMA transfer start pulse.
Register control unit 34 to which the DMA transfer start pulse is input
Sends a transfer request signal (not shown) to the CPU 12. Then, the transfer approval signal corresponding to the transfer request signal is received from the CPU 12, and the CPU 12 receives the bus 1 signal.
When the control right of 1 is transferred, the DMAC 27 independently outputs a bus control signal from the bus interface unit 35 to the capture register 31 that is the transfer source and the RAM 14 that is the transfer destination, and holds it directly in the capture register 31. The specified data is transferred in the transfer size unit set in advance for the number of times of transfer.

Such an LTC signal reading device includes, for example, a so-called single-chip RISC (Reduced Instruction Set Compute) including a plurality of TCUs and a DMAC.
r) can be realized.

The operation of the LTC signal reader according to this embodiment will be described below.

First, from the CPU 12 through the register control unit 34 of the DMAC 27 of the LTC signal detection circuit 17, D
The second timer 2 is added to the transfer source initial address and the transfer destination initial address, which are DMA transfer control registers of the MAC 27.
6, the I / O address for specifying the capture register 31 and the start address of the pulse width count value array of the RAM 14 are set. In addition, D which is a DMA transfer control register
The MA transfer size is set to a data unit corresponding to the size of each array, and is a DMA transfer control register DMA.
The number of transfers is set to 160 times corresponding to the size of the pulse width count value array.

The LTC signal detection circuit 17 has L converted into a binary pulse waveform through a waveform shaping circuit (not shown).
The TC signal 28 is input. In the LTC signal detection circuit 17, the edge detector 29 of the second TCU 26 is
A rising edge or a falling edge of the C signal 28 is detected. Each time these edges are detected by the edge detector 29, a latch pulse is sent to the capture register 31 and a clear pulse for initializing the timer section 30 is sent. Timer unit 30
Counts a clock of a predetermined frequency generated by a clock generator (not shown), and the edge detector 2
When the clear pulse is received from 9, the count value counted by the timer unit 30 is supplied to the capture register 31. When receiving the latch pulse from the edge detector 29, the capture register 31 holds the count value supplied by the timer unit 30. Thus, the count value held in the capture register 31 becomes the pulse width count value of the LTC signal 28.

The edge detector 29 is the LT detector described above.
Every time the rising edge or the falling edge of the C signal is detected, the DMA transfer request signal 32 is sent to the DMAC 27.

Upon receiving the DMA transfer request signal 32 from the edge detector 29 of the second TCU 26, the request priority control unit 33 of the DMAC 27 gives the highest priority to the register control unit 34 according to the preset priority setting information. Request the DMA transfer. Where the second TCU 26
Assuming that the DMA transfer request signal 32 from the edge detector 29 has the highest priority, the register control unit 34 activates the DMA transfer, and the second TCU 26 is activated according to the DMA transfer control register set to a predetermined value. The pulse width count value held in the capture register 31 of
DMA transfer is performed to a memory address indicating the pulse width count value array of M14. After this transfer, the register control unit 34
Causes the transfer destination address to be increased by the transfer size.

FIG. 2 shows an outline of the configuration of the pulse width count value stored in the RAM 14. RAM
14 shows the capture register 3 for each pulse detected by the edge detector 29 as shown in FIG.
The count value of the timer unit 30 held by 1 is stored. The LTC signal reader 10 according to the present embodiment.
The LTC signal 28 input to is 80 bits long as shown in FIG. 7, FIG. 8 or FIG. 9 and FIG. 10, and at each bit cycle, if the bit value is “1”, it is at the center of the bit. When the bit value is inverted and the bit value is "0", it is recorded by the bi-phase mark modulation method as a digital modulation method that is not inverted at the center of the bit but is inverted at the bit value boundary, so a maximum of 160 pulse width count values Since 0 is stored, addresses 0 to 159 are reserved. The pulse width count value at each of these addresses is referenced using the buffer pointer shown in FIG. The address of the pulse width count value array is designated in this buffer pointer. For example, by designating "2" in the buffer pointer as shown in FIG. 9B, it is possible to access the second address of the pulse width count value array.

As described above, each time the rising edge or the falling edge of the LTC signal is detected, the buffer pointer indicating the reference address of the pulse width count value array is incremented, and the pulse width count value indicating the pulse width of the LTC signal is sequentially obtained. Are transferred from the capture register 31 and accumulated.

The LTC signal 28 is the LTC signal detection circuit 17
On the other hand, the frame sync pulse 22 is detected by the sync detection circuit 16 for each frame of the video signal.

The edge detector 23 in the first TCU 21 of the sync detection circuit 16 detects the falling edge of the frame sync pulse 22. The edge detector 23 sends a latch pulse to the capture register 25 and a clear pulse for initializing the timer unit 24 each time the falling edge of the frame synchronization pulse 22 is detected. The timer unit 24 counts a clock of a predetermined frequency generated by a clock generator (not shown), and when receiving a clear pulse from the edge detector 23, supplies the count value counted by the timer unit 24 to the capture register 25. To do. When receiving the latch pulse from the edge detector 23, the capture register 25 holds the count value supplied by the timer unit 24. In this way, the count value held in the capture register 25 becomes the cycle of the frame synchronization pulse 22.

The edge detector 23 detects the falling edge of the frame sync pulse 22 every time it detects IN.
The interrupt request signal 18 is sent to the TC 15 and the CPU
The discrimination processing of the input LTC signal by 12 is performed. That is, the LTC signal is discriminated for each frame of the video signal to acquire the time information. Furthermore, from the register control unit 34 of the DMAC 27 of the LTC signal detection circuit 17, when the preset number of DMA transfers is exceeded, an interrupt request signal 19 is sent to the INTC 15 as a DMA transfer end interrupt processing request, The CPU 12 is caused to perform the discrimination processing of the input LTC signal. The DMA transfer end interrupt processing request is 1 for the video signal when the speed is 1 ×.
This does not occur because the DMA transfer count is initialized every time the frame synchronization pulse 22 is input in frame units. However, if it exceeds 1x speed, RAM1
It is generated in order to avoid accumulation of pulse width count values that are equal to or larger than the pulse width count value array provided in FIG.

FIG. 3 shows an outline of the processing contents of an example of the LTC signal reading control program stored in the ROM 13 which carries out the discrimination processing of the input LTC signal by such an interrupt request signal. First, the CPU 12 detects the falling edge of the frame sync pulse 22 notified via the INTC 15 in response to the interrupt request signal 18 or DMA notified via the INTC 15 in response to the interrupt request signal 19. When the interrupt process is activated by any of the transfer end interrupt requests, first, the bit value of the input LTC signal is determined (step S40).

In step S40, the CPU 12
Input LTC temporarily stored in the capture register 31 in the second TCU 26 of the LTC signal detection circuit 17
The pulse width count value of the signal 28 determines the bit value of the input LTC signal for each address data of the pulse width count value array transferred to the RAM 14 by the DMAC 27. That is, when the pulse width count value when the bit value is “0” is T, “0.75 × T” is used as the threshold value, and the next pulse width count value is “0.75 × T”.
When it is shorter than T ", the bit value is judged as" 1 ",
When it is longer than “0.75 × T”, the bit value is judged to be “0”. When the pulse width count value when the bit value is “1” is T ′, “0.75 × T ′” is set as the threshold value and the next pulse width count value is “0.
When it is shorter than 75 × T ′ ”, the bit value is determined as“ 1 ”, and when it is longer than“ 0.75 × T ′ ”, the bit value is determined as“ 0 ”. Only when it is determined that the bit value is “1” is the bit value “1”.
Is confirmed.

FIG. 4 shows the relationship between the input LTC signal and the pulse width count value. FIG. 7A shows the LTC signal 28 converted into a binary pulse waveform through a waveform shaping circuit (not shown). FIG. 11B shows a pulse width count value array in which the pulse width count values between the rising edge and the falling edge of the LTC signal 28 are stored. By thus detecting the rising edge and the falling edge of the LTC signal 28, the pulse width count value is stored for each pulse width. Here, the count value "T" is assigned to addresses 0 and 1, the count value "2T" is assigned to address 2, the count value "T" is assigned to addresses 3 and 4, and the count value "2T" is assigned to address 5. Is stored.

For example, as shown in FIG.
2 is when the bit value at address 1 is set to “1”,
Since the pulse width count value at address 2 is longer than “0.75 × T”, it is determined that the bit value is “0”. Also,
Since the pulse width count value of address 3 is shorter than 0.75 times the pulse width count value of address 2 which is set to “0”,
It is determined that the bit value is "1".

A technique relating to such a bit value discrimination process is disclosed in, for example, Japanese Patent Laid-Open No. 10-289535.

Returning to FIG. 3, the description will be continued. As described above, after determining the bit value of the LTC signal in step S40, the CPU 12 extracts the time information of the time code (step S41). That is, the format-configured LTC signal shown in FIG. 7, FIG. 8, FIG. 9, or FIG. get. After that, the register control unit 34 of the DMAC 27
On the other hand, the transfer destination address of DMA transfer and the number of transfers are initialized (step S42), and the pulse width of the subsequently input LTC signal is counted (end).

As described above, the CPU 12 detects the LTC signal input in the preceding frame synchronization pulse by the frame synchronization interrupt processing started by the detection of the falling edge of the frame synchronization pulse 22, or a predetermined value. By the DMA transfer end interrupt processing started when the number of times of transfer exceeds, the LTC signal input at a speed exceeding 1 × speed is detected.

The relationship between the interrupt processing and the LTC signal will be described below with reference to the timing chart.

FIG. 5 shows the LT synchronized with the frame at 1 × speed.
It shows the relationship between the C signal and the frame synchronization interrupt process. As shown in FIG.
Is input, and the LTC signal is input at 1 × speed in synchronization with the frame as shown in FIG.

The LTC signal detection circuit 17 detects the rising edge and the falling edge of the LTC signal shown in FIG. 7B, counts each pulse width, and holds it in the capture register 31. The pulse width count value held in the capture register 31 is subjected to DMA transfer 45 _{1 to} 45 _M to the RAM 14 by the DMAC 27 each time, and is stored in the pulse width count value array as shown in FIG. . On the other hand, in the synchronization detection circuit 16, the first TC
The detection of the falling edge of the frame synchronization pulse 22 is monitored by U21, and when this is detected, the CPU 12 is requested as the interrupt request signal 18 via the INTC 15 to perform the frame synchronization interrupt process. That is, as shown in FIG. 3D, the falling edge of the frame sync pulse 22 causes the pulse width count value of the previous frame to be different from that of FIG.
The frame interrupt processing 46 _N-1 and 46 _N as shown in FIG.

FIG. 6 shows the LTC input over 1 × speed.
It shows the relationship between signals and DMA transfer end interrupt processing. As shown in FIG.
Is input, and as shown in FIG.
It is assumed that the TC signal is input.

The LTC signal detection circuit 17 detects the rising edge and the falling edge of the LTC signal shown in FIG. 7B, counts each pulse width, and holds it in the capture register 31. The pulse width count value held in the capture register 31 is DMA-transferred 47 to the RAM 14 by the DMAC 27 each time and is stored in the pulse width count value array as shown in FIG. On the other hand, the register control unit 34 of the DMAC 27 sends a CP as an interrupt request signal 19 via the INTC 15 when the preset transfer count of 160 is exceeded.
Request U12 for DMA transfer end interrupt processing. That is, when the DMA transfer is performed 160 times as shown in FIG. 3D, the DMA transfer end interrupt processing 4 as shown in FIG.
8 is performed.

As described above, in the LTC signal reader of this embodiment, the second TCU 2 of the LTC signal detection circuit 17 is used.
6, the rising edge and the falling edge of the LTC signal are detected, the count value of the timer unit 30 during that time is held in the capture register 31, and the DMAC 2
7, the data is transferred to the RAM 14 by DMA. As a result, the CPU 12 synchronizes with the frame at 1 × speed and LT
When the C signal is input, the frame sync pulse interrupt processing is activated only once per frame due to the detection of the falling edge of the frame sync pulse 22 detected by the sync detection circuit 16. Processing delay due to processing overhead can be significantly reduced. Further, when the LTC signal is input at a speed exceeding 1 × speed, the DMA transfer end interrupt processing is started when the predetermined DMA transfer count is exceeded, so that the L interval is set at the maximum interval.
It is possible to perform the determination processing of the TC signal, and it is possible to minimize the delay associated with the processing.

[0055]

As described above, according to the first aspect of the present invention, when the time code is input in synchronization with the frame at 1 × speed, only once in one frame by the edge detection of the frame synchronization pulse signal. Since only the frame synchronization pulse interrupt process is activated, the processing delay due to the overhead of the interrupt process can be significantly reduced. Therefore, the time code input at a higher speed than in the past can be discriminated. Further, unlike the conventional case, a PLL circuit is not required, so that the circuit configuration can be simplified and the cost can be reduced.

[0056] According to the first aspect of the present invention, without flooding the storage area of a pulse width corresponding to the time code input exceeds the normal speed <br/>, LT at maximum intervals
C signal discrimination processing can be performed, and the delay associated with the processing can be minimized.

Further, according to the second aspect of the invention, the pulse width corresponding to the bit value of the time code can be accumulated with a very simple structure, which contributes to speeding up of the time code discrimination processing. You can

Furthermore, according to the invention of claim 3 ,
In the counting means to measure the pulse width of the time code, the count value is initialized each time both edges are detected, so the pulse width corresponding to the bit value of the time code can be continuous with a very simple configuration. Then, it becomes possible to measure.

Further, according to the invention described in claim 4 , since the pulse width is sequentially stored by using the direct memory access controller, the hardware scale can be reduced and the cost can be reduced.

[Brief description of drawings]

FIG. 1 is a block diagram showing an outline of a configuration of an LTC signal reading device in this embodiment.

FIG. 2 is an explanatory diagram showing an outline of a configuration of a pulse width count value array.

FIG. 3 is a flowchart showing an outline of processing contents of an example of an LTC signal reading control program in the present embodiment.

FIG. 4 is a timing chart showing a relationship between an input LTC signal and a pulse width count value in this embodiment.

FIG. 5 is a timing chart showing a relationship between an LTC signal synchronized with a frame at 1 × speed and a frame synchronization interrupt process in the present embodiment.

FIG. 6 is an input L exceeding 1 × speed in the present embodiment.
7 is a timing chart showing a relationship between a TC signal and a DMA transfer end interrupt process.

FIG. 7 is an explanatory diagram showing an outline of a format configuration from the 0th bit to the 39th bit of the LTC signal of the NTSC color video signal defined by SMPTE.

FIG. 8 is an explanatory diagram showing an outline of a format configuration from the 40th bit to the 79th bit of the LTC signal of the NTSC color video signal defined by SMPTE.

FIG. 9 is an explanatory diagram showing an outline of a format configuration from the 0th bit to the 39th bit of the LTC signal of the PAL system color video signal defined by EBU.

FIG. 10 is an explanatory diagram showing an outline of a format configuration from the 40th bit to the 79th bit of the LTC signal of the PAL system color video signal defined by EBU.

[Explanation of symbols]

10 LTC signal reader 11 bus 12 CPU 13 ROM 14 RAM 15 INTC 16 Sync detection circuit 17 LTC signal detection circuit 18, 19 Interrupt request signal 20 Interrupt processing request 21 First TCU 22 frame sync pulse 23, 29 Edge detector 24, 30 timer section 25, 31 Capture register 26 Second TCU 27 DMAC 28 LTC signal 32 DMA transfer request 33 request priority control unit 34 Register control unit 35 Bus interface section

Claims (4)

(57) [Claims] 1. A first edge detecting means for detecting both rising and falling edges of a time code including predetermined time information, and a pulse width between both edges detected by the first edge detecting means. Pulse width measuring means for measuring the pulse width, pulse width storing means for storing the pulse width, transfer request sending means for sending a transfer request every time the first edge detecting means detects both edges, Pulse width storage means for sequentially transferring and storing the pulse widths measured by the pulse width measuring means on the basis of the transfer request sent by the request sending means, and sent by the transfer request sending means. Transfer request
Accordingly, the number of times transferred by the pulse width storage means is
When the number of times exceeds a predetermined number, transfer end interrupt required
A transfer end interrupt request transmission means for transmitting a request, and a second for detecting an edge of a predetermined frame synchronization pulse signal
Edge detecting means and the second edge detecting means detect an edge of the frame synchronization pulse signal , or the transfer end.
Transfer interrupt request sent by the completion interrupt request sending means
And a bit value discriminating means for discriminating a bit value of each pulse width stored in the pulse width storage means when the request is received and acquiring time information including the time code. Signal reader. 2. The pulse width measuring means has a predetermined frequency.
Counting means for counting clocks;
Of the time code is detected by the edge detection means.
When the falling edge is detected, the count is
Hold to hold the count value counted by means
Means for storing the pulse width in the transfer request.
The count value held in the holding means based on the
A contract characterized by being transferred to and stored in the loose width storage means.
The time code signal reader according to claim 1 . 3. The first edge detecting means is configured to detect both edges.
The count value of the counting means each time
The time code signal reading device according to claim 2 , wherein the time code signal reading device is initialized . 4. The pulse width storage means is a direct memory access.
4. The time code signal reading device according to claim 1 , wherein the time code signal reading device comprises a process controller.