JP3486784B2 - Method for manufacturing thin film transistor - Google Patents

Description

BACKGROUND OF THE INVENTION [0001] FIELD OF THE INVENTION This invention relates to a process <br/> manufacturing a thin film transistor. 2. Description of the Related Art FIGS. 8 to 8 show an example of manufacturing a conventional thin film transistor used as a switching element of an active matrix type liquid crystal display device.
This will be described with reference to FIG. First, FIG.
As shown in (C), a gate electrode 2 made of chromium and a gate line 3 connected to the gate electrode 2 are integrally formed at predetermined locations on an upper surface of a transparent substrate 1 made of glass or the like, and the upper surface thereof is formed. A gate insulating film 4 made of silicon nitride is formed thereon, a semiconductor thin film 5 made of amorphous silicon or polysilicon or the like is formed thereon, and a layer 6 for forming a channel protection film or the like made of silicon nitride is formed thereon. Then, a positive photoresist layer 7 is formed on the upper surface. Next, as shown in FIGS. 9A to 9C,
The back surface is exposed using the gate electrode 2 and the gate line 3 as a mask. In this case, the exposure is performed so that the width of the remaining portion 7a of the photoresist layer 7 on the gate electrode 2 becomes smaller to some extent than the width of the gate electrode 2 for a reason to be described later. Therefore, the exposure is performed such that the width of the remaining portion 7 a of the photoresist layer 7 on the gate line 3 is also somewhat smaller than the width of the gate line 3. Next, as shown by a dashed line in FIG. 9A, the channel protective film forming region 8 and the inter-line insulating film (the two lines at the intersection of the gate line 3 and a drain line described later are insulated). Is exposed from the front side using a photomask (not shown) having a light-shielding film in a portion corresponding to the formation region 9 for the insulating film). [0006] Next, as shown in FIGS. 10A to 10 C, when development is performed, a predetermined portion of the upper surface of the layer 6 for forming a channel protection film or the like on the gate electrode 2 is formed with a width smaller than the width of the gate electrode 2. Also, a photoresist pattern 7b having a somewhat narrow width is formed, and a predetermined portion on the upper surface of the layer 6 for forming a channel protection film or the like on the gate line 3 (that is, an intersection between the gate line 3 and a drain line described later). A photoresist pattern 7 having a width somewhat smaller than the width of the gate line 3.
c is formed. Next, as shown in FIGS. 11A to 11C, when etching is performed using the photoresist patterns 7b and 7c as masks, unnecessary portions of the layer 6 for forming a channel protective film and the like are removed. A channel protective film 10 is formed below the pattern 7b, and an inter-line insulating film 11 is formed below the photoresist pattern 7c. Thereafter, the photoresist patterns 7b and 7c are removed. Next, when ions such as phosphorus and boron are implanted using the channel protective film 10 and the inter-line insulating film 11 as a mask, the channel protective film 10 and the inter-line insulating film 11
Ion-implanted regions are formed in the semiconductor thin film 5 in regions other than the lower region. Next, as shown in FIGS. 12A to 12C, contact layers 12 and 13 made of chromium or the like are formed on both sides of the channel protective film 10 and on the upper surface of the semiconductor thin film 5 near each of them. In addition, these contact layers 12, 1
3. An unnecessary portion of the semiconductor thin film 5 in a region other than below the channel protective film 10 and the inter-line insulating film 11 is removed. In this state, a portion of the semiconductor thin film 5 provided on the gate electrode 2 via the gate insulating film 4 under the channel protective film 10 is a channel region 5a composed of an intrinsic region, and both sides thereof are a source region composed of an ion implanted region. The region 5b and the drain region 5c are provided. Next, as shown in FIGS. 13A to 13C, a pixel electrode 14 made of ITO is formed at a predetermined position on the upper surface. Next, a source electrode 15 and a drain electrode 16 made of aluminum and a drain line 17 connected to the drain electrode 16 are formed at predetermined locations on the upper surface. In this state, the source region 5b of the semiconductor thin film 5 is connected to the pixel electrode 14 via the contact layer 12 and the source electrode 15, and the drain region 5c is
Is connected to the drain electrode 16 via the. Further, the gate line 3 and the drain line 17 are arranged to intersect. In this case, it is a portion where the gate line 3 and the drain line 17 intersect and between them,
As shown in FIG. 2C, in addition to the gate insulating film 4, an inter-line insulating film 11 made of silicon nitride or the like is provided, thereby further preventing short-circuit defects between lines (layers) and noise. . Thus, a thin film transistor is manufactured. Here, in the exposure steps shown in FIGS. 9A to 9C, the exposure is performed so that the width of the remaining portion 7a of the photoresist layer 7 on the gate electrode 2 is somewhat smaller than the width of the gate electrode 2. The reason for doing so will be described. When the layer 6 for forming a channel protective film or the like is etched using the resist patterns 7b and 7c obtained by the exposure or the like as a mask, the width of the channel protective film 10 is reduced as shown in FIG. It is somewhat smaller than the width of 2. Then, as shown in FIG. 13B, a portion where the gate electrode 2 and the source electrode 15 and the drain electrode 16 face each other without the intermediary of the channel protective film 10 occurs, so that the transistor characteristics can be improved. It is. [0008] However, in such a conventional method of manufacturing a thin film transistor, FIG.
In the exposure steps shown in FIGS. 3A to 3C, the exposure is performed such that the width of the remaining portion 7a of the photoresist layer 7 on the gate electrode 2 becomes smaller to some extent than the width of the gate electrode 2.
The width of the remaining portion 7a of the photoresist layer 7 on the gate line 3 is somewhat smaller than the width of the gate line 3, and the width of the interline insulating film 11 in a predetermined direction is somewhat smaller than the width of the gate line 3. turn into. As a result, there is a problem that the effect of preventing a short-circuit defect between lines (layers) at the intersection of the gate line 3 and the drain line 17 is reduced. SUMMARY OF THE INVENTION An object of the present invention is to provide a method of manufacturing a thin film transistor capable of improving transistor characteristics and improving the effect of preventing a short-circuit defect between lines (layers) at a portion where a gate line and a drain line intersect. It is in. Means for Solving the Problems According to the invention of claim 1
The method of manufacturing a thin film transistor is described below.
Gate electrode and gate line connected to the gate electrode
Is provided on the gate insulating film on the gate electrode.
Channel region and source regions located on both sides of the channel region
Region, a semiconductor thin film having a drain region is provided,
Connected to the drain region of the semiconductor thin film on the gate insulating film
Drain line crosses the gate line
And a channel protective film is provided on the semiconductor thin film.
At the intersection of the gate line and the drain line.
Thin film transistor with an inter-line insulating film between
In the method of manufacturing a star, the channel protective film and the
Channel protective film for forming inter-line insulating film
A formation layer is formed, and a layer is formed on the formation layer such as a channel protective film.
Forming a photoresist layer, forming the gate electrode and the gate
The gate line is used as a mask in the longitudinal direction of the gate line.
Exposure from the back side obliquely, and then a mask with a predetermined pattern
Photo-exposed by surface exposure and then developed
Etching using the resist pattern as a mask
Thus, unnecessary portions of the layer for forming the channel protective film and the like are removed.
Then, the chip having a width smaller than the width of the gate electrode is removed.
Wider than the channel protective film and the width of the gate line.
The inter-line insulating film is formed.
It is. According to the first aspect of the present invention, a channel protection film narrower than the width of the gate electrode is formed on the semiconductor thin film only by devising the back surface exposure, and the gate line and the gate line are formed. Since an inter-line insulating film that is a portion that intersects with the drain line and is wider than the width of the gate line can be formed therebetween, the number of steps can be prevented from increasing. FIGS. 1 to 6 show respective steps of manufacturing a thin film transistor according to an embodiment of the present invention. Therefore, the structure of the thin film transistor of this embodiment will be described together with its manufacturing method with reference to these drawings in order. First, as shown in FIGS. 1A to 1C,
A gate electrode 22 made of chromium and a gate electrode 22 made of chromium
The gate line 23 connected to the substrate is integrally formed with a thickness of about 1000 °, a gate insulating film 24 made of silicon nitride is formed on the upper surface with a thickness of about 4000 °, and an amorphous silicon, polysilicon or the like is formed on the upper surface. A semiconductor thin film 25 is formed to a thickness of about 500 °, a layer 26 for forming a channel protective film or the like made of silicon nitride is formed to a thickness of about 2000 ° on the upper surface, and a positive photoresist layer 27 is formed on the upper surface. Form. Next, as shown in FIGS. 2A to 2C,
The back surface is exposed using the gate electrode 22 and the gate line 23 as a mask. In this case, as shown in FIG. 2B, exposure is performed from both sides of the gate electrode 22 in the width direction, that is, from both sides of the gate line 23 in the longitudinal direction. As shown in (C), the exposure in the width direction of the gate line 23 is substantially the same as the exposure from the vertical direction. As a result, even if the exposure is performed so that the width of the remaining portion 27a of the photoresist layer 27 on the gate electrode 22 left by the development becomes smaller to some extent than the width of the gate electrode 22, the photoresist layer 27 on the gate line 23 is exposed. The exposure can be performed such that the width of the remaining portion 27a is somewhat larger than the width of the gate line 23. Here, an example of the relationship between the exposure time in such exposure and the exposed area of the photoresist layer 27 will be described with reference to FIG. In FIG. 7, the horizontal axis indicates the exposure time, and the vertical axis indicates the degree of the remaining portion 27a of the photoresist layer 27 left by the development after the exposure, with one edge of the gate electrode 22 and the gate line 23 in the width direction. The corresponding portion is defined as a reference (± 0), the outside is shown as plus (+), the inside is shown as minus (-), and the illuminance of the lamp used for exposure is 20 mW / cm ^2.
It is. When the exposure is performed obliquely on both sides in the width direction of the gate electrode 22, in the area shown in FIG. 2C, as shown by the curve C in FIG. Photoresist layer 27
Of the gate line 23 proceeds inward from one edge in the width direction of the gate line 23. On the other hand, FIG.
In the region shown in FIG. 7B, since the exposure is performed obliquely on both sides in the width direction of the gate electrode 22, as shown by the curve B in FIG. When the width of the photoresist becomes narrower and the exposure time elapses for 30 seconds, the non-remaining portion 27b of the photoresist layer 27 on the gate electrode 22
From the one edge in the width direction.
The remaining portion 27 a of the photoresist layer 27 on both ends of the channel protection film 30, that is, on the gate electrode 22 corresponding to the channel protection film 30, as transistor characteristics.
Should be located at least 0.5 μm inward from one edge of the gate electrode 22 in the width direction.
If the exposure time is about 40 to 45 seconds, the gate electrode 22
The width of the remaining portion 27a of the photoresist layer 27 on the upper side can be made somewhat smaller than the width of the gate electrode 22, and the width of the remaining portion 27a of the photoresist layer 27 on the gate line 23 can be reduced.
Can be made somewhat larger than the width of. After the above-described backside exposure is completed, a light-shielding film is formed on a portion corresponding to the channel protective film forming region 28 and the inter-line insulating film forming region 29, as shown by a dashed line in FIG. Exposure is performed from the front side using a photomask (not shown). Next, FIG.
As shown in FIG. 3C, when the development is performed, the gate electrode 2 can be formed even if the accuracy of alignment of a photomask (not shown) is not high.
A photoresist pattern 27c having a width somewhat smaller than the width of the gate electrode 22 is formed at a predetermined position on the upper surface of the layer 26 for forming a channel protective film and the like on the gate line 23. At a predetermined location on the upper surface of the layer 26 (that is, at the intersection of the gate line 23 and a drain line described later), a photoresist pattern 27d that is somewhat wider than the width of the gate line 23 is formed. Next, as shown in FIGS. 4A to 4C,
When etching is performed using the photoresist patterns 27c and 27d as masks, unnecessary portions of the layer 26 for forming a channel protection film or the like are removed, so that the channel protection film 30 is formed under the photoresist pattern 27c. An inter-line insulating film 31 is formed below. Thereafter, the photoresist pattern 27c,
27d is removed. Next, when ions such as phosphorus and boron are implanted using the channel protective film 30 and the inter-line insulating film 31 as a mask, an ion-implanted region is formed in the semiconductor thin film 25 in a region other than under the channel protective film 30 and the inter-line insulating film 31. Is done. Next, as shown in FIGS. 5A to 5C,
The contact layer 3 made of chromium or the like is formed on the upper surface of the semiconductor thin film 25 on both sides of the channel protection film 30 and in the vicinity thereof.
2 and 33 are formed, and these contact layers 32 and 3 are formed.
3. Unnecessary portions of the semiconductor thin film 25 in regions other than below the channel protective film 30 and the inter-line insulating film 31 are removed. In this state, the gate insulating film 2 is formed on the gate electrode 22.
The portion under the channel protective film 30 of the semiconductor thin film 25 provided with the interposition 4 is a channel region 25a made of an intrinsic region, and both sides thereof are source regions 2 made of an ion implanted region.
5b and a drain region 25c. Next, as shown in FIGS. 6A to 6C,
A pixel electrode 34 made of ITO is formed at a predetermined location on the upper surface. Next, a source electrode 35 and a drain electrode 36 made of aluminum and a drain line 37 connected to the drain electrode 36 are formed at predetermined locations on the upper surface.
In this state, the source region 25b of the semiconductor thin film 25 is connected to the pixel electrode 34 via the contact layer 32 and the source electrode 35, and the drain region 25c is
3 is connected to the drain electrode 36. Also,
The drain line 37 and the gate line 23 are arranged crossing each other. Further, an interline insulating film 31 made of silicon nitride and the like are provided in addition to the gate insulating film 24 at a portion where the drain line 37 and the gate line 23 intersect. Thus, the thin film transistor of this embodiment is manufactured. In the thin film transistor thus obtained, as shown in FIG. 2B, the width of the remaining portion 27a of the photoresist layer 27 on the gate electrode 22 is set to be somewhat smaller than the width of the gate electrode 22. , The width of the channel protective film 30 is
Can be made somewhat smaller than the width of. As a result, a portion where the gate electrode 22 faces the source electrode 35 and the drain electrode 36 without interposing the channel protective film 30 is generated, so that the transistor characteristics can be improved. Further, as shown in FIG. 2C, the remaining portion 27 of the photoresist layer 27 on the gate line 23 is formed.
Since the exposure is performed so that the width a is somewhat larger than the width of the gate line 23, the width of the inter-line insulating film 31 may be made somewhat larger than the width of the gate line 23 (and the width of the drain line 37). it can. As a result, the effect of preventing short-circuit defects between lines (layers) and the effect of preventing noise at the intersection of the gate line 23 and the drain line 37 can be enhanced. further,
The channel protection film 3 having a width smaller than the width of the gate electrode 22 is formed on the channel region 25a only by devising the back surface exposure.
0, and the inter-line insulating film 31 which is a portion where the gate line 23 and the drain line 37 intersect and which is wider than the gate line 23 can be formed therebetween. It can be prevented from increasing. As described above, according to the first aspect of the present invention, a channel protection film narrower than the gate electrode is formed on the channel region only by devising the back surface exposure. Since an inter-line insulating film that is a portion where the gate line and the drain line intersect and is wider than the gate line can be formed therebetween, the number of steps can be prevented from increasing.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 (A) shows a method for forming a gate electrode, a gate line, a gate insulating film, a semiconductor thin film, a channel protective film, etc. on a transparent substrate when manufacturing a thin film transistor according to one embodiment of the present invention. FIG. 4B is a plan view showing a state in which a layer and a photoresist layer are formed, FIG. 4B is a cross-sectional view along the line BB, and FIG. 4C is a cross-sectional view along the line CC. FIG. 2A is a plan view showing a state where the back surface is exposed in the same manufacturing process, FIG. 2B is a cross-sectional view along the line BB, and FIG. 2C is a cross-sectional view along the line CC. 3A is a plan view showing a state in which a photoresist pattern is formed in the same manufacturing process, FIG. 3B is a cross-sectional view along the line BB, and FIG. 3C is a cross-sectional view along the line CC . 4A is a plan view showing a state in which a channel protective film and an inter-line insulating film are formed in the same manufacturing process, FIG. 4B is a cross-sectional view taken along the line BB, and FIG. Sectional view along the line. FIG. 5A is a plan view of the same device in a state where elements are separated, FIG. 5B is a cross-sectional view taken along the line BB, and FIG. 5C is a cross-sectional view taken along the line CC. 6A is a plan view showing a state in which a pixel electrode, a source electrode, a drain electrode, and a drain line are formed in the same manufacturing process, FIG. 6B is a cross-sectional view taken along the line BB, and FIG.
Is a cross-sectional view along the line CC. FIG. 7 is a view showing an example of a relationship between an exposure time in the backside exposure shown in FIG. 2 and a degree of a width of a photoresist left by development with respect to a width of a mask. FIG. 8A is a plan view showing a state in which a layer for forming a gate electrode, a gate insulating film, a semiconductor thin film, a channel protective film, and the like and a photoresist layer are formed on a transparent substrate in manufacturing a conventional thin film transistor; () Is a cross-sectional view along the line BB, and (C) is a cross-sectional view along the line CC. 9A is a plan view showing a state where the back surface is exposed in the same manufacturing, FIG. 9B is a cross-sectional view taken along the line BB, and FIG. 9C is a cross-sectional view taken along the line CC. 10A is a plan view showing a state in which a photoresist pattern is formed in the same manufacturing process, FIG. 10B is a cross-sectional view along the line BB, and FIG. 10C is a cross-sectional view along the line CC . 11A is a plan view showing a state where a channel protective film and an inter-line insulating film are formed in the same manufacturing process, FIG. 11B is a cross-sectional view taken along the line BB, and FIG. Sectional view along the line. FIG. 12A is a plan view showing a state where elements are separated in the same manufacturing, FIG. 12B is a cross-sectional view along the line BB, and FIG. 12C is a cross-sectional view along the line CC. 13A is a plan view showing a state in which a pixel electrode, a source electrode, a drain electrode, and a drain line are formed in the same manufacturing process, FIG. 13B is a cross-sectional view taken along the line BB, and FIG.
Is a cross-sectional view along the line CC. [Description of Signs] 22 Gate electrode 23 Gate line 24 Gate insulating film 25 Semiconductor thin film 30 Channel protective film 31 Inter-line insulating film 32 Source electrode 33 Drain electrode 37 Drain line

Claims (1)

(57) Claims 1. A gate electrode and a gate electrode under a gate insulating film.
A gate line connected to the gate electrode is provided;
A channel region on the gate insulating film on the gate electrode and
Source and drain regions located on both sides
Semiconductor thin film is provided on the gate insulating film.
Drain line connected to the drain region of the semiconductor thin film
Is provided crossing the gate line, and the semiconductor thin film is provided.
A channel protective film is provided on the film, and the
Line break between the intersection with the drain line
Method for manufacturing thin film transistor provided with edge film
To form the channel protective film and the inter-line insulating film.
A layer for forming a channel protective film or the like for forming
A photoresist layer is formed on the protective layer
Using the gate electrode and the gate line as a mask,
The back side is exposed obliquely on both sides in the longitudinal direction of the gate line,
Next, surface exposure is performed using a mask having a predetermined pattern.
Mask the photoresist pattern formed by developing with
The channel protective film is etched as
Unnecessary portions of the layer for equal formation are removed to remove the gate electrode.
The channel protective film narrower than the width, and
The inter-line insulation wider than the width of the gate line
Manufacture of a thin film transistor characterized by forming a film
Method.