JP3404928B2 - Manufacturing method of thin film integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [0001] BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a thin film integrated circuit.
It is about the law. [0002] 2. Description of the Related Art In recent years, research on thin film integrated circuits has been active.
In particular, the thin film transistor (TFT) has a liquid crystal
As demand for display devices is expected to be great,
R & D is underway. TFT has polysilicon
(Poly-Si) TFT and amorphous silicon (a
-Si) TFT, but poly-Si TFT
Is two orders of magnitude faster than a-Si TFT
This is advantageous in reducing the size of the TFT,
The drive IC, etc., located outside the display panel
Cost reduction can be achieved by integrating
Due to its strengths such as being able to do so, it is receiving particular attention. [0003] By the way, poly-Si TFTs have a low cost.
In order to manufacture with a
It is necessary to form as many elements as possible on a glass substrate
is there. By doing so, the unit cost of the substrate is reduced, and the substrate 1
Increase the number of panels per sheet to reduce material and processing costs
Can be reduced. However, the large area currently available
Large and inexpensive glass substrates pose a major problem in terms of heat resistance.
There is a title. That is, the strain point temperature of an inexpensive glass substrate is
It is about 600 ° C to 650 ° C.
If the process temperature is close to the strain point temperature of the glass substrate,
The expansion and contraction of the glass substrate increases, making it impossible to manufacture.
is there. Therefore, when the margin is 100 ° C., TF
Reduce the maximum temperature of the manufacturing process of T to about 500 ° C or less
Although it is necessary to reduce the
The maximum temperature is about 600 ° C.
Are about 100 ° C. apart. FIGS. 17 to 20 show conventional TFTs.
FIG. 3 is a diagram showing a manufacturing process. As shown in FIG.
An LPCVD method (Low Pres) is formed on the glass substrate 10.
Sure CVD) or p-CVD (Plasma-C)
Furnace deposition after a-Si is deposited by VD)
Alternatively, it is crystallized by laser annealing and becomes an operating layer.
Thus, a poly-Si film 20a is obtained. [0005] Next, as shown in FIG.
The i-film 20a is patterned in an island shape, and an island-shaped pol is formed.
The y-Si film 20 is formed, and an ECR-CVD method is formed thereon.
(Electron Cyclotron Reson
ance-CVD), p-CVD or normal pressure CVD
SiO by the method_Two Such as a gate insulating film 30 is deposited
It is. [0006] Next, as shown in FIG.
Gate electrode 50 is deposited and patterned
Thereafter, ion implantation is performed using gate electrode 50 as a mask.
(Not shown) or ion doping device (not shown)
), The source electrode portion 40a and the drain electrode portion 4
0b is doped with impurities and then activated at a temperature of 500 ° C
Annealing treatment is performed. Further, as shown in FIG._Two Etc.
An interlayer insulating film 60 is deposited, and an opening for taking out an electrode is formed.
70a and 70b were opened, and Al was deposited thereon
Thereafter, the Al wiring 80 is formed by patterning.
After that, a protective film 90 such as SiN is disposed,
A y-Si TFT is formed. By the way, the strain point temperature 6
When using a glass substrate of about 00 ° C,
Maximum temperature needs to be set at a relatively low temperature around 500 ° C
As mentioned before, here is the best
The steps related to the temperature will be described in detail. First, a process for forming a poly-Si operation layer is performed.
Usually, excimer laser annealing equipment is used.
Often. Excimer laser annealing equipment includes
a pulse of about 248 nm which is easily absorbed by a-Si
User has high energy of several MW and 25n
It is used with a short pulse width of about 100 to 100 nsec.
Processing time is extremely short, and the laser beam
Size is as small as 1cm x 1cm
Heat damage to the substrate
There is an advantage that it is less. For conventional furnace annealing,
Although a processing temperature of around 600 ° C was required,
In the case of a Shima laser annealing device, room temperature is sufficient.
Safe against strain point temperature of glass substrate. Further, as a method of depositing a gate insulating film,
In many cases, an ECR-CVD apparatus is used.
CR-CVD equipment has a high density
Good quality gate near room temperature to generate plasma
An insulating film can be deposited. However, ECR-CVD
The equipment has better gate insulation than p-CVD equipment.
Although it has the advantage of obtaining an edge film, it can process large-area substrates.
There is a disadvantage that it is difficult to perform. [0010] In addition, ion dope
Is often used. Generally, ion do
The ping device differs from the ion implanter in that
All ions generated from the ion source cannot be separated
Is introduced into the semiconductor. But this ion doping
The device is a cross section of the ion beam itself extracted from the ion source.
With a large area, large area substrates can be processed in a short time.
Temperature of the impurity activation annealing after ion implantation
It can be relatively low temperature of about 500 ℃ to 500 ℃
You. The reason for this is that when introducing impurities,
Due to the simultaneous injection of a large amount of generated hydrogen,
Due to the assist effect of so-called hydrogen beam annealing
It is believed that there is. With the advent of these devices, excellent heat resistance
With a quartz substrate
Therefore, glass substrates that are inexpensive and easy to enlarge
Panels are being prepared. By the way, use these devices
Even if TFT with sufficient performance is manufactured on a glass substrate
There are still difficult tasks to do. Of that challenge
As one, the maximum temperature of the process is as low as about 500 ° C
Therefore, a gate insulating film with sufficiently good characteristics is still not obtained.
That is not done. Especially about 1000 ° C
Formed by low temperature treatment compared to thermal oxide film formed at high temperature
The properties of the insulating film used are inferior, and further improvements in properties are expected.
It is rare. Further, as described above, the ECR-CVD apparatus
In comparison with p-CVD equipment and normal pressure CVD equipment
As a result, a high-quality gate insulating film can be obtained,
There is a disadvantage that the substrate is difficult to process. Therefore, good characteristics are provided on a glass substrate.
Japanese Patent Application Laid-Open No. 62-11 / 1987 discloses a method of forming a gate insulating film.
No. 9974 discloses that a gate insulating film is deposited on a semiconductor thin film.
And irradiate it with a laser beam such as an excimer laser.
By doing so, the glass substrate can be
That a gate insulating film with favorable characteristics can be formed
Is disclosed. However, in practice, this method
However, a TFT with sufficiently good characteristics on a glass substrate
You can't get it. It is a wave of excimer laser light
Since the length is ultraviolet light, SiO_Two The gate insulating film
Laser light is transmitted, and the irradiated laser light is p
The target gate absorbed only in the poly-Si operation layer
This is probably because the insulating film is hardly annealed. Furthermore,
The heat given to the working layer by the laser beam
Not the direction of the gate insulating film, but the lower glass substrate
Heat is dissipated in the direction. Therefore, in this annealing method, pol
Interface between y-Si working layer and gate insulating film and gate insulation
Defects in the film cannot be sufficiently removed,
It is considered that a TFT having characteristics cannot be obtained. Next, the process temperature performed by the present inventors was described.
Results of preliminary experiments on the effect of TFT on TFT characteristics
explain about. First, excimer laser on quartz substrate
Forming a poly-Si working layer using an annealing device;
Furthermore, a gate insulating film is deposited at room temperature by ECR-CVD
After depositing a Ta gate electrode, the gate electrode is
Impurity source by ion doping equipment
Part, drain part, and temperature 500 ℃ by electric furnace
Activation annealing of impurities was performed to produce a sample.
When the characteristics of this sample were examined,
The sheet resistance of the contact area was sufficiently low and good, but other characteristics
Performance is not good, for example, the threshold of n-channel TFT
Voltage V_THWas as high as 10V. So, this sample
After additional annealing at a temperature of 600 ° C., the threshold voltage V_TH
Decreased from 1 to 2 V, and very good characteristics were obtained. This
After the gate electrode is formed,
Removal of process damage by annealing
It is considered that good characteristics were obtained. This
Process damage is caused by the gate electrode deposit
Stacking, gate electrode processing, or ion doping equipment
Occurs at any stage during the introduction of impurities
It is thought to be, but details are currently unknown. This
TFT with good characteristics using a glass substrate like
After the impurity introduction, annealing at about 600 ° C.
Where the glass base should be applied.
Since thermal damage to the plate is inevitable, annealing can be performed easily.
I can not do it. In addition, heat damage to the glass substrate
As a method of annealing without providing,
No. 72 discloses that a thin film semiconductor and a transparent insulating substrate are interposed.
Incoherent wavelengths transmitted through the transparent insulating substrate
Disclosed is a method of providing a layer that absorbs light. This
Raise the transparent insulating substrate to a high temperature
Process only the semiconductor thin film at high temperature
Low cost Pyrex as an insulating substrate
Inexpensive glass such as glass and soda glass can be used
Semiconductor devices that are inexpensive and have good electrical characteristics
It is stated that it can be obtained. But in fact halogen
In the case of incoherent light such as a lamp, a few seconds to several tens
Insulation substrate requires relatively long irradiation time
Absorbing layer does not absorb light directly
High-temperature heat is transmitted to the underlying insulating substrate,
Often receives damage. Also disclosed in the above publication
In the case of the method described above, the absorption layer provided under the semiconductor thin film
As a result, the flatness of the device is impaired, and the production yield is low.
There is also a disadvantage that it is easy to drop. [0014] SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned circumstances.
In view of the above, using a glass substrate, a thin film
Thin-film integrated circuits that can produce integrated circuits at low cost
It is an object of the present invention to provide a method for producing the same. [0015] [MEANS FOR SOLVING THE PROBLEMS]
The manufacturing method of the thin film integrated circuit of Ming
Manufacturing of thin film integrated circuits, forming thin film integrated circuits on insulating films
In the fabrication method, a predetermined pulse is
Form a light-absorbing film that absorbs laser light,
By irradiating the absorption film with a predetermined pulsed laser beam,
The method includes a step of heat-treating the region to be processed. [0016] The method of manufacturing a thin film integrated circuit according to the present invention is as described above.
The operation layer, gate insulating film and
A predetermined pulse rate is set on a predetermined area to be processed, such as an interface between them.
After forming a light-absorbing film that has light-absorbing properties for laser light,
Irradiating this light absorbing film with a predetermined pulsed laser beam
Therefore, the region to be processed is instantaneously subjected to high-temperature annealing.
As a result, a gate insulating film having good characteristics can be obtained. That
As a result, to manufacture inexpensive and high-performance thin film integrated circuits
Can be. [0017] Embodiments of the present invention will be described below.
Each of the following embodiments is a so-called coplanar p-type.
The present invention is applied to a method for manufacturing an poly-Si TFT.
This is an example of the case. 1 to 5 show a first embodiment of the present invention.
It is a figure showing the manufacturing process of TFT in an example. First, as shown in FIG.
On top of this, a thickness of 100
After depositing a-Si of nm, the wavelength is 248 nm and the pulse is
25nsec width, 450mJ / cm energy intensity^Two of
A-Si is connected by KrF excimer laser
The poly-Si film 20a to be crystallized to be an operation layer was obtained.
In this crystallization process, a-Si instantaneously
It is heated to over 00 ° C and melts, but its melting time is about
Because the glass substrate is extremely short, about 100 nsec,
No damage is taken. In addition, high energy
Because of the crystallization treatment, a poly-Si film with good crystallinity is obtained.
can get. Next, as shown in FIG.
After patterning the film 20a into an island shape, the ECR-CV
100 nm thick SiO at room temperature by Method D_Two Consisting of
A gate insulating film 30 was deposited. Next, as shown in FIG.
In order to form a light absorbing film on the gate insulating film 30,
LPCVD method at a temperature of 450 ° C. and a thickness of 30 nm
After depositing the a-Si light absorbing film 200, an excimer laser
-450 mJ / cm depending on the device^Two With the energy of
Laser annealing was performed. Next, as shown in FIG.
Damage the semiconductor when removing the film 200
CDE (Chemical Dry Etch)
ing) Dry etching by equipment
After removing the completed light absorbing film a-Si200, sputtering
A gate electrode with a thickness of 500 nm at a temperature of 150 ° C depending on the device
Ta50 was deposited. Next, on the gate electrode 50
In addition, resist pattern by photolithography method
And dry-etch using the resist as a mask.
went. Next, the resist was stripped to form a pattern
Thereafter, ion doping is performed using the gate electrode 50 as a mask.
Between the source electrode portion 40a and the drain electrode portion 40b.
Impurities were introduced. The implantation conditions are the source electrode section and the drain.
N for the in-electrode⁺ When using a mold, the acceleration voltage is 100 ke
V, gas used is 5% PH_Three Containing hydrogen gas, injection amount is
1 × 10¹⁶cm^-2And the source and drain electrodes
Pole part⁺ When using a mold, use the accelerating voltage of 40 keV
The gas is 5% B_Two H₆ Hydrogen gas containing 1 × 1
0¹⁶cm^-2It is. After introducing impurities, in a nitrogen atmosphere
At 500 ° C. for 1 hour for impurity activation annealing
Was. The activation annealing temperature is as low as this
Therefore, the glass substrate was not thermally deformed. Next, as shown in FIG.
1 m thick SiO 2 at a temperature of 250 ° C._Two Consisting of
An interlayer insulating film 60 is deposited and wet-etched with hydrofluoric acid.
Openings 70a and 70b for taking out electrodes
1 μm thick at a temperature of 150 ° C. by a sputter device
After depositing Al, patterning is performed to form Al wiring 8
0 at a temperature of 250 ° C. by a p-CVD apparatus.
A protective insulating film 90 made of 1.5 μm SiN is deposited.
Was. The poly-Si thus produced is
  TFTs have better characteristics than the conventional example.
In addition, the threshold voltage was greatly improved. Furthermore, the gate insulating film
Was evaluated by the CV method.
The defect density at the interface between the active layer and the gate insulating film is significantly lower.
I knew it was down. Furthermore, the breakdown voltage of the gate insulating film
Was also improved compared to the conventional example. In addition, the short pulse
Because of the use of Maresa, it is heated to over 1000 ℃
The lower glass substrate was not thermally damaged.
Note that a large area can be used as a gate insulating film deposition method.
In the case where a simple p-CVD method is adopted,
The characteristics of the film were improved. The reason why the characteristics have been improved in this way is as follows.
Thus, the following can be explained. In the above embodiment
Heat-treated with short-wavelength pulsed laser light,
In the case of an excimer laser having a wavelength of 248 nm,
Laser between the depth of about 5nm from the surface of a-Si layer
Light is absorbed and almost all laser light is absorbed by the light absorbing film
It is thought that it is. As a result, the light absorbing film is 100
The temperature rises to 0 ° C or more, and the amount of heat rises below the gate insulation
Gradually transferred to the film, working layer and even the glass substrate
It is. Therefore, the interface between the operating layer and the gate insulating film and the gate
It is thought that the defects in the insulating film itself were greatly reduced.
You. In contrast, conventionally, the amount of absorbed heat itself is small.
In addition, the amount of heat is sufficiently supplied to the gate insulating film side
Without dissipating heat to the glass substrate
It is thought that there is. Next, a second embodiment of the present invention will be described.
I do. FIGS. 6 to 9 show a second embodiment of the present invention.
It is a figure showing the manufacturing process of TFT. First, as shown in FIG.
As shown in FIG.
A-Si having a thickness of 100 nm was deposited at a temperature of 50 ° C.
After that, wavelength 248 nm, pulse width 25 nsec, energy
-Strength 450mJ / cm^Two KrF excimer laser equipment
Depending on the position, the pol which crystallizes a-Si and becomes an operation layer
A y-Si film 20a was formed. Next, as shown in FIG.
After patterning the film 20a into an island shape, the ECR-CV
100 nm thick SiO at room temperature by Method D_Two Consists of
A gate insulating film 30 was deposited. Next, as shown in FIG.
In order to form a light absorbing film on the gate insulating film 30,
LPCVD method at a temperature of 450 ° C. and a thickness of 30 nm
After depositing the a-Si light absorbing film 200, the p-CVD method
50 nm thick SiO at room temperature_Two Insulating film 2 made of
00a was deposited and 400 excimer laser equipment was used.
mJ / cm^Two Laser annealing treatment with the energy of
went. Next, as shown in FIG._Two Insulating film
200a is removed with hydrofluoric acid, and the a-Si light absorbing film 20 is removed.
Dry etch by CDE equipment to remove 0
I did it. Next, at a temperature of 150 ° C.
A Ta50 for a gate electrode having a thickness of 500 nm was deposited. This
Subsequent steps are the same as in the first embodiment. this
The poly-Si TFT manufactured as described above has a first
As in the example, it had good characteristics. The second embodiment is different from the first embodiment.
8 is that the insulating film 20 is formed on the light absorbing film 200 in FIG.
0a is formed. With such a structure
As a result, the a-Si film 200 used as the light absorbing film
When excimer laser annealing
Is reduced, and the energy of the laser light is
You. Therefore, the energy density of the irradiated laser light is reduced.
And the beam size can be increased accordingly.
Can reduce the processing time
You. Also, since the heat capacity of the light absorbing film increases, the cooling rate
Decreases the annealing time, effectively extending the annealing time
Fruit is enhanced. Next, a third embodiment of the present invention will be described.
I do. 10 to 14 show a third embodiment of the present invention.
FIG. 4 is a diagram showing a manufacturing process of a TFT according to the present invention. First, FIG.
0, on the glass substrate 10 by the LPCVD method.
A-Si with a thickness of 100 nm is deposited at a temperature of 450 ° C.
After that, wavelength 248 nm, pulse width 25 nsec, energy
Gee strength 450mJ / cm^Two KrF excimer laser
The apparatus is used to crystallize a-Si to form a po
The ly-Si film 20a was formed. In this crystallization process
A-Si is instantaneously heated to 1000 ° C. or more.
It melts and the melting time is about 100 nsec.
Is extremely short, so that the glass substrate
And not. In addition, crystallization treatment with high energy
Therefore, a poly-Si film having good crystallinity can be obtained. Next, as shown in FIG.
After patterning the i film 20a into an island shape, the ECR-C
100 nm thick SiO at room temperature by VD method_Two Consisting of
A gate insulating film 30 was deposited. Next, as shown in FIG.
And a thickness of 500 nm at a temperature of 150 ° C. by a sputtering apparatus.
Ta50 for the gate electrode was deposited. Next, the gate
Resist on the pole 50 by photolithography
Pattern and dry etching using the resist as a mask.
Was performed. Strip resist and form pattern
Then, ion doping is performed using the gate electrode 50 as a mask.
The source electrode portion 40a and the drain electrode portion 40
An impurity was introduced into b. The implantation conditions are as follows:
N for the drain electrode⁺ When the mold is used, the accelerating voltage is 100
KeV, gas used is 5% PH_ThreeIncluding hydrogen gas, injection
The quantity is 1 × 10¹⁶cm^-2And the source electrode and the drain
Electrode part⁺ In the case of a mold, the acceleration voltage is 40 keV,
Gas used is 5% B_Two H₆Containing hydrogen gas, the injection amount is 1
× 10¹⁶cm^-2It is. After introducing impurities, in a nitrogen atmosphere
Activation annealing of impurities at 500 ° C for 1 hour in air
Was done. When the activation annealing temperature is as low as this
Then, the glass substrate is not deformed by heat. Next, as shown in FIG.
In order to form a light absorbing film on
A-Si 200 having a thickness of 30 nm at a temperature of 450 ° C.
Stacked. Next, 450 excimer laser devices were used.
mJ / cm^Two Laser annealing treatment with the energy of
went. Next, when removing the a-Si light absorbing film 200,
CDE (Che) that does not damage semiconductors
Drying with a mechanical DryEtching device
Light absorption film a-Si whose role has been terminated by etching
200 were removed. Next, as shown in FIG.
1 μm thick SiO 2 at a temperature of 250 ° C._Two Consisting of
An interlayer insulating film 60 is deposited and wet-etched with hydrofluoric acid.
Openings 70a and 70b for taking out electrodes
1 μm thick at a temperature of 150 ° C. by a sputter device
After depositing Al, patterning and Al wiring
80 at a temperature of 250 ° C. by a p-CVD apparatus.
A 1.5 μm thick insulating protective film 90 made of SiN.
Stacked. The poly-Si thus prepared
  The sheet resistance of the source electrode of the TFT is 590Ω / □
And the sheet resistance of the drain electrode portion is 940
Ω / □, both of which were good values. The mobility is
60cm for n channel^Two / Vs, 40 cm with p-channel
^Two / Vs, which is a good value. Also, the threshold voltage is n channels.
1 V for the P-channel and -3 V for the p-channel, using a quartz substrate
And the same goodness as in the case of performing the activation annealing at 600 ° C.
Value. Also use a short pulse excimer laser
The glass substrate of the lower layer
The board was not thermally damaged. The reason why such a good result was obtained is as follows.
Therefore, it can be explained as follows. That is, on
In this embodiment, the heat treatment is performed by using a short-wavelength pulsed laser beam.
The excimer having a wavelength of 248 nm in this embodiment was used.
In the case of a laser, it extends over about 5 nm from the surface of the a-Si layer.
The laser light is absorbed by the
Glass substrate is directly annealed with the irradiated energy beam
It was never done. Also, almost all laser light
The temperature of the absorbed absorber rises to 1000 ° C. or higher,
Is transmitted to the underlying gate electrode and gate insulating film
However, since the processing time is extremely short, the glass substrate surface
This is probably because the temperature was kept low. Also, a high-power excimer laser and this excimer laser
Combined use with a-Si which absorbs excimer laser light well
Therefore, heat of 1000 ° C. or more is applied to the poly-Si operation layer,
Can be supplied to gate insulating films and their interfaces
As a result, the remaining strain was removed.
Required energy for operating layer and gate insulating film
And the glass substrate surface temperature is distorted.
It is considered that the temperature was kept below the point temperature. Next, a fourth embodiment of the present invention will be described.
I do. FIG. 15 shows a TFT according to the fourth embodiment of the present invention.
FIG. 3 is a diagram showing a manufacturing process. The fourth embodiment is described above.
Is similar to the third embodiment, and is different from the third embodiment.
Is between the gate electrode and the light absorbing film made of a-Si.
The only difference is that the insulating film is provided. Therefore, the third
The steps in FIGS. 10, 11 and 12 in the embodiment are the same as those in the embodiment.
Are completely the same in FIG.
15 will be described below. As shown in FIG. 15, a gate made of Ta
After the formation of the electrode 50, the temperature is set to 250 by the p-CVD method.
SiO with thickness of 30 nm at ℃_Two Deposit an insulating film 200a
Was. An LPCV as a light absorbing film is formed on the insulating film 200a.
A-Si 20 having a thickness of 50 nm at a temperature of 450 ° C. according to Method D
After depositing 0, the energy is
Gee 450mJ / cm^Two Laser annealing
Was. The a-Si film 200 used as the light absorbing film is
The process after removal by dry etching is the third embodiment.
Is the same as The poly-S thus prepared
The mobility of iTFT is n-channel and p-channel
60cm^Two / Vs, 40cm^Two / Vs and the third fruit
It was good as in the example. The threshold voltage is also n-channel,
1V and -3V for the p channel at 600 ° C
Was as good as when the activation annealing was used. Ma
There was no thermal damage to the substrate. This embodiment is different from the third embodiment in that
Between the gate electrode 50 and the light absorbing film 200 made of a-Si.
Only in that the insulating film 200a is disposed,
As a result, aS by dry etching
Making the step of removing the i-light absorbing film 200 more reliable
be able to. This is because the removal of the gate electrode
Depending on how the material and the light absorbing film material are combined, selectivity,
In other words, materials to be removed and materials not to be removed are selected
Is not sufficiently etched, and the lower layer
Because there is a risk that the gate electrode will be etched
It is. The combination of materials that can secure this selectivity is limited.
Therefore, the configuration as in this embodiment is actually
Above, it is extremely effective. In addition, the insulating film placed in the middle
Is SiO _Two Alternatively, SiN or the like is desirable. This is made of semiconductor
High-quality materials commonly used in
Besides that, in particular, SiO_Two Is the same material as the interlayer insulating film
Therefore, a process of opening an opening for taking out the electrode at a later stage
Has the advantage of not interfering with Also this insulation
The thickness of the film is set to 10 so that the gate electrode can be sufficiently covered.
A thickness of at least nm is desirable. If the film thickness is too thick,
Desirable because etching in the step of opening steps becomes difficult
Not good. In addition, this intermediate insulating film removes the light absorbing film.
At the same time, it may be removed at the same time. Next, a fifth embodiment of the present invention will be described.
I do. FIG. 16 shows a TFT according to the fifth embodiment of the present invention.
FIG. 3 is a diagram showing a manufacturing process. The fifth embodiment is described above.
The third embodiment is similar to the third and fourth embodiments of the present invention.
The difference is that the gate electrode and the light absorbing film composed of a-Si
An insulation film is placed between the light absorption film and the light absorption film.
The point is that the film is arranged. Further, the fourth embodiment and
Means that an insulating film is further disposed on the light absorbing film made of a-Si
The only difference is that it is. Therefore, the third implementation
The steps of FIGS. 10, 11, and 12 in the example are the same as those in the present embodiment.
16 is completely the same,
explain. As shown in FIG. 16, a gate made of Ta
After the formation of the electrode 50, the temperature is set to 250 by the p-CVD method.
SiO with thickness of 30 nm at ℃_Two Deposit an insulating film 200a
Was. An LPCV as a light absorbing film is formed on the insulating film 200a.
A-Si 200 having a thickness of 50 nm at 450 ° C. by Method D
Was deposited. Further, at a temperature of 250 ° C. by a p-CVD method,
25 nm thick SiO_Two After depositing 200b,
Energy of 450 mJ / cm using a laser^Two
Laser annealing treatment was performed. On the light absorbing film 200
SiO_Two Remove 200b with hydrofluoric acid and absorb a-Si light
The process after removing the film 200 by dry etching is
This is the same as the third embodiment. Made in this way
The mobility of the poly-Si TFT is n-channel and p-channel.
60cm each in the channel^Two / Vs, 40cm^Two / V
s, which was good as in the third example. Also, the threshold
The value voltage is also 1 V,-
3 V, the same as in the case of the activation annealing at 600 ° C.
It was good. No thermal damage to substrate
Was. This embodiment is different from the third embodiment in that a gate electrode
An insulating film is disposed between the light absorbing film and the a-Si light absorbing film;
This is because an insulating film is also provided on the light absorbing film.
As a result, the a-S
When excimer laser annealing the i-film,
Can reduce reflection and use energy effectively
This has the advantage that Also, the heat capacity of the light absorption film increases
Therefore, the cooling rate decreases, and the annealing time is effectively reduced.
There is also the effect of extending. The thickness of this insulating film is set appropriately.
Otherwise, the laser light will reflect off the insulating film surface,
The thickness of the underlying a-Si film and the wavelength of the laser light
Based on the length, it is possible to select the film thickness with the lowest reflectance.
desirable. It should be noted that, as in the third embodiment, on the gate electrode
When a light absorbing film is directly placed on the light absorbing film,
An effective method is to place an anti-irradiation film and perform laser annealing.
is there. In each of the above embodiments, the co-play
Only about the manufacturing method of the na-type poly-Si TFT
As described above, the present invention relates to a coplanar type poly-Si
  Not limited to TFT, staggered type or
Applies to other thin film integrated circuits such as inverted stagger type
Can be. In each of the above embodiments, p is used as the operation layer.
The case where the poly-Si is used has been described.
In the above, the operation layer is limited to only poly-Si.
Instead of other semiconductor thin films such as Ge and SiGe,
No. In each of the above embodiments, the gate insulating film
As SiO_Two Has been described in the case of using
In the description, the gate insulating film operation layer is made of SiO._Two Limited to only
Other gate insulating films such as SiN.
No. Further, in each of the above embodiments, a-Si
In the present invention, an example using light absorption is described.
The film collection is not limited to a-Si only,
Low in purity, easy to deposit on large area devices, and later
At present, a-Si is the most preferable because it is easy to remove.
New The light absorbing film should be as thin as possible.
No. This is because the heat absorbed by the light absorbing film is not transmitted
To the underlying gate insulating film and the active layer
For this reason, a thinner film is more advantageous. Also, light absorption
Do not place the collecting film on top of the gate electrode.
It may be arranged at another position such as below the layer. Also after heat treatment
However, it is not always necessary to remove the light absorbing film. However, light
If the absorbing film remains, the flatness of the device will be impaired.
Generally, it is preferable to leave the light absorbing film
Not good. The laser light on the surface of the insulating film
If the reflection is large, the effect is diminished.
Taking into account the wavelength of the laser beam and the
Thus, it is desirable to determine the thickness of the insulating film. Ma
In each of the above embodiments, impurities were introduced,
After performing the activation annealing treatment (500 ° C.) of the pure substance,
Forming a light absorbing film and performing laser annealing
However, the activation annealing treatment was omitted,
Only laser annealing is performed on the film to be collected.
Consider a method that also serves as an activation annealing process
Can be However, the activation annealing process is performed for the following reasons.
It is considered that the method of omitting the process is not preferable.
You. That is, generally, the pol
The y-Si working layer is formed
It is fuzzy and has a lower density than the initial state
I have. Therefore, the impurity activation annealing step was omitted.
If impurities were introduced during laser annealing
A large amount in a short time on the source and drain electrodes
Heat is supplied, causing rapid shrinkage,
Flatness is easily damaged, and the yield of wiring etc. decreases.
It is easy to do. The energy used and the working layer
There may be no problem depending on the combination of film thickness etc.
Therefore, in such a case, the activation annealing treatment is omitted.
No problem. In each of the above embodiments, a high-output exhaust
MALASER and a-Si that absorbs this laser light well
By using together, the heat of 1000 ° C or more is po
The ly-Si operating layer, the gate insulating film and the interface between them are provided.
In general, the excimer laser
The higher the energy, the better the results. Only
If the energy is too high, the light absorbing film
Of the light absorbing film, evaporation of the light absorbing film,
Insulation film may be thermally deformed.
It is necessary to limit energy to a level that does not cause
You. In each of the embodiments described above, the light source is
Although the case using a Kisima laser device was described,
The present invention uses an excimer laser device as a light source.
The pulsed laser is not limited to
It may be used as a source. Laser light is coherent light
Coherent light is a conventional non-coherent light
Light is absorbed by the light-absorbing film more than
Therefore, it is necessary to consider the transmission wavelength of the underlying substrate.
No need. In the case of non-coherent light, multiple wavelengths
Included, light of some wavelengths may reach the glass substrate
However, since coherent light has a single wavelength,
Absorbed completely by the film, keeping substrate temperature low
There are advantages. In addition, in non-coherent light,
Very short time of several tens nsec like Shima laser
Irradiation cannot be performed, and the heat absorbed by the light absorbing film
The glass substrate is easily damaged. Therefore, in the present invention,
In some cases, the irradiating light is coherent light and
Very short pulse lasers preferred
No. The gate electrode is thin and has a heat conductivity and heat conductivity.
Low material is desirable. This is the heat absorbed by the light absorbing film.
To effectively transfer the data to the underlying gate insulating film and operating layer
That's why. By the way, as in the above embodiments, the gate
Emit the gate electrode directly without placing a light absorbing film on the electrode.
The question of whether or not to perform Kisima laser annealing
However, doing so creates the following problems:
You. In other words, the excimer laser
Ablation of the gate electrode
And the metal gate electrode itself such as Ta, Cr or Mo
May be damaged. So, suppress ablation
If you try to supply enough energy,
No improvement can be expected. Note that poly-Si is used as a gate electrode.
Ablation is unlikely to occur,
It is not preferable because the sheet resistance increases. Also, game
If there is no light absorbing film on the electrode, heat can be
I can't. In each of the above embodiments, the light-absorbing film covers the entire gate electrode.
It is not possible to do this because it is arranged to cover the surface
No. [0048] As described above, according to the present invention,
Light-absorbing film having light-absorbing property for specified pulse laser light
Of the substrate without causing thermal damage to the substrate
Because it can be instantaneously subjected to high-temperature annealing,
High performance thin film integration using glass substrate with low strain point temperature
Roads can be manufactured. Further, according to the present invention, an inexpensive glass substrate can be used.
Can be used, and the characteristics of the gate insulating film
Large area of the substrate
Enables low-cost production of high-performance thin-film integrated circuits
be able to.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a diagram showing a manufacturing process of a TFT according to a first embodiment of the present invention. FIG. 2 is a diagram showing a manufacturing process of the TFT according to the first embodiment of the present invention. FIG. 3 is a diagram showing a manufacturing process of the TFT according to the first embodiment of the present invention. FIG. 4 is a diagram showing a manufacturing process of the TFT according to the first embodiment of the present invention. FIG. 5 is a diagram showing a manufacturing process of the TFT according to the first embodiment of the present invention. FIG. 6 is a diagram illustrating a manufacturing process of a TFT according to a second embodiment of the present invention. FIG. 7 is a diagram showing a manufacturing process of a TFT according to a second embodiment of the present invention. FIG. 8 is a diagram illustrating a manufacturing process of a TFT according to a second embodiment of the present invention. FIG. 9 is a diagram showing a manufacturing process of the TFT according to the second embodiment of the present invention. FIG. 10 is a diagram showing a manufacturing process of a TFT according to a third embodiment of the present invention. FIG. 11 is a diagram illustrating a manufacturing process of a TFT according to a third embodiment of the present invention. FIG. 12 is a diagram illustrating a manufacturing process of a TFT according to a third embodiment of the present invention. FIG. 13 is a diagram illustrating a manufacturing process of a TFT according to a third embodiment of the present invention. FIG. 14 is a diagram illustrating a manufacturing process of a TFT according to a third embodiment of the present invention. FIG. 15 is a diagram illustrating a manufacturing process of a TFT according to a fourth embodiment of the present invention. FIG. 16 is a diagram illustrating a manufacturing process of a TFT according to a fifth embodiment of the present invention. FIG. 17 is a diagram showing a manufacturing process of a TFT in a conventional example. FIG. 18 is a view showing a manufacturing process of a TFT in a conventional example. FIG. 19 is a diagram showing a TFT manufacturing process in a conventional example. FIG. 20 is a diagram showing a manufacturing process of a TFT in a conventional example. DESCRIPTION OF THE SYMBOLS 10 Glass substrate 20 Poly-Si operation layer 20a Poly-Si film 30 Gate insulating film 40a Source electrode part 40b Drain electrode part 50 Gate electrode 60 Interlayer insulating film 70a Source electrode part opening 70b Drain electrode part opening 80 Al wiring 90 Protective insulating film layer 200 Light absorbing film 200a Insulating film 200b Insulating film

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-64-48410 (JP, A) JP-A-61-145819 (JP, A) JP-A-6-181178 (JP, A) JP-A 63-148178 25913 (JP, A) (58) Field surveyed (Int. Cl. ⁷ , DB name) H01L 21/20 H01L 21/268 H01L 21/336 H01L 27/12 H01L 29/786

Claims (1)

(57) [Claim 1] A step of depositing amorphous silicon on an insulating substrate or an insulating film, and a step of irradiating the amorphous silicon with an ultraviolet pulse laser to form polycrystalline silicon Depositing a gate insulating film on the polycrystalline silicon, depositing an amorphous silicon light absorbing film on the gate insulating film , and irradiating the light absorbing film with an ultraviolet pulse laser beam. The gate insulation
Resistance of the gate insulating film with reducing the defect density at the interface between the film and the polycrystalline silicon and the gate insulating film
And a heat treatment step of increasing the pressure .