JP3405208B2 - Split multi-screen display device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image synthesizing display device for a television, and more particularly to a split multi-screen display device that splits and displays images by a plurality of asynchronous video signals on one television screen.

[0002]

2. Description of the Related Art A split multi-screen display device which divides a television screen into multiple displays is used as a display device such as a monitoring device because it does not occupy any installation space, can see a plurality of screens simultaneously, and is economical. The number of divisions is usually 4, 9, 16, etc. N due to the aspect ratio.
There are many divisions based on the square of. General-purpose television cameras that do not have an external synchronization function are often used in surveillance systems and the like, and since each video signal is asynchronous, it is necessary to perform synchronization processing for asynchronous signals in the split multi-screen display device. If the video inputs are asynchronous with each other, normal writing cannot be performed as it is, and a frame memory is provided in each of the four-input circuits to perform synchronization by performing reading based on common synchronization.

A block diagram of a conventional example of a conventional four-division multi-screen display device compatible with asynchronous video signal input will be described with reference to FIG. 5, 1 to 3 are video input terminals, 4 is a switching circuit, 5 is an A / D conversion circuit, 37 is a frame memory circuit, 23 to 25 are D / A conversion circuits, 26 to 28 are video output terminals, and 38. Is a synchronizing circuit, 39 is a clock generating circuit, 4
Reference numerals 0 to 42 are connection points of the frame memory, 43 is a sync generation circuit, 44 to 47 are sync signal output terminals, and 48 is an input video signal processing circuit. In the case of a color composite video signal such as NTSC or PAL system, Y (luminance signal) / C (color signal) separation is performed, and this C (color signal) is further subjected to U (BY) and V (R- Y) and two color difference signals are demodulated before digital processing such as A / D (analog-digital) conversion. The Y, U and V signals are respectively inputted from the video input terminals 1 to 3 and are connected to the switching circuit 4 to be output in the order of Y, U, Y and V on a dot clock basis in a time division manner and output on a dot clock basis. Is sampled and converted into digital data by the A / D conversion circuit 5. In this state, the Y pixel data is halved,
Since the U and V data have been thinned out to 1/4, respectively, they are suitable as they are as pixel data for a 1/2 reduced screen in the horizontal direction in a 4-split screen. However, most of the conventional devices are simplified circuits. Therefore, the data may be further thinned to 1/2, and in this case, the horizontal resolution will be deteriorated.

The output digital data of the A / D conversion circuit 5 is thinned out as described above, but is also written in the frame memory circuit 37 in the vertical direction by thinning out every one horizontal synchronizing period, that is, every line. The synchronization pulse and clock necessary for the circuit operation from the switching circuit 4 to the writing of the frame memory circuit 37 are Y of the video input terminal 1.
The VCO (Voltage Controlled Oscillator) is generated by the synchronizing circuit 38 and the clock generating circuit 39 based on the synchronizing signal separated from the signal.
It is generated by a cillator) or a PLL (Phase Locked Loop) circuit or the like and supplied to each circuit. The circuit configuration described above is 4
A channel is required, and the data read outputs of the frame memory circuits of the other three channels are respectively connected to the connection point 40.
Frame memory circuit 3 as a data bus via
7 is connected in parallel with the data read output. Clocks used for reading data from the respective frame memory circuits and subsequent circuits and signals based on the clocks such as synchronization pulses and memory addresses are generated by the synchronization generation circuit 43.

Clocks, sync pulses, etc. for reading data in the frame memory circuit 37 are supplied from a common sync generation circuit 43 through a connection point 44, and similarly to other three channel frame memory circuits. 45 to 47, and the image data of each frame memory is switched and read according to the display address of each screen of four divisions to form a four-division multi-screen image signal. The data read from each frame memory circuit 37 is clocked by the synchronization generating circuit 43 corresponding to each data of Y, U, and V and Y, U by the D / A (digital-analog) conversion circuits 23 to 25, respectively. , V signals are converted into analog signals and output via the video output terminals 26 to 28, respectively. Normal,
These outputs are output as a four-division multi-screen video signal converted into a color composite video signal such as NTSC or PAL by a known circuit means such as a subcarrier modulation circuit.

[0006]

Although the conventional device has a large number of inputs such as 4, 9 and 16, etc., the A / D conversion circuit, the synchronizing circuit and the clock generator are generated for the respective inputs as described above. Circuits, frame memory circuits, etc. were required, and the number of parts was large, and there was a limit to miniaturization and cost reduction.
Each of the plurality of video input and video output circuits has a clock generation circuit, and when different kinds of clocks are mixed, there is an adverse effect on the jitter of the output image due to the interference. The capacity of the frame memory for each input should be inversely proportional to the number of screen divisions, but the general-purpose frame memory IC is for standard television image processing, and the standard screen is, for example, 2
Due to the chip configuration, the actual circuit configuration does not always have the minimum required memory capacity and is inefficient.

Further, as described above, the horizontal resolution is often deteriorated by excessively thinning out pixel data for simplification of the circuit. However, the method of using the common single-screen frame memory has been difficult to implement in the past due to the complexity of the electric circuit and the large number of constituent parts, and the constraints such as cost and product size. In view of the present situation described above, the present invention enables division display even with a plurality of asynchronous video inputs with only one frame memory, and further simplifies the circuit by using a common clock generation circuit, thereby achieving a digital circuit. ASIC (Application Specific Integrated Circuit)
Provided is a split multi-screen display device which is reduced in size and cost by facilitating the realization.

[0008]

The present inventor has solved the problem by the following means as a result of earnest research in view of the above. (1) In a split multi-screen display device for split-displaying a plurality of images on the same screen, a switching circuit having a color video signal input terminal, an A / D conversion circuit for analog / digital converting the switching circuit output signal, and this digitization. line memory and two for has been write-free two luminance signal data write data
And two sets of line memories in the line memory for the color difference signal data, the selection circuit of the plurality of line memories outputs the dot clock divided clock and clear operation by the synchronization signal of the input video signal, a memory write drive signal Produces
A frame memory having a plurality of input video signal processing circuits including a line memory and a synchronous clock generation circuit supplied to a circuit in the preceding stage, and for displaying a plurality of images by the output signals of the plurality of input video signal processing circuits on the same screen in a divided manner. comprising a circuit, writing of the line memory f of the each of the input video signal processing circuit is performed by decimating the video signal data output from the a / D converter in units of lines, two
The luminance signal data line memory is alternately written with a clock having a frequency obtained by dividing the dot clock of the A / D conversion circuit, and two color difference signal data line memories are also written.
Alternately, the dot clock of the A / D conversion circuit is alternately written by a frequency-divided clock, and the reading from each line memory and the writing and reading of the frame memory are performed by a dot clock based on a common synchronization generation circuit. A split multi-screen display device characterized in that a clock having a frequency twice or more is used, and writing to the frame memory is performed by referring to address information based on a vertical synchronizing signal of each input video signal processing circuit.

(2) In a split multi-screen display device that splits and displays a plurality of images on the same screen, a black and white video signal input terminal and an A / D converter for analog / digital converting the video input signal
Write No write D conversion circuit, the digitized data
Two luminance signal data line memory, the selection circuit of the plurality of line memories outputs the dot clock divided clock and clear operation by the synchronization signal of the input video signal, generates a memory write drive signal line A frame memory circuit having a plurality of input video signal processing circuits including a memory and a synchronous clock generation circuit for supplying the circuit to the preceding stage, and for displaying a plurality of images by the output signals of the plurality of input video signal processing circuits on the same screen. the provided, write line memory f of the each of the input video signal processing circuit is performed by decimating the video signal data output from the a / D converter in units of lines, the line memories alternately <br / > Write with the frequency of the dot clock of the A / D conversion circuit and read from each line memory. Writing and reading of the frame memory uses a clock having a frequency twice or more of a dot clock based on a common synchronization generating circuit, and writing to the frame memory uses a vertical synchronizing signal of each input video signal processing circuit. A split multi-screen display device, characterized in that it is performed by referring to address information based on the above. (3) All clocks used in the input video signal processing circuit according to (1) or (2) are based on a clock generated by a common clock generation circuit, and the dot clocks of the respective A / D conversion circuits are respectively the clocks described above. (1) or (2), wherein the phase is divided by an integer with reference to the phase of the horizontal synchronizing signal by the input video signal corresponding to the A / D conversion circuit of Split multi-screen display device.

[0010] (4) For the 2 multiplier split multi-screen display device of their respective integer of 2 or more N, write to thinning reducing the video signal data in line units each N
The thinning is performed by writing once for each line, and the thinning and reducing writing by a clock having a frequency obtained by dividing the dot clock is a clock having a frequency obtained by dividing the dot clock by 1 / N. The divided multi-screen display device according to any one of (1) to (3). (5) before SL includes a line memory in the processing circuit of the read data from the frame memory, writing of the line memory is more than 2 times the dot clock, reading and carrying out at the dot clock equivalent frequency clock The split multi-screen display device according to any one of (1) to (4). (6) before SL frame memory, characterized in that it is a synchronous DRAM a single port (1) to (5)
13. A split multi-screen display device according to any one of 1.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention is a synchronous DRAM.
(Dynamic Random Access Memory) and the like, using only a common set of frame memories, the difference in horizontal synchronization timing due to writing of each asynchronous input video signal to the frame memory is different from each input video signal processing circuit. A line memory using a FIFO (First In First Out) memory or the like provided for each circuit is used. This line memory can be configured in an ASIC. The synchronization relationship between a plurality of asynchronous video signals is 1 line at the maximum in terms of horizontal synchronization rate (1 horizontal synchronization period)
However, in the case of a 4-division multi-screen, the video signal is thinned out line by line in order to reduce the screen size to 1/2. Therefore, it is possible to absorb the deviation of the synchronization by utilizing this period.

That is, a plurality of asynchronous video signal data can be synchronized at the horizontal synchronization rate by writing the asynchronous video signal data in the line memory and performing synchronous reading based on a common synchronization signal. A timing diagram in the case where each image of A, B, C, and D based on the 4-division multi-screen as in the example of FIG. 3 is a monochrome video signal will be described with reference to FIG. Figure 41 (1) shows A, B, C, D
1A, 2A, 3 is an example of a timing diagram at a horizontal synchronizing signal rate of asynchronous input video signal data of each image of FIG.
The numbers A ... Show the order of horizontal scanning. Each of the video signal data is thinned out for every line, that is, once every two lines, and this data is shown in the writing timing chart of the two line memories 1 and 2 in FIG. They are written alternately as shown.

In this writing, a clock common to each of the above video signals is used, and writing is performed with a clock having a frequency half that of the dot clock.
This means that the vertical size is reduced to 1/2. In addition,
In the case of a 9- or 16-division multi-screen, each of the video signal data is alternately written into the two line memories once every 3 or 4 lines, and the write clock is 1/3 of the dot clock or It is assumed that writing is performed with a clock having a frequency of 1/4.

The reading of these line memories and the writing / reading of the frame memory are performed by a timing based on a common synchronizing circuit and a clock having a frequency twice as high as the dot clock (hereinafter referred to as a double speed clock). The read data from the memory is synchronized at the horizontal synchronization rate, and is compressed to 1/4 in time at the timing as shown in FIG. Since writing and reading cannot be done at the same time in a single-port frame memory, the processing time is halved by the double-speed clock, so that writing and reading processing can be equivalently performed in real time, and vertical synchronization of each video signal during writing is possible. By generating the write memory address by referring to the information, it is possible to display each video signal screen at each predetermined position on the split screen. The data is read from the frame memory at the timing of the blank portion in FIG. 4C (3) with the double speed clock and is once written in the line memory.

The data of this line memory is read at the clock of the normal speed to become the data of the real time rate, and by the D / A conversion, as shown in FIG. 3, the portions A, B and C, D of the split multi-screen. A video signal corresponding to is obtained. In the above description, the case of a black and white video signal has been described, but in the case of a four-division multi-screen using a composite color video signal such as the NTSC or PAL system, the luminance signal Y and the color difference signals U and V are dots in the order of Y, U, Y and V. Since switching is performed in clock units for sampling and A / D conversion, Y pixel data is thinned and reduced to 1/2 in this state, and Y data is equivalent to the case of the monochrome video signal. That is, in the case of a black and white video signal, there is U and V pixel data in the portion of pixel data that is thinned out and unnecessary.
If the clock is shifted by one and the thinning processing is performed as described above, only the U and V data are selected, and the U and V data are thinned to 1/4, respectively.

Therefore, also in the case of a color video signal, the processing for the memory circuit can be similarly performed by adding two line memories to the black and white video circuit, and the line memory for Y data and the line memory for U and V data respectively can be processed. It suffices if writing is performed with a clock having a frequency half that of the dot clock, and the description is the same as for a monochrome video signal. In the device according to the present invention, the digital processing circuit from A / D conversion to D / A conversion including the control circuit for the frame memory for one screen can be integrated into an ASIC. Therefore, the frame memory for each video input is eliminated to provide only one set, and similarly, the clock generation circuit by the phase control VCO or the like provided for each video input is eliminated and a common set of simple clock generation circuits is provided. As a result, it is possible to eliminate the jitter due to the mixture of different clocks, realize the miniaturization, and provide a low-cost split multi-screen display device.

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The structure and operation of a split multi-screen display device of the present invention will be described below with reference to the drawings. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a block diagram relating to clock division, FIG. 3 is a 4-division multi-screen diagram, and FIG. 4 is a timing diagram in the case of a monochrome video signal. 1 and 2, 1 to 3 are video input terminals, 4 is a switching circuit, and 5 is an A / D.
Conversion circuits, 6 to 9 are line memories, 10 is a selection circuit, 1
1 is a synchronous clock generation circuit, 12 is a frame memory circuit, 13 to 15 are selection circuit connection points, 16 to 19 are synchronous signal output terminals, 20 and 21 are line memories, 22 is a synchronous generation circuit, and 23 to 25 are D / A conversion circuit, 26 to 28 are video output terminals, 29 is a clock generation circuit, 30 to 33 are clock output terminals, 34 is an input video signal processing circuit, 35 is a synchronous counter, and 36 is a clock generation circuit. When the video input signal is a composite color signal such as NTSC or PAL system, a luminance signal Y is obtained by Y / C separation and a chroma decoder.
And the color difference signals U (BY) and V (RY), which are respectively connected to the video input terminals 1 to 3 and the switching circuit 4
Are switched in the order of Y, U, Y, V in dot clock units by time division, sampled in dot clock units, and converted into digital data by the A / D conversion circuit 5.

In this state, the pixel data of Y in the horizontal direction of the image is thinned to 1/2, and U and V are thinned to 1/4, respectively, but U and V are color difference signals and the frequency band is The thinning rate may be small because it may be narrow, and this digital data is further thinned out every one line, that is, written into the line memories 6 to 9 such as FIFO once every two lines. In the line memories 6 and 7, only Y data of the digital data in the order of Y, U, Y, V is written alternately for each line of data by a clock having a half frequency of the dot clock. Similarly, the line memories 8 and 9 have U, V, U,
Only the data of the color difference signals for one line in the order of V are alternately written by the clock. The sync clock generation circuit 11 inputs a Y signal from the video input terminal 1 to generate a horizontal sync pulse or the like based on the separated sync signal, and a clock generation circuit 29 such as a crystal oscillator via a clock output terminal 30. The input clock is divided to generate a dot clock and the like, which are connected and used for the circuit operation from the switching circuit 4 to the writing operation of the line memories 6 to 9.

Conventionally, when the dot clock and the video input signal are asynchronous, A / D conversion of the dot clock and D / A conversion with the synchronized dot clock based on the synchronizing signal on the output side result in an output video signal of 1 Jitter for the dot clock is generated and cannot be used. In the present invention, this drawback is improved and cost is reduced by using a clock based on a common clock generator for a plurality of video input and video output sides, and the clocks between different clocks are used. It is possible to eliminate the harmful effects of interference. The clock division of the synchronous clock generation circuit 11 will be described with reference to the block diagram of FIG. 2 relating to clock division. For example, a clock input having a frequency four times as high as the dot clock is input to the synchronous counter 35 and cleared by a horizontal synchronous pulse. Meanwhile, it is divided by 4 to become a dot clock.

Therefore, the jitter of the dot clock is within one clock period of the quadruple frequency clock, which is 1/4 of that of the conventional case, and this amount of jitter is not a problem in the present apparatus, and clock generation is possible. It is generated as various clocks by the circuit 36 and becomes the output of the synchronous clock generation circuit 11. As described above, in the case of the 9- or 16-division multi-screen, the digital data is alternately written into the two line memories at a rate of once every 3 or 4 lines, and the write clock is the dot clock. It is assumed that writing is performed with a clock having a frequency of ⅓ or ¼. Line memory 6 of FIG.
The read data of 9 is selectively switched by the selection circuit 10 and written in a predetermined location within the address of four screens of the frame memory circuit 12, and the vertical write address refers to the vertical synchronization signal by the synchronization clock generation circuit 11. Is generated. In the 4-division multi-screen, four channels of the same circuit configuration from the video input terminals 1 to 3 or the video signal processing circuit before the terminals to the selection circuit 10 and the synchronous clock generation circuit 11 are required. The data outputs of the selection circuits of the other three channels are connected in parallel as data buses via the selection circuit connection points 13 to 15, respectively, and are output to predetermined addresses corresponding to the divided multi-screens of the frame memory circuit 12. It is controlled so that the image data is written.

The reading from the line memory of each channel and the writing / reading of the frame memory circuit 12 in the 4-channel constituent circuit are twice the dot clock generated by the synchronization generating circuit 22 based on the clock of the clock generating circuit 29. Is performed by using a clock having a frequency of, a sync pulse based on the clock, an address signal, and the like, and these are connected to each channel via sync signal output terminals 16 to 19. Similarly, the clock generated by the clock generation circuit 29 is connected to each channel via terminals 30 to 33. Of the digital data read from the frame memory circuit 12, Y data is written in the line memory 20 and U, V data is written in the line memory 21 at the double speed clock, and reading is performed at the normal speed clock. D / A conversion circuits 23 to 25 corresponding to Y, U, and V, respectively
Becomes an analog signal.

These Y, U, and V analog signals are output via the video output terminals 26 to 28, respectively, and are usually of the NTSC or PAL system or the like by known circuit means such as a subcarrier modulation circuit or a composite circuit. It is converted into a color composite video signal and displayed on a television monitor or the like as a four-division multi-screen. D / A from the A / D conversion circuit 5 of FIG.
Most of the digital circuit configuration except the frame memory circuit 12 up to the conversion circuits 23 to 25 can be formed into an ASIC, and the device according to the present invention can be downsized and the cost can be reduced. In the thinning reduction processing of the image signal data as described above, it is possible to correct the image quality deterioration due to thinning by forming and adding a vertical interpolation filter using a line memory or the like.

[0023]

According to the present invention, the following effects are exhibited. 1. According to the first and second aspects of the present invention, only a common set of frame memories using a synchronous DRAM or the like is used, and horizontal input / output of each asynchronous input video signal is written to the frame memory. the difference of the synchronization timing are used a means of absorbing the respective input two per circuit of the video signal processing circuit (four in the case of a color signal) FIFO memories such as a line memory using with. Further, for reading from each line memory and writing and reading to and from the frame memory, a high-speed clock having a frequency twice or more that of a dot clock based on a common synchronizing circuit is used. For writing to the frame memory, writing is performed by referring to the vertical synchronization information of each input video signal processing circuit, and a memory address is generated.
It is possible to display each video signal screen at a predetermined position on each split screen. A plurality of line memories of each input video signal processing circuit and a common set of frame memories are read and written by using a high-speed clock to simplify the circuit and facilitate digital circuit ASIC. As a result, it is possible to realize a split multi-screen display device that is small in size and low in cost. 2. According to the third aspect of the present invention, conventionally, since a plurality of asynchronous input video signals are synchronized with each other, a clock circuit is required for each of the digital circuits such as the frame memory of the input and output circuits. Because the clocks are mixed,
There was an adverse effect of jitter in the output image due to interference. In the present invention, all the clocks used in the video signal processing circuit are supplied from a common clock generation circuit, and further divided by an integer by referring to the phase of the horizontal sync signal of the input video signal, and thus the jitter, etc. No interference occurs. In addition, the clock circuit existing in each circuit is unnecessary, so that the cost can be reduced.

3. According to the fourth aspect of the present invention, in the present invention, only one common frame memory is used to perform thinning-out by writing once every N lines and thinning-out writing by a clock obtained by dividing the dot clock by 1 / N. By changing the vertical and horizontal decimation ratio by
It is possible to support N squared split screens such as 4, 9 and 16 split screens. 4. According to the invention of claim 5 of the present invention, as described above,
For the reading from the line memory and the writing to and reading from the frame memory provided for each circuit of each input video signal processing circuit, a clock having a frequency twice or more that of the dot clock based on the common synchronizing circuit is used. The data read from the frame memory at double speed is further written to the line memory on the output side at double speed. At the time of reading, the data is read at the clock of normal speed to become the data of the real-time rate, which is standardized by D / A conversion. Can be displayed on the screen as a television signal. 5. According to a sixth aspect of the present invention, a single frame memory common to a plurality of input video signals used in the present invention is
It is a single-port synchronous DRAM, which has high-speed data transfer, external clock synchronization function, etc., and can perform double-speed writing and reading technology of the present invention and all-circuit synchronization control by a single clock signal. became.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is a block diagram related to clock division.

FIG. 3 is a 4-division multi-screen view.

FIG. 4 is a timing chart in the case of a monochrome video signal.

FIG. 5 is a block diagram of a conventional example of a 4-division multi-screen display device.

[Explanation of symbols]

1-3: Video input terminal 4: Switching circuit 5: A / D conversion circuit 6-9: Line memory 10: Selection circuit 11: Synchronous clock generation circuit 12: Frame memory circuit 13-15: Selection circuit connection points 16-19 : Synchronous signal output terminals 20, 21: Line memory 22: Synchronous generation circuit 23-25: D / A
Conversion circuits 26 to 28: video output terminals 29: clock generation circuits 30 to 33: clock output terminals 34: input video signal processing circuit 35: synchronization counter 36: clock generation circuit 37: frame memory circuit 38: synchronization circuit 39: clock generation Circuits 40 to 42: Frame memory connection point 43: Synchronization generation circuit 44 to 47: Synchronization signal output terminal 48: Input video signal processing circuit

─────────────────────────────────────────────────── ─── Continuation of front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) H04N 5/262-5/265 H04N 5/45 H04N 7/18 G09G 5/00

Claims (6)

(57) [Claims] 1. A split multi-screen display device for split-displaying a plurality of images on the same screen, a switching circuit having a color video signal input terminal, and an A / D conversion circuit for analog / digital converting the switching circuit output signal. Included free two luminance signal data line memory write digitized data
When two two sets of line memories in the line memory for the color difference signal data, a selection circuit of the plurality of line memories outputs,
A plurality of input video signal processing circuits including a dot clock obtained by performing a clear operation with the sync signal of the input video signal to divide the clock and a memory write drive signal, and supplying the line memory and its preceding circuit with a synchronous clock generation circuit. And a frame memory circuit for dividing and displaying a plurality of images by the output signals of the plurality of input video signal processing circuits on the same screen, and writing to a line memory in each of the input video signal processing circuits, performed by decimating the video signal data output from the a / D converter in units of lines, two bright
Frequency signal data line memory is written alternately by a clock having a frequency obtained by dividing the dot clock of the A / D conversion circuit, and the two color difference signal data line memories are
Alternately, writing is performed by a clock having a frequency obtained by dividing the dot clock of the A / D conversion circuit, and reading from each line memory and writing and reading of the frame memory are performed twice as much as a dot clock based on a common synchronization generation circuit. A split multi-screen display device characterized in that a clock having the above frequency is used and writing to the frame memory is performed by referring to address information based on a vertical synchronizing signal of each input video signal processing circuit. 2. A split multi-screen display device for split-displaying a plurality of images on the same screen, comprising a monochrome video signal input terminal,
An A / D converter for analog / digital conversion of the video input signal, write no two write this digitized data
A line memory for luminance signal data, the selection circuit of the plurality of line memories outputs the dot clock divided clock and clear operation by the synchronization signal of the input video signal, generates a memory write drive signals, the line memory A plurality of input video signal processing circuits including a synchronous clock generation circuit to be supplied to the preceding circuit are provided, and a frame memory circuit for dividing and displaying a plurality of images by the output signals of the plurality of input video signal processing circuits on the same screen is provided. The writing to the line memory in each of the input video signal processing circuits is performed by thinning out the video signal data output from the A / D conversion circuit on a line-by-line basis, and the line memories alternately perform the A / D conversion. Writing with a clock of a frequency obtained by dividing the dot clock of the circuit, reading from each line memory, and A clock having a frequency twice or more that of a dot clock based on a common sync generation circuit is used for writing and reading in the memory, and an address based on a vertical sync signal of each input video signal processing circuit is used for writing in the frame memory. A split multi-screen display device characterized by being referred to information. 3. All the clocks used in the input video signal processing circuit according to claim 1 or 2 are based on the clock by a common clock generation circuit, and the dot clocks of the respective A / D conversion circuits are respectively the clocks. 3. The split multi-screen according to claim 1 or 2, wherein the phase of the horizontal synchronizing signal by the input video signal corresponding to the A / D conversion circuit is divided by an integer. Display device. Regarding wherein two multipliers of their respective integer of two or more N-divided multi-screen display device, thinning by writing once each write every N lines for thinning reducing the video signal data in line units Further, in the writing for thinning and reducing by the clock of the frequency obtained by dividing the dot clock, the dot clock is 1 / N, respectively.
4. The split multi-screen display device according to claim 1, wherein the divided multi-screen display device is a clock having a frequency divided into. 5. comprising a processing circuit in the line memory before Symbol data read from the frame memory, writing of the line memory is more than 2 times the dot clock, reading characterized in that in the dot clock equivalent frequency clock The split multi-screen display device according to any one of claims 1 to 4. 6. Before SL frame memory, according to claim 1, characterized in that the synchronous DRAM single-port
5. The split multi-screen display device according to any one of items 1 to 5.