JP3405955B2 - Semiconductor circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor circuit (for example, an image sensor) having a thin film transistor (TFT) and a thin film diode (TFD), and a manufacturing method thereof. The semiconductor circuit manufactured by the present invention is formed on either an insulating substrate such as glass or a semiconductor substrate such as single crystal silicon. In particular, the present invention relates to a semiconductor circuit having a TFT and a TFD which are manufactured through crystallization and activation by thermal annealing.

[0002]

2. Description of the Related Art Thin film semiconductor devices such as thin film transistors and thin film diodes are classified into amorphous devices and crystalline devices depending on the type of silicon used.
Amorphous silicon was low in manufacturing temperature and excellent in mass productivity, but it is inferior to crystalline silicon in physical properties such as field effect mobility and conductivity, so a crystalline semiconductor element is required to obtain high-speed operation characteristics. It was Recently, a circuit (for example, an integrated image sensor circuit) in which an optical sensor using a thin film diode is driven by a thin film transistor using crystalline silicon that can operate at high speed has been proposed.

[0003]

FIG. 4 shows an example of a conventional procedure for manufacturing a circuit in which a TFD and a TFT are combined. A base insulating film 42 is formed on a glass substrate 41, an amorphous silicon film is formed on the base insulating film 42, and this is crystallized by annealing for a long time at a temperature of 600 ° C. or higher and patterned to form an island-shaped silicon region 43. To get Then, the gate insulating film 44 is formed, and the gate electrodes 45N and 4N are formed.
5P is formed. (Fig. 4 (A))

Then, the N-type impurity region 46N and the P-type impurity region 46P are formed by using a known CMOS manufacturing technique. In this impurity introducing step, impurities are introduced in a self-aligned manner with respect to the gate electrode. After implanting impurities,
The impurities are activated by means such as laser annealing and thermal annealing. (Fig. 4 (B))

Next, a first interlayer insulator 47 is formed,
Contact holes are formed in this, and electrodes / wirings 48a, 48b, 48c and electrodes 48d of the amorphous silicon diode are formed on the source and drain of the TFT. (FIG. 4C) Next, P-type, I-type (intrinsic) and N-type amorphous silicon films 49P, 49I, and 49N are sequentially stacked and patterned to form a diode junction. (Fig. 4
(D) Finally, a second interlayer insulator 50 is formed, a contact hole is formed in the second interlayer insulator 50, and an electrode 51 of the amorphous silicon diode is formed to complete the circuit. (Fig. 4
(E))

In the conventional method which requires such a procedure,
Since it is necessary to form two layers each of a silicon film and an interlayer insulator, which are required to be formed for a long time, and N layers and P layers in addition to them, there is a problem that the throughput is lowered. In addition, in the plasma CVD method and the low pressure CVD method used for forming these films, the dead time of the apparatus for maintenance is large, and the existence of these extra steps further lowers the throughput.

In addition, a temperature of 600 ° C. or higher is required to crystallize the silicon film used for the crystalline silicon TFT, and a long time of 24 hours or more is required for the crystallization, so that it is actually necessary. When mass-producing, a number of crystallization equipment facilities were required, and there was the problem that a huge amount of equipment investment would rebound into costs. The present invention overcomes the above-mentioned problems by forming a silicon film used for a crystalline silicon TFT and a silicon film used for a TFD at the same time, and has only one interlayer insulating film. Provided is a technique for crystallizing a silicon film at the above temperature and in a short time that does not substantially cause a problem.

[0008]

As a result of the research conducted by the present inventor,
It has been revealed that the addition of a trace amount of a catalyst material to the substantially amorphous silicon coating can promote crystallization, lower the crystallization temperature, and shorten the crystallization time. Suitable catalyst elements are nickel (Ni), iron (Fe), cobalt (Co) and platinum (Pt). Specifically, a film, particles, clusters, etc. containing these catalytic element simple substance or a compound such as a silicide are formed in intimate contact under or on the amorphous silicon film, or amorphous silicon is formed by a method such as ion implantation. These catalytic elements can be crystallized by introducing these catalytic elements into the film and then thermally annealing them at a suitable temperature, typically 580 ° C. or lower.

As a matter of course, the higher the annealing temperature, the shorter the crystallization time. Further, there is a relationship that the higher the concentration of the catalyst element, the lower the crystallization temperature and the shorter the crystallization time. According to the research conducted by the present inventors, in order to promote crystallization, the concentration of at least one of these elements is 1 × 10 ¹⁷ cm ⁻³ , preferably 5 × 10 ¹⁸ cm 3.
^-It turns out that it is necessary to exist more than ^-3 .

On the other hand, all of the above catalyst materials are unfavorable materials for silicon, so it is desirable that the concentration thereof be as low as possible. In the present inventors' research, especially when used as an active region, the total concentration of these catalyst materials is 2 in order to obtain sufficient reliability and characteristics.
It is desired not to exceed × 10 ²⁰ cm ^-3 . On the other hand, it has been clarified that even if a relatively large amount is present in the source, drain, etc., it does not cause a problem.

Further, such a catalytic element has the effect of crystallizing the surroundings by diffusing during annealing. For example, when annealing is performed at 550 ° C. for 4 hours, these catalytic elements diffuse into the periphery of 10 to 20 μm and crystallize the periphery. Therefore, if the width of the gate electrode of the TFT is 20 μm, preferably 10 μm or less,
Similarly, before and after introducing the N-type or P-type impurity, a catalyst element is similarly introduced into the source and the drain, and by annealing this, crystallization proceeds laterally, and the active region in which the catalyst element is not introduced is introduced. The (channel formation region) can also be crystallized. In addition, generally, in this method, the concentration of the catalytic element in the active region is lower than the concentration of the catalytic element in the source and drain. This lateral crystallization depends on the annealing temperature and time and the concentration of the catalytic element. Therefore, by optimizing these, the crystalline silicon region and the amorphous silicon region can be freely formed. For example, two kinds of TFT gate electrodes having widths of 5 μm and 30 μm are prepared,
It is also possible to use a crystal silicon TFT having a thickness of 5 μm and an amorphous silicon TFT having a thickness of 30 μm.

The present inventor has paid attention to the effect of this catalytic element, and by utilizing this effect, it has become possible to lower the conductivity of the impurity region by annealing at a lower temperature for a shorter time. In the present invention, the impurity region, the active region of the TFT, and the intrinsic region of the TFD are crystallized at a lower temperature than before by taking advantage of the characteristics of crystallization by the above-mentioned catalyst material
A method has been found that activates and simplifies the problematic process, that is, reduces the number of film forming steps. The outline is shown below. Amorphous silicon film formation'Introduction of catalytic element (by ion implantation or ion doping method) (Also possible to form a substance having a catalytic element on a silicon film) Insulating film (gate insulating film) film formation TFT gate Electrode, TFD mask material formation Doping impurity introduction (by ion implantation or ion doping method) Doping impurity activation (600 ° C or less, within 8 hours) Interlayer insulator formation TFT source / drain electrode formation

Alternatively, formation of amorphous silicon film, formation of insulating film (gate insulating film), formation of gate electrode of TFT, mask material of TFD, introduction of doping impurities (by ion implantation or ion doping method) 'Introduction of catalytic element (By ion implantation or ion doping method) (It may be formed by depositing a substance having a catalytic element on a silicon film) Activation of doping impurities (600 ° C or less, within 8 hours) Formation of interlayer insulator TFT source / drain Electrode formation

In these steps, the latter and 'can also reverse their order. Means such as an ion implantation method is desirable from the viewpoint of precisely controlling the concentration of the catalytic element. 6 for crystallization and activation
A temperature of 00 ° C. or lower, typically 550 ° C. or lower, is sufficient, and an annealing time of 8 hours or less, typically 4 hours or less is sufficient. In particular, when the catalyst element was evenly distributed from the beginning by the ion implantation method or the ion doping method, the crystallization was extremely easy to proceed.

In the present invention, the structure of the TFD will be briefly described. In contrast to the conventional TFD having a layered structure, the TFD of the present invention is characterized by having a planar (planar) structure. . In the present invention, the active region of the TFT and the intrinsic region of the TFD start from the same amorphous silicon film. For this reason, conventionally, it was necessary to form a two-layer silicon film, whereas in the present invention, formation of a single-layer silicon film is sufficient. Then, the N layer and the P layer, which have been conventionally required, can be obtained by forming the N layer and the P layer in a plane at the same time as the impurity doping of the TFT. That is, the N-type region of the TFD is formed when the N-type impurity is injected into the TFT, and the P-type region of the TFD is formed when the P-type impurity is injected into the TFT. As a result,
The interlayer insulator also becomes one layer.

Such a planar TFD has a feature not heretofore available. When a conventional TFD (having a shape as shown in FIG. 4) is used as an optical sensor, for example, the direction in which the electric field generated inside the semiconductor is applied is perpendicular to the light irradiation surface, and the light irradiation intensity is applied by the electric field. The direction was not uniform, and electrons / holes were efficiently generated and could not be taken out to the outside. In addition, the TFD may be short-circuited due to pinholes between layers. In the present invention, since the direction of the electric field generated in the TFD is parallel to the light irradiation surface, the light intensity in the electric field direction is constant, the photoelectric conversion efficiency is improved, and a short circuit hardly occurs.

Further, in the present invention, due to the action of the catalytic element, a thin amorphous silicon film of 100 nm or less which is not crystallized by ordinary thermal annealing is also crystallized. The thickness of the crystalline silicon film is required to be 100 nm or less, preferably 50 nm or less from the viewpoint of preventing pinholes and insulation defects in the gate insulating film in the step portion of the TFT, and disconnection of the gate electrode. Conventionally, it could not be realized by a method other than laser crystallization, but according to the present invention, it could be realized by thermal annealing even at low temperature. It goes without saying that this contributes to further improvement in yield. In addition, even when the TFD is used as an optical sensor, the use of a thin semiconductor layer improves the SN ratio and photoelectric conversion efficiency. Hereinafter, the present invention will be described in more detail with reference to examples.

[0018]

[Embodiment] [Embodiment 1] FIG. 1 shows a cross-sectional view of a manufacturing process of this embodiment. First, the substrate (Corning 7059) 10
An underlying film 11 of silicon oxide having a thickness of 200 nm was formed thereon by a sputtering method. Further, an intrinsic (I-type) amorphous silicon film having a thickness of 50 to 150 nm, for example 150 nm, was deposited by the plasma CVD method. Next, nickel ions were implanted into the obtained amorphous silicon film by the ion implantation method. Dose amount is 1 × 10 ¹³
˜5 × 10 ¹⁴ cm ⁻² , for example, 5 × 10 ¹³ cm ⁻² .
As a result, 5 × 10 ¹⁸ is contained in the amorphous silicon film.
Nickel was implanted at a concentration of about cm ⁻³ . (Fig. 1
(A))

Next, patterning was performed by photolithography to form island-shaped silicon regions 12a (for TFT) and 12b (for TFD). Further, a 100-nm-thick silicon oxide film 13 was deposited as a gate insulating film by a sputtering method. For sputtering, silicon oxide is used as a target, the substrate temperature during sputtering is 200 to 400 ° C., for example 250 ° C., the sputtering atmosphere is oxygen and argon, and argon / oxygen = 0 to 0.
It was set to 0.5, for example, 0.1 or less. Subsequently, decompression C
According to the VD method, the thickness is 600 to 800 nm, for example 60
A 0 nm silicon film (containing 0.1-2% phosphorus) was deposited. It is desirable that the steps of forming the silicon oxide and the silicon film are continuously performed. Then, the silicon film is patterned to form the gate electrodes 14a and 14b of the TFT.
And the mask material 14c of TFD was formed. (Fig. 1
(B))

Next, as shown in FIG. 1C, a photoresist mask 15a was formed, and an impurity (phosphorus) was implanted into the silicon region by plasma doping using the gate electrode as a mask. Phosphine (PH ₃ ) is used as the doping gas, the acceleration voltage is 60 to 90 kV,
For example, it is set to 80 kV. Dose amount is 1 × 10 ¹⁵ to 8 × 1
It was set to 0 ¹⁵ cm ^-2 , for example, 2 × 10 ¹⁵ cm ^-2 . As a result, the N-type impurity region 16a of the TFT and the N-type impurity region 17n of the TFD were formed. (Fig. 1 (C))

Next, as shown in FIG. 1D, a photoresist mask 15b was formed, and impurities (boron) were implanted into the silicon region by plasma doping using the gate electrode as a mask. Diborane (B ₂ H ₆ ) was used as a doping gas, and the acceleration voltage was 40 to 80 k.
V, for example, 65 kV. The dose amount is 1 × 10 ¹⁵ to 8
It was set to × 10 ¹⁵ cm ^-2 , for example, 5 × 10 ¹⁵ . As a result, the P-type impurity region 16b of the TFT and the P-type impurity region 17p of the TFD were formed. N-type region 17 of TFD
An intrinsic region 17i is left between the n and P type regions 17p. (Fig. 1 (D))

Then, the impurities were activated by annealing at 500 ° C. for 4 hours in a reducing atmosphere. By this annealing, crystallization easily proceeded and the doping impurities were activated. After the crystallization was completed, the TFD mask material 14c was removed. (Fig. 1 (E))

Then, a silicon oxide film 18 having a thickness of 600 nm is formed.
Is formed by plasma CVD as an interlayer insulator,
A contact hole is formed in this, and the TFT is made of a metal material, for example, a multilayer film of titanium nitride and aluminum.
Electrodes / wirings 19a, 19b, 19c, TFD electrodes /
The wirings 19d and 19e are formed. Finally, annealing was performed at 350 ° C. for 30 minutes in a hydrogen atmosphere of 1 atm. The semiconductor circuit is completed through the above steps. (Fig. 1
(F))

In this step, both the silicon film and the interlayer insulator could be formed into one layer, as is clear from the figure. As a result, the film forming process was greatly reduced. Also, TFT
The concentration of nickel in the active region and the intrinsic region of TFD was measured by the secondary ion mass spectrometry (SIMS) method. As a result, nickel of 1 × 10 ^{18 to} 5 × 10 ¹⁸ cm ⁻³ was detected.

The TFD portion of the semiconductor circuit of this embodiment is shown in FIG. When this TFD is used as an optical sensor, light is incident from above. This TFD
The energy band diagram along AA 'of FIG.
As shown. In general, crystalline silicon has low photosensitivity. Therefore, in order to improve this, as shown in FIG. 2C, after removing the TFD mask 14c, a thickness of 100 is obtained.
A semiconductor film 17a having a high photosensitivity, such as hydrogenated amorphous silicon having a thickness of up to 800 nm, for example 300 nm, may be formed in close contact with the intrinsic region 17i.

For example, when amorphous silicon is used, since the light absorption coefficient is larger than that of the intrinsic region 17i of the crystalline silicon below, a large amount of carriers are generated in the amorphous silicon film 17a by the light irradiation from above. After that, it drifts to the intrinsic region 17i of crystalline silicon and is separated by the electric field applied thereto.

In the structure shown in FIG. 2C, carriers are generated in the amorphous semiconductor film 17a, and at the same time, carriers are also generated in the crystalline silicon semiconductor film 17i according to the wavelength dependence of its photosensitivity. Therefore, it becomes possible to convert light in a wider wavelength range into electricity. When an amorphous silicon film is used as the amorphous semiconductor film 17a, carbon, nitrogen, oxygen or the like may be added to change the wavelength dependence of the photosensitivity.

If the energy band width of the amorphous semiconductor film 17a is wider than that of the intrinsic region 17i, the carriers generated in the intrinsic region 17i are amorphous semiconductor film 17.
The carrier generated in the amorphous semiconductor film 17a is prevented from drifting to a and moves to the intrinsic region 17i along the gradient of the energy band. Therefore, the generated carrier can be taken out to the outside more efficiently.

[Embodiment 2] FIG. 3 shows a cross-sectional view of a manufacturing process of this embodiment. A 200 nm-thick base film 31 of silicon oxide was formed on the substrate (Corning 7059) 30 by a sputtering method, and an amorphous silicon film was formed by a plasma CVD method. Then, the amorphous silicon film is patterned to form the island-shaped silicon region 32a.
(For TFT) and 32b (for TFD) were formed. Furthermore, tetra-ethoxy-silane (Si (OC ₂ H ₅ ))
₄ , TEOS) and oxygen were used as raw materials, and a silicon oxide 33 having a thickness of 100 nm was formed as a gate insulating film by a plasma CVD method. As the raw material, trichlorethylene (C ₂ HCl ₃ ) was used in addition to the above gas. Before the film formation, oxygen was flown into the chamber at 400 ml / min, and the substrate temperature was 3
Plasma was generated at 00 ° C., total pressure 5 Pa, and RF power 150 W, and this state was maintained for 10 minutes. Then, 300 ml / min oxygen and 15 ml / m TEOS in the chamber.
A silicon oxide film was formed by introducing in and trichlorethylene at 2 ml / min. The substrate temperature, RF power, and total pressure were 300 ° C., 75 W, and 5 Pa, respectively. 1.33 × 10 ⁴ Pa in the chamber after the film formation is completed
Was introduced, and hydrogen annealing was performed at 350 ° C. for 35 minutes.

Subsequently, by the sputtering method,
A tantalum film having a thickness of 600 to 800 nm, for example 600 nm, was deposited. It is desirable that the steps of forming the silicon oxide 33 and the tantalum film be continuously performed. Chromium, molybdenum, tungsten, titanium, or the like may be used instead of tantalum, but it is required that they can withstand the subsequent annealing step. Then, the tantalum film is patterned to form the gate electrodes 34a, 34b, T of the TFT.
An FD mask material 34c was formed. At this time, the width (= channel length) of the gate electrode of the TFT is 5 to 10 μm, and TF is
The width of the mask material D was 20 to 50 μm. Further, the surface of this tantalum wiring was anodized to form an oxide layer on the surface. Anodization was performed in a 1-5% ethylene glycol solution of tartaric acid. The thickness of the obtained oxide layer was 200 nm. (Fig. 3 (A))

Next, impurities (phosphorus) were implanted into the silicon region by the plasma doping method. Phosphine (PH ₃ ) was used as the doping gas, and the acceleration voltage was 6
It was set to 0 to 90 kV, for example, 80 kV. 1x dose
10 ¹⁵ to 8 × 10 ¹⁵ cm ^-2 , for example, 2 × 10 ¹⁵ cm ^-2
And Thus, the N-type impurity region 35 was formed. (FIG. 3B) Subsequently, nickel ions were implanted by the ion implantation method. The dose amount was set to 1 × 10 ^{13 to} 5 × 10 ¹⁴ cm ⁻² , for example, 5 × 10 ¹³ cm ⁻² . As a result, nickel was implanted into the amorphous silicon film at a concentration of about 5 × 10 ¹⁸ cm ⁻³ . (Fig. 3 (C))

Further, the left TFT (N-channel type TF
T) and the area on the right side of the TFD (N-type area).
Mask with dyst 36 and again plasma doping method
And the silicon area of the TFT (P-channel TFT) on the right side
And a region (P-type region) on the left side of the TFD and
Was injected. As a doping gas, diborane (B
₂H₆), The acceleration voltage is 50 to 80 kV, for example, 6
It was set to 5 kV. Dose amount is 1 × 10¹⁵~ 8 × 10¹⁵cm
^-2, For example, 5 × 10 more than the previously implanted phosphorus ¹⁵cm
^-2And As a result, the N-type impurity region 37 of the TFT is formed.
a, the P-type region 37b and the N-type region 38n of the TFD,
A P-type region 38p was formed. (Fig. 3 (D))

Then, the impurities were activated by annealing at 500 ° C. for 4 hours in a hydrogen reducing atmosphere of 0.1 to 1 atm. At this time, since nickel has diffused into the regions 37a, 37b and 38p, 38n into which nickel was previously implanted, this annealing facilitates the crystallization and activates the doping impurities. Also,
Nickel diffused into the active region of the TFT, and crystallization proceeded. On the other hand, nickel did not exist in the silicon in the intrinsic region 38i of the TFD, particularly in the central portion, and since there was no diffusion from the surroundings, crystallization did not occur. That is, TFT
Was crystallized over the entire region, and in TFD, the impurity region and a part of the intrinsic region in contact with the impurity region were crystallized, and the central portion of the intrinsic region 38i was in an amorphous state. (Fig. 3
(E))

Subsequently, a 200 nm thick silicon oxide film 39 is formed.
Is formed by plasma CVD as an interlayer insulator,
A contact hole is formed in this, and the TFT is made of a metal material, for example, a multilayer film of titanium nitride and aluminum.
Electrodes / wirings 40a, 40b, 40c, TFD electrodes /
Wirings 40d and 40e are formed. Finally, annealing was performed at 350 ° C. for 30 minutes in a hydrogen atmosphere of 1 atm. The semiconductor circuit is completed through the above steps. (Fig. 3
(F))

In this embodiment, the TFD mask material 34c is used.
Is insulated from other gate electrode wirings and is in a floating potential state. However, in this case, the operation of the TFD may be hindered by the accumulation of some electric charge. if,
If stable operation is required, it may be set to the same potential as the P-type region or N-type region of the TFD. Further, in this embodiment, since the mask material 34c is present on the intrinsic region 38i, when the TFD is used as an optical sensor, it is necessary to make light incident from the substrate side. In the case of the present embodiment, it is difficult to bring the amorphous semiconductor film into close contact with the intrinsic region in order to improve the photosensitivity as shown in FIG. 2C shown as a variation of the first embodiment. Different from No. 1, there is no problem because the amorphous region with good photosensitivity remains in the intrinsic region 38i.

[0036]

According to the present invention, a crystalline silicon TFT is provided.
The number of processes for manufacturing a semiconductor circuit having TFD and TFD can be reduced and mass productivity can be improved. Further, the present invention can also be performed by crystallization of silicon at a low temperature of 500 ° C. and a short time of 4 hours, for example.
Throughput can be improved. In addition, conventionally, when a process of 600 ° C. or higher is adopted, shrinkage or warpage of the glass substrate has been a problem as a cause of a decrease in yield, but by using the present invention, such a problem is solved at once. Resulting in.

This means that a large area substrate can be processed at one time. That is, by processing a large-area substrate, a large number of integrated circuits or the like can be cut out from one substrate, whereby the unit price can be significantly reduced. Thus, the present invention is an industrially useful invention.

[Brief description of drawings]

1A to 1C are cross-sectional views of a manufacturing process of Example 1.

FIG. 2 shows the TFD obtained in Example 1 and its band diagram.

3A to 3C are sectional views showing a manufacturing process of the second embodiment.

FIG. 4 shows a conventional manufacturing process example (cross-sectional view).

[Explanation of symbols]

10 ... Substrate 11 ... Base insulating film (silicon oxide) 12 ... Island silicon region 13 ... Gate insulating film (silicon oxide) 14 ... Gate electrode and mask material (phosphorus-doped silicon) ) 15 ... Doping mask (photoresist) 16 ... TFT source / drain region 17 ... TFD impurity region / intrinsic region 18 ... Interlayer insulator (silicon oxide) 19 ... Metal wiring Electrode (titanium nitride / aluminum)

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI H01L 27/092 H01L 29/78 613A 27/146 618F 627G (56) Reference JP-A-6-275808 (JP, A) JP JP 4-119664 (JP, A) JP 2-140915 (JP, A) JP 4-206969 (JP, A) JP 60-154660 (JP, A) JP 57-194518 (JP , A) JP 58-23479 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) H01L 29/786 H01L 21/336 H01L 21/8238 H01L 21/20 H01L 27/08 331 H01L 27/092 H01L 27/146

Claims (5)

(57) [Claims] 1. A first source region, a first drain region and a first drain region on a substrate .
Located between a source region and the first drain region
P-channel TFT having first channel forming region
And a second source region, a second drain region and the second
Located between a source region and the second drain region
N-channel TFT having second channel formation region
And a thin film diode having an N-type region, a P-type region and an intrinsic region
A semiconductor circuit having a de, wherein the first source region, said first drain region, wherein
A first channel formation region, the second source region, the
The second drain region and the second channel formation region are
The N-type region, the P-type region and the intrinsic region are formed on the first silicon film on the substrate,
It is formed on the second silicon film on the plate, and the first silicon film and the second silicon film are the same.
A layer, the first source region, the first drain region, and
The P-type region includes P-type impurities, the second source region, the second drain region, and
The N-type region includes an N-type impurity, the intrinsic region is amorphous silicon, and the first silicon film, the P-type region, and the N-type region are included.
Area is a metal that promotes crystallization of amorphous silicon
Crystalline silicon containing an element, the first source region, the first drain region, the
Second source region, the second drain region, the P-type
The semiconductor region and the N-type region containing phosphorus.
Body circuit. 2. The semiconductor circuit according to claim 1, wherein the P-type impurity is boron. 3. A any one of claims 1 to 2,
It said first and said second channel forming region is the amorphadiene
A semiconductor circuit comprising a metal element that promotes crystallization of fast silicon . 4. The method according to any one of claims 1 to 3 ,
The first source region, the first drain region, the
Gold for promoting crystallization of the amorphous silicon contained in the second source region and the second drain region
The concentration of the group element is 1 × 10 ¹⁷ cm ⁻³ or more and 2 × 10 ²⁰ cm ⁻³
A semiconductor circuit characterized by being less than. 5. The method according to any one of claims 1 to 4 ,
Metal element that promotes crystallization of the amorphous silicon
The semiconductor circuit is characterized in that the element is nickel, iron, cobalt or platinum.