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JP3543254B2 - Structure of a semiconductor device having a plurality of IC chips - Google Patents

Structure of a semiconductor device having a plurality of IC chips Download PDF

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Publication number
JP3543254B2
JP3543254B2 JP15991297A JP15991297A JP3543254B2 JP 3543254 B2 JP3543254 B2 JP 3543254B2 JP 15991297 A JP15991297 A JP 15991297A JP 15991297 A JP15991297 A JP 15991297A JP 3543254 B2 JP3543254 B2 JP 3543254B2
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Prior art keywords
chip
electrode pad
main
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barrier metal
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JP15991297A
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JPH118348A (en
Inventor
和孝 柴田
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Rohm Co Ltd
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Rohm Co Ltd
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Priority to JP15991297A priority Critical patent/JP3543254B2/en
Application filed by Rohm Co Ltd filed Critical Rohm Co Ltd
Priority to US09/155,134 priority patent/US6133637A/en
Priority to EP98900725A priority patent/EP0890989A4/en
Priority to KR10-1998-0707403A priority patent/KR100522223B1/en
Priority to KR10-2004-7000090A priority patent/KR100467946B1/en
Priority to PCT/JP1998/000281 priority patent/WO1998033217A1/en
Publication of JPH118348A publication Critical patent/JPH118348A/en
Priority to US09/612,480 priority patent/US6458609B1/en
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Publication of JP3543254B2 publication Critical patent/JP3543254B2/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/831—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
    • H01L2224/83101—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus as prepeg comprising a layer connector, e.g. provided in an insulating plate member
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]

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Description

【０００１】
【発明の属する技術分野】
本発明は、複数個のＩＣチップを、その相互間を電気的に接続した状態で一体的に接合した半導体装置の構造に関するものである。
【０００２】
【従来の技術】
従来、二つのＩＣチップを、その相互間を電気的に接続した状態で、一体的に接合するに際しては、前記両ＩＣチップのうち一方のメインＩＣチップに形成した各電極パッド及び前記両ＩＣチップのうち他方のサブＩＣチップに形成した各電極パッドのうちいずれか一方の電極パッドにバンプを設けて、このバンプを、他方の電極パッドに対して圧着すると言う方法を採用している。
【０００３】
【発明が解決しようとする課題】
しかし、この方法において、メインＩＣチップとサブＩＣチップとの一体化を、メインＩＣチップの各電極パッド及びサブＩＣチップの各電極パッドのうちいずれか一方の電極パッドに設けたバンプにおける他方の電極パッドへの圧着のみに依存することができず、前記した圧着後において、両ＩＣチップの間に、その両者を一体的に接着するための合成樹脂を充填するようにしなければならないから、両ＩＣチップを一体化することに要するコストが大幅にアップすると言う問題があった。
【０００４】
しかも、前記ＩＣチップにおける電極パッドは、一般的に言ってアルミニウム製であるのに対し、バンプは、アルミニウムと異質の金又は半田製であることにより、一方の電極パッドに設けたバンプを、他方の電極パッドに対して圧着することの確実性が低く、その確実性を確保するためには、その押圧力を可成り強くしなければならず、このバンプを他方の電極パッドに圧着するときに、この他方の電極パッドに対して大きなダメージを及ぼすことになるから、電気的接続の信頼性が低くて、不良品の発生率が高いと言う問題もあった。
【０００５】
本発明は、これらの問題を解消できるようにした半導体装置の構造を提供することを技術的課題とするものである。
【０００６】
【課題を解決するための手段】
この技術的課題を達成するため本発明は、
「少なくとも上面に回路素子、この回路素子に対する電極パッドを形成したメインＩＣチップと、少なくとも片面に回路素子とこの回路素子に対する電極パッドとを形成したサブＩＣチップとから成り、前記サブＩＣチップを、前記メインＩＣチップの上面側に、当該サブＩＣチップにおける回路素子及び電極パッドが前記メインＩＣチップにおける回路素子及び電極パッドに対面するように下向きにして配設し、前記メインＩＣチップにおける電極パッド及びサブＩＣチップにおける電極パッドのうち一方の電極パッドにバンプを設け、前記メインＩＣチップにおける電極パッド及びサブＩＣチップにおける電極パッドのうち他方の電極パッドが設けられる側のＩＣチップに、当該ＩＣチップにおける回路素子及び前記他方の電極パッドを覆う保護膜を形成し、この保護膜のうち前記他方の電極パッドを覆う部分に、当該電極パッドの周囲に保護膜の電極パッドに対する重なり部を残して開口部を設け、前記他方の電極パッドのうち前記開口部内の部分に、バリアメタルを、当該バリアメタルの周囲が前記保護膜のうち前記開口部の周囲縁の部分に重なるように形成して、前記バリアメタルにおける上面のうち前記開口部の部分に前記バンプが嵌まる凹所を設け、更に、前記両ＩＣチップの相互間を、その間に介挿した導電粒子混入の接着フィルムにて、前記バンプが当該接着フィルムを前記バリアメタルに対して圧縮変形するようにして接着する。」
と言う構成にした。
【０００７】
【発明の作用・効果】
このように構成することにより、両ＩＣチップを、その間に介挿した接着フィルムにて強固に一体化することができる一方、前記接着フィルムを、一方の電極パッドに設けたバンプが他方の電極パッドに設けたバリアメタルに対して圧縮変形することにより、この接着フィルムに混入されている導電粒子が、このバンプと、他方の電極パッドの表面に形成されているバリアメタルとの間に挟まれることになり、しかも、この導電粒子が前記バンプとバリアメタルとの間から横方向に逃げるのを、前記バリアメタルの上面に設けられる凹所にて阻止でき、換言すると、前記バリアメタルの上面における凹所内に、多くの導電粒子を確保することができるから、前記接着フィルムへの導電粒子の混入量を多くすることなく、メインＩＣチップにおける各電極パッドと、サブＩＣチップにおける各電極パッドとの相互間を電気的に確実に接続することができるのである。
【０００８】
しかも、前記一方の電極パッドに設けたバンプが他方の電極パッドに対してダメージを及ぼすことを、この他方の電極パッドの表面に形成されているバリアメタルによって確実に低減できるのである。
従って、本発明によると、メインＩＣチップとサブＩＣチップとを、その間に接着フィルムを介挿したのち押圧するだけで、その相互間を電気的に接続した状態で簡単に一体化することができる一方、その相互間に電気的な接続に際して、電極パッドに対して及ぼすダメージが小さいと共に、電気的接続の信頼性を高くて、不良品の発生率が低いから、前記一体化が簡単にできることと相俟って、製造コストを大幅に低減できる効果を有する。
【０００９】
【発明の実施の形態】
以下、本発明の実施の形態を、一つのパッケージ体にて二つのＩＣチップを密封した形式の半導体装置に適用した場合の図面（図１〜図８）について説明する。
この図において、符号１は、矩形状のチップマウント部１ａと、このチップマウント部１ａにおける四つの各辺から外向きに延びる複数本のリード端子１ｂとを備えたリードフレームを示す。
【００１０】
また、符号２は、前記リードフレーム１におけるチップマウント部１ａに対してダイボンディングされるメインＩＣチップを示し、このメインＩＣチップ２の上面には、図示しない能動素子又は受動素子等のような回路素子の多数個が形成されていると共に、その周囲にワイヤボンディング用電極パッド２ａの多数個が、その内側に後述するサブＩＣチップ３に対する接続用の電極パッド２ｂの多数個が形成されている。
【００１１】
この場合において、前記メインＩＣチップ２の上面には、図３に示すように、当該上面に形成されている各種の回路素子を覆う保護膜２ｃが、前記各電極パッド２ｂの部分に開口部を設けて形成され、更に、前記各電極パッド２ｂの部分には、バリアメタル２ｅが、当該電極パッド２ｂのうち前記保護膜２ｃにおける開口部内の部分及び前記保護膜２ｃのうち開口部の周囲縁の部分を覆うように形成されている。
つまり、このように構成することにより、前記バリアメタル２ｅの上面に、前記保護膜２ｃの膜厚さと略等しい深さの凹所を形成することができる。
なお、このバリアメタル２ｅは、例えば、チタンを下層としタングステンを上層とするか、クロムを下層とし銀を上層とする二層構造に構成されている。
【００１２】
更にまた、符号３は、前記メインＩＣチップ２の上面に一体化されるサブＩＣチップを示し、このサブＩＣチップ３における表裏両面のうち少なくとも片面には、前記メインＩＣチップ２と同様に図示しない能動素子又は受動素子等のような回路素子の多数個が形成されている共に、前記メインＩＣチップ２における各電極パッド２ｂの各々に対応する箇所ごとに接続用の電極パッド３ａが形成されている。
【００１３】
そして、前記サブＩＣチップ３を、前記メインＩＣチップ２に対して、これらにおける電極パッド２ｂ，３ｂの相互間を電気的に接続した状態で一体化するに際しては、前記サブＩＣチップ３における各電極パッド３ａの各々に、金又は半田等によるバンプ３ｂを設けるのである。
次いで、前記サブＩＣチップ３を、その回路素子、電極パッド３ａ及びバンプ３ｂを形成した片面を下向きにして、前記メインＩＣチップ２の上面側に配設し、その間に導電粒子を混入した接着フィルム４を介挿したのち、前記サブＩＣチップ３を、メインＩＣチップ２に向かって、その間における前記接着フィルム４を、図５に示すように、各バンプ３ｂにより圧縮変形するように押圧し、この押圧を保持した状態で、加熱等にて前記接着フィルム４を乾燥・硬化することにより、前記サブＩＣチップ３を、メインＩＣチップ２に対して、その間に介挿した接着フィルム４により確実に且つ強固に一体化できるのである。
【００１４】
また、前記サブＩＣチップ３における各バンプ３ｂが、前記接着フィルム４を、圧縮変形することにより、この接着フィルム４に混入されている導電粒子が、この各バンプ３ｂと、メインＩＣチップ２における各電極パッド２ｂの表面に形成したバリアメタル２ｅとの間に挟まれることにより、サブＩＣチップ３における各電極パッド３ａと、メインＩＣチップ２における各電極パッド２ｂとの相互間を電気的に接続することができるのであり、前記した押圧のときにおいて、サブＩＣチップ３における各電極パッド３ａに設けたバンプ３ｂが、メインＩＣチップ２における各電極パッド２ｂに対してダメージを及ぼすことを、この各電極パッド２ｂの表面に形成されているバリアメタル２ｄによって確実に低減できるのである。
【００１５】
この場合において、図示のように、メインＩＣチップ２の上面における保護膜２ｃのうち各電極パッド２ｂを覆う部分に、当該電極パッド２ｂの周囲に保護膜２ｃの電極パッド２ｂに対する重なり部を残して開口部を設ける一方、バリアメタル２ｄを、電極パッド２ｂのうち前記保護膜２ｃにおける開口部内の部分及び前記保護膜２ｃのうち開口部の周囲縁の部分を覆うように形成することにより、このバリアメタル２ｄの上面には、前記バンプ３ｂが嵌まる凹所が形成されることになる。
【００１６】
これにより、前記接着フィルム４がバンプ３ｂによって前記バリアメタル２ｄにおける凹所内に向かって圧縮変形されるときに、この接着フィルム４に混入した導電粒子が前記バンプ３ｂとバリアメタル２ｄとの間から横方向に逃げるのを、前記バリアメタル２ｄの上面に形成される凹所にて阻止でき、換言すると、前記バリアメタル２ｄの上面における凹所内に、多くの導電粒子を確保することができるから、前記接着フィルム４への導電粒子の混入量を多くすることなく、電気的接続の確実性を向上できるのである。
【００１７】
このようにして、メインＩＣチップ２に対してサブＩＣチップ３を一体化すると、このメインＩＣチップ２を、図６に示すように、前記リードフレーム１におけるチップマウント部１ａに対してダイボンディングし、次いで、このメインＩＣチップ２における各ワイヤボンディング用電極パッド２ａと、リードフレーム１における各リード端子１ｂとの間を、細い金属線５によるワイヤボンディングにて電気的に接続したのち、これらの全体を、図７に示すように、合成樹脂製のパッケージ体６にて密封し、次いで、図８に示すように、リードフレーム１から切り離したのち、各リード端子１ｂのうちパッケージ体６から突出する部分を、パッケージ体６の下面の同一平面状に折り曲げることにより、密封型半導体装置の完成品とするのである。
【００１８】
なお、前記の説明は、バンプ３ｂを、サブＩＣチップ３における各電極パッド３ａに設けて、このバンプ３ｂを、メインＩＣチップ２における各電極パッド２ｂに設けたバリアメタル２ｄに対して電気的に接続する場合を示したが、これに代えて、バンプを、メインＩＣチップ２における各電極パッド２ｂに設けて、このバンプを、サブＩＣチップ３における各電極パッド３ａに設けたバリアメタルに対して電気的に接続するように構成にしても良く、また、本発明は、前記のように、メインＩＣチップ２に対して一つのサブＩＣチップ３を一体化することに限らず、メインＩＣチップ２に対して二つのサブＩＣチップ３を一体化する場合にも適用できることは言うまでもない。
【図面の簡単な説明】
【図１】本発明の実施の形態を示す分解斜視図である。
【図２】図１の縦断正面図である。
【図３】図２の要部拡大図である。
【図４】サブＩＣチップをメインＩＣチップに対して一体化した状態を示す縦断正面図である。
【図５】図４の要部拡大図である。
【図６】リードフレームに対してマウントした状態を示す縦断正面図である。
【図７】全体をパッケージ体に密封した状態を示す縦断正面図である。
【図８】半導体装置の縦断正面図である。
【符号の説明】
１ リードフレーム
１ａ チップマウント部
１ｂ リード端子
２ メインＩＣチップ
２ｂ 電極パッド
２ｃ 保護膜
２ｄ バリアメタル
３ サブＩＣチップ
３ａ 電極パッド
３ｂ バンプ
４ 接着フィルム
５ 金属線
６ パッケージ体[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a structure of a semiconductor device in which a plurality of IC chips are integrally joined while electrically connecting the IC chips to each other.
[0002]
[Prior art]
Conventionally, when two IC chips are integrally connected with each other in a state where they are electrically connected to each other, each electrode pad formed on one main IC chip of the two IC chips and the two IC chips Of the respective electrode pads formed on the other sub IC chip, a bump is provided on one of the electrode pads, and the bump is pressed against the other electrode pad.
[0003]
[Problems to be solved by the invention]
However, in this method, the integration of the main IC chip and the sub IC chip is performed by combining the other electrode on the bump provided on one of the electrode pads of the main IC chip and the electrode pads of the sub IC chip. It is not possible to rely solely on the pressure bonding to the pad, and after the above-mentioned pressure bonding, it is necessary to fill between the two IC chips with a synthetic resin for integrally bonding them. There has been a problem that the cost required for integrating the chips increases significantly.
[0004]
In addition, the electrode pads of the IC chip are generally made of aluminum, whereas the bumps are made of gold or solder different from aluminum, so that the bumps provided on one electrode pad can be replaced with the bumps provided on the other. There is a low degree of certainty of crimping against the electrode pad, and in order to ensure the certainty, the pressing force must be considerably increased. However, since the other electrode pad is seriously damaged, there is also a problem that the reliability of the electrical connection is low and the incidence of defective products is high.
[0005]
It is a technical object of the present invention to provide a structure of a semiconductor device capable of solving these problems.
[0006]
[Means for Solving the Problems]
To achieve this technical problem, the present invention
"At least the upper surface to the circuit element, and the main IC chip forming the electrode pads for the circuit element consists of a sub-IC chip forming the electrode pads for the circuit element and the circuit element on at least one surface, the sub-IC chip, On the upper surface side of the main IC chip, a circuit element and an electrode pad of the sub IC chip are disposed facing downward so as to face the circuit element and the electrode pad of the main IC chip. A bump is provided on one of the electrode pads of the sub IC chip, and the other of the electrode pads on the main IC chip and the sub IC chip on which the other electrode pad is provided is provided with a bump. Circuit element and the other electrode pad A protective film is formed, and in the portion of the protective film covering the other electrode pad, an opening is provided around the electrode pad except for an overlapping portion of the protective film with respect to the electrode pad. A barrier metal is formed in a portion inside the opening so that the periphery of the barrier metal overlaps with a peripheral edge portion of the opening in the protective film. A concave portion where the bump fits is provided in a portion, and furthermore, an adhesive film containing conductive particles interposed between the two IC chips is provided, and the bump is attached to the barrier metal with respect to the barrier metal. Adhesive so that it can be compressed and deformed. "
It was configured to say.
[0007]
[Action and Effect of the Invention]
With this configuration, the two IC chips can be firmly integrated with the adhesive film interposed therebetween, while the adhesive film is provided on one electrode pad with the bump provided on the other electrode pad. The conductive particles mixed in the adhesive film are sandwiched between the bumps and the barrier metal formed on the surface of the other electrode pad due to the compression deformation of the barrier metal provided in the above. In addition, the conductive particles can be prevented from laterally escaping from between the bump and the barrier metal by the recess provided on the upper surface of the barrier metal. In other words, the recesses on the upper surface of the barrier metal can be prevented. Since a large number of conductive particles can be secured in the place, the amount of the conductive particles mixed into the adhesive film can be increased without increasing the amount of the conductive particles mixed into the main IC chip. And the electrode pads that, it is possible to reliably electrically connect the mutually between each of the electrode pads in the sub-IC chip.
[0008]
Moreover, the damage of the bumps provided on the one electrode pad to the other electrode pad can be reliably reduced by the barrier metal formed on the surface of the other electrode pad.
Therefore, according to the present invention, the main IC chip and the sub IC chip can be easily integrated in a state where they are electrically connected only by pressing after inserting the adhesive film therebetween. On the other hand, at the time of electrical connection between them, the damage to the electrode pad is small, the reliability of the electrical connection is high, and the incidence of defective products is low. In addition, there is an effect that the manufacturing cost can be significantly reduced.
[0009]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, drawings (FIGS. 1 to 8) in which the embodiment of the present invention is applied to a semiconductor device in which two IC chips are sealed in one package body will be described.
In this drawing, reference numeral 1 denotes a lead frame including a rectangular chip mount 1a and a plurality of lead terminals 1b extending outward from four sides of the chip mount 1a.
[0010]
Reference numeral 2 denotes a main IC chip that is die-bonded to the chip mount portion 1a of the lead frame 1. A circuit such as an active element or a passive element (not shown) is provided on the upper surface of the main IC chip 2. both the large number of elements are formed, a large number of wire bonding electrode pads 2a around it, a large number of electrode pads 2b for connection is formed for the sub IC chip 3 to be described later on the inside .
[0011]
In this case, on the upper surface of the main IC chip 2, as shown in FIG. 3, a protective film 2c covering various circuit elements formed on the upper surface is provided with an opening at each of the electrode pads 2b. Further, a barrier metal 2e is formed on the portion of each of the electrode pads 2b, and a portion of the electrode pad 2b in the opening of the protective film 2c and a portion of the peripheral edge of the opening in the protective film 2c. It is formed so as to cover the portion.
That is, with this configuration, a recess having a depth substantially equal to the thickness of the protective film 2c can be formed on the upper surface of the barrier metal 2e.
The barrier metal 2e has, for example, a two-layer structure including titanium as a lower layer and tungsten as an upper layer, or chromium as a lower layer and silver as an upper layer.
[0012]
Further, reference numeral 3 denotes a sub IC chip integrated on the upper surface of the main IC chip 2, and at least one of the front and back surfaces of the sub IC chip 3 is not shown like the main IC chip 2. A large number of circuit elements such as active elements or passive elements are formed, and connection electrode pads 3a are formed at locations corresponding to the respective electrode pads 2b on the main IC chip 2. .
[0013]
When the sub IC chip 3 is integrated with the main IC chip 2 while electrically connecting the electrode pads 2b and 3b to each other, each electrode of the sub IC chip 3 is A bump 3b made of gold, solder, or the like is provided on each of the pads 3a.
Then, the sub IC chip 3 is disposed on the upper surface side of the main IC chip 2 with one side on which the circuit elements, the electrode pads 3a, and the bumps 3b are formed facing downward, and an adhesive film mixed with conductive particles therebetween. 4, the sub IC chip 3 is pressed toward the main IC chip 2 so that the adhesive film 4 therebetween is compressed and deformed by the bumps 3 b as shown in FIG. By drying and curing the adhesive film 4 by heating or the like while holding the pressure, the sub IC chip 3 is securely and reliably attached to the main IC chip 2 by the adhesive film 4 interposed therebetween. It can be firmly integrated.
[0014]
Each bump 3b of the sub IC chip 3 compresses and deforms the adhesive film 4, so that conductive particles mixed in the adhesive film 4 cause each bump 3b and each of the bumps 3b of the main IC chip 2 to deform. By being sandwiched between the electrode pad 2b and the barrier metal 2e formed on the surface of the electrode pad 2b, each electrode pad 3a in the sub IC chip 3 and each electrode pad 2b in the main IC chip 2 are electrically connected to each other. It is determined that the bumps 3b provided on the respective electrode pads 3a of the sub IC chip 3 damage the respective electrode pads 2b of the main IC chip 2 at the time of pressing. This can be reliably reduced by the barrier metal 2d formed on the surface of the pad 2b.
[0015]
In this case, as shown in the drawing, in the portion of the protective film 2c on the upper surface of the main IC chip 2 that covers each electrode pad 2b, an overlapping portion of the protective film 2c with respect to the electrode pad 2b is left around the electrode pad 2b. While providing the opening, the barrier metal 2d is formed so as to cover a portion of the electrode pad 2b inside the opening in the protective film 2c and a portion of the protective film 2c at a peripheral edge of the opening. On the upper surface of the metal 2d, a recess is formed to fit the bump 3b.
[0016]
Thus, when the adhesive film 4 is compressed and deformed by the bumps 3b into the recesses in the barrier metal 2d, the conductive particles mixed in the adhesive film 4 are laterally moved from between the bumps 3b and the barrier metal 2d. The escape in the direction can be prevented by the recess formed on the upper surface of the barrier metal 2d. In other words, a large number of conductive particles can be secured in the recess on the upper surface of the barrier metal 2d. The reliability of the electrical connection can be improved without increasing the amount of the conductive particles mixed into the adhesive film 4.
[0017]
When the sub IC chip 3 is integrated with the main IC chip 2 in this manner, the main IC chip 2 is die-bonded to the chip mount portion 1a of the lead frame 1 as shown in FIG. Then, after electrically connecting each of the wire bonding electrode pads 2a of the main IC chip 2 and each of the lead terminals 1b of the lead frame 1 by wire bonding with a thin metal wire 5, they are entirely connected. Is sealed with a package body 6 made of synthetic resin as shown in FIG. 7 and then separated from the lead frame 1 as shown in FIG. By bending the portion into the same plane on the lower surface of the package 6, a sealed semiconductor device is completed. .
[0018]
In the above description, the bump 3b is provided on each electrode pad 3a of the sub IC chip 3, and the bump 3b is electrically connected to the barrier metal 2d provided on each electrode pad 2b of the main IC chip 2. Although connection is shown, a bump is provided on each electrode pad 2b of the main IC chip 2 instead of this, and this bump is applied to the barrier metal provided on each electrode pad 3a of the sub IC chip 3. The present invention is not limited to integrating one sub IC chip 3 with the main IC chip 2 as described above. Needless to say, the present invention can be applied to the case where two sub IC chips 3 are integrated.
[Brief description of the drawings]
FIG. 1 is an exploded perspective view showing an embodiment of the present invention.
FIG. 2 is a vertical sectional front view of FIG.
FIG. 3 is an enlarged view of a main part of FIG. 2;
FIG. 4 is a longitudinal sectional front view showing a state where a sub IC chip is integrated with a main IC chip.
FIG. 5 is an enlarged view of a main part of FIG. 4;
FIG. 6 is a longitudinal sectional front view showing a state of being mounted on a lead frame.
FIG. 7 is a longitudinal sectional front view showing a state where the whole is sealed in a package body.
FIG. 8 is a vertical sectional front view of the semiconductor device.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Lead frame 1a Chip mount part 1b Lead terminal 2 Main IC chip 2b Electrode pad 2c Protective film 2d Barrier metal 3 Sub IC chip 3a Electrode pad 3b Bump 4 Adhesive film 5 Metal wire 6 Package body

Claims (1)

少なくとも上面に回路素子、この回路素子に対する電極パッドを形成したメインＩＣチップと、少なくとも片面に回路素子とこの回路素子に対する電極パッドとを形成したサブＩＣチップとから成り、前記サブＩＣチップを、前記メインＩＣチップの上面側に、当該サブＩＣチップにおける回路素子及び電極パッドが前記メインＩＣチップにおける回路素子及び電極パッドに対面するように下向きにして配設し、前記メインＩＣチップにおける電極パッド及びサブＩＣチップにおける電極パッドのうち一方の電極パッドにバンプを設け、前記メインＩＣチップにおける電極パッド及びサブＩＣチップにおける電極パッドのうち他方の電極パッドが設けられる側のＩＣチップに、当該ＩＣチップにおける回路素子及び前記他方の電極パッドを覆う保護膜を形成し、この保護膜のうち前記他方の電極パッドを覆う部分に、当該電極パッドの周囲に保護膜の電極パッドに対する重なり部を残して開口部を設け、前記他方の電極パッドのうち前記開口部内の部分に、バリアメタルを、当該バリアメタルの周囲が前記保護膜のうち前記開口部の周囲縁の部分に重なるように形成して、前記バリアメタルにおける上面のうち前記開口部の部分に前記バンプが嵌まる凹所を設け、更に、前記両ＩＣチップの相互間を、その間に介挿した導電粒子混入の接着フィルムにて、前記バンプが当該接着フィルムを前記バリアメタルに対して圧縮変形するようにして接着したことを特徴とする複数のＩＣチップを備えた半導体装置の構造。At least the upper surface to the circuit element, and the main IC chip forming the electrode pads for the circuit element consists of a sub-IC chip forming the electrode pad and the at least one surface to a circuit element for the circuit elements, the sub-IC chip, the On the upper surface side of the main IC chip, the circuit elements and the electrode pads of the sub IC chip are disposed facing downward so as to face the circuit elements and the electrode pads of the main IC chip. A bump is provided on one of the electrode pads on the IC chip, and a circuit on the IC chip on the side where the other electrode pad is provided on the electrode pad on the main IC chip and the electrode pad on the sub IC chip is provided. Cover the element and the other electrode pad. Forming a protective film, forming an opening in a portion of the protective film covering the other electrode pad, leaving an overlapping portion of the protective film with respect to the electrode pad around the electrode pad; A barrier metal is formed in a portion inside the opening so that a periphery of the barrier metal overlaps a peripheral edge portion of the opening in the protective film, and a portion of the upper surface of the barrier metal corresponding to the opening is formed. The bump is compressed by an adhesive film containing conductive particles interposed between the two IC chips. The bump compresses the adhesive film against the barrier metal. A structure of a semiconductor device including a plurality of IC chips, which are bonded so as to be deformed.
JP15991297A 1997-01-24 1997-06-17 Structure of a semiconductor device having a plurality of IC chips Expired - Fee Related JP3543254B2 (en)

Priority Applications (7)

Application Number Priority Date Filing Date Title
JP15991297A JP3543254B2 (en) 1997-06-17 1997-06-17 Structure of a semiconductor device having a plurality of IC chips
EP98900725A EP0890989A4 (en) 1997-01-24 1998-01-22 Semiconductor device and method for manufacturing thereof
KR10-1998-0707403A KR100522223B1 (en) 1997-01-24 1998-01-22 Semiconductor device and method for manufacturing thereof
KR10-2004-7000090A KR100467946B1 (en) 1997-01-24 1998-01-22 Method for manufacturing a semiconductor chip
US09/155,134 US6133637A (en) 1997-01-24 1998-01-22 Semiconductor device having a plurality of semiconductor chips
PCT/JP1998/000281 WO1998033217A1 (en) 1997-01-24 1998-01-22 Semiconductor device and method for manufacturing thereof
US09/612,480 US6458609B1 (en) 1997-01-24 2000-07-07 Semiconductor device and method for manufacturing thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15991297A JP3543254B2 (en) 1997-06-17 1997-06-17 Structure of a semiconductor device having a plurality of IC chips

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US8981574B2 (en) 2012-12-20 2015-03-17 Samsung Electronics Co., Ltd. Semiconductor package

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US4659117A (en) * 1982-08-10 1987-04-21 Iwk Regler Und Kompensatoren Gmbh Flexible coupling for pipes in exhaust systems of motor vehicles
JP2006237280A (en) * 2005-02-25 2006-09-07 Sony Corp Semiconductor device and its manufacturing method
EP3390464B1 (en) * 2015-12-17 2020-10-21 3M Innovative Properties Company Aqueous dispersions of amine-containing fluorinated polymers and methods of making and using the same

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8981574B2 (en) 2012-12-20 2015-03-17 Samsung Electronics Co., Ltd. Semiconductor package
US9633973B2 (en) 2012-12-20 2017-04-25 Samsung Electronics Co., Ltd. Semiconductor package

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