JP3543941B2 - Electrical check method for semiconductor integrated circuit device - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to an electrical check of a semiconductor integrated circuit, and more particularly, to an electrical check in which a wiring to be checked extends between layers of the integrated circuit.
[0002]
[Prior art]
Conventionally, the electrical check of a semiconductor integrated circuit, in particular, the crosstalk noise when a layout is performed using a basic circuit function block such as a gate array or a standard cell is based on parameters extracted from the wiring after layout and the basic circuit function block. This is performed using the characteristic library. For example, in the case of cross-talk check circuit, the amount of crosstalk noise _{V n} is _{V n = {C L / (} C F + C L)} × {1 / (1 + TR n / TR c)}
C _L: line capacitance of the check target wiring C _F: load capacitance of the functional blocks of the check target wiring TR _n: Load delay of the noise source wiring TR _c: Yes load delay check target wiring. Load capacitance C _F of the functional blocks of the check target wiring is included in characteristic library of basic circuit function blocks. Since the capacitance value of the impedance and the wiring of the load delay TR _n and check load delay target wiring TR _c output terminals contained in the characteristic library of similarly functional blocks of the noise source wiring is determined by the resistance value, the crosstalk To perform the check, a capacitance value and a resistance value of the laid out wiring are required in addition to the value of the characteristic library. Therefore, an electrical characteristic check such as a crosstalk check is generally performed for each layout design unit, but ultimately needs to be performed at an LSI chip level. In recent years, as the size of an LSI has increased and the number of integrated functional blocks and wirings has increased, it has become difficult to execute a crosstalk check at one time.
[0003]
[Problems to be solved by the invention]
In order to respond to the request to execute the crosstalk check all at once, for example, labor saving methods such as checking the wiring checked in the lower layout hierarchy not in the upper layer are being studied, but when the wiring to be checked spans between layers However, there is a problem that it is necessary to develop lower data at a higher level so that the whole can be seen, so that a check at a higher level requires a lot of time.
[0004]
An object of the present invention is to provide a simple electrical check method for a semiconductor integrated circuit device even in such wiring extending between layers.
[0005]
[Means for Solving the Problems]
An electrical check method for a semiconductor integrated circuit device according to the present invention provides a crosstalk noise when a wiring to be checked exists in an upper layout and a lower layout in a semiconductor integrated circuit having a layout divided into a plurality of layers. Storing a wiring system parameter extracted for each lower layout unit and a noise amount obtained as a result of the crosstalk check as a library for each layout unit, and connecting to each lower layout unit. Determining the electrical check of the wiring to be checked in the upper layout by adding the wiring parameter stored in the library of each lower layout unit, the noise amount, and the value of the check result based on the layout data present in the upper layout. Have.
[0006]
The library of each layout unit includes a plurality of basic circuit function blocks, includes function blocks laid out in a hierarchy called a macro, which is an integrated circuit serving as an independent layout unit, and outputs the function blocks after the layout. It has the wiring system parameters extracted from the wiring and the amount of crosstalk noise of the crosstalk check performed for each macro.
[0007]
The library further has the load capacity of the function block of the wiring to be checked of the function block.
[0008]
Further, the library has a wiring delay calculated using the wiring parameters extracted from the output wiring of the functional block and the load capacitance and the impedance of the output terminal included in the characteristic library of the basic circuit functional block.
[0009]
The wiring parameters include the capacitance value, the resistance value, or the impedance of the wiring laid out in each layout unit.
[0010]
Further, the amount of crosstalk noise is the amount of crosstalk noise due to the noise source wiring of the wiring to be checked, which is the output wiring of the functional block included in the macro.
[0011]
The layout data for performing the crosstalk check includes the load capacitance of the basic circuit function block of the wiring to be checked included in the characteristic library of the basic circuit function block, and the load of the noise source wiring and the wiring of the wiring to be checked included in the characteristic library. It has a delay and a capacitance value and a resistance value of the laid out wiring.
[0012]
Furthermore, the step of obtaining by adding performs crosstalk the check target wiring, and obtaining the crosstalk noise quantity V _0, obtained as a result of the crosstalk check the layout units lower stored in the library a noise amount V _n, extracting wiring capacitance C _n to the check target wiring and the lower the layout units, the wiring capacitance and checked with the layout of the noise source wiring that exists in the wiring and upper checked a step of obtaining a wiring capacitance _{C 0} by adding the load capacitance connected to the wiring, as all crosstalk noise amount _{V S} to be checked in the wiring _{(V 1 · C 1 + V} 2 · C 2 + ·· + V n _{· C n + V 0 · C} 0) including the step of calculating a _{/ (C 1 + C 2 +} ·· + C n + C 0).
[0013]
Further, in the electrical checking method for a semiconductor integrated circuit device according to the present invention, the wiring to be checked in a semiconductor integrated circuit having a layout divided into a plurality of hierarchies includes an upper layout, a lower layout, and a lower level in the lower layout. In the electrical check method for crosstalk noise when the layout exists across the layouts, the wiring system parameters extracted in the lower layout units and the noise amount obtained as a result of the crosstalk check are stored as a lower library in each layout unit. A lower-level calculation step in which an electrical check of a wiring to be checked of a lower-level layout connected to each lower-level layout unit is performed by adding a check result based on a lower-level library of each lower-level layout unit and layout data existing at a lower level. And each lower layout unit A step of storing the extracted wiring system parameters and the noise amount obtained as a result of the crosstalk check as a lower library of each layout unit, and an electrical check of a wiring to be checked of an upper layout connected to each lower layout unit. An upper-order calculation step is provided in which a lower-order library of each lower-order layout unit and a check result based on layout data existing in the upper order are added to obtain an upper-order calculation step.
[0014]
The present invention relates to a method for checking crosstalk noise in an electrical check when a hierarchical layout is performed using a basic circuit functional block such as a semiconductor integrated circuit device, particularly a gate array or a standard cell, wherein a wiring to be checked is When the layout exists between the upper layout and the lower layout, crosstalk is checked with the wiring parameters extracted in the lower layout and the lower layout so that the lower layout data can be checked even if the lower layout data is not directly visible. The resulting noise amount is compiled into a library in layout units, and the upper-level check combines the lower-level library-related wiring system parameters, the noise amount of the crosstalk check result, and the upper-level layout data check result into Check It is characterized in that.
[0015]
BEST MODE FOR CARRYING OUT THE INVENTION
Next, embodiments of the present invention will be described in detail with reference to the drawings.
[0016]
FIG. 1 is a configuration diagram of a semiconductor integrated circuit device showing a hierarchical layout of basic circuit function blocks for explaining an electrical check method of the semiconductor integrated circuit device of the first embodiment. According to the drawing, in this layout, the LSI 101 includes a macro 201 which is a lower layer and includes a circuit at a functional block level therein, a macro 202, a macro 201 laid out at a higher level, and a FB 303 which is a functional block immediately below the macro 201. , FB 305 are included.
[0017]
The macro 201 includes functional blocks FB301 and FB302, and the macro 202 includes functional blocks FB304 and FB306. The wiring NET1 is a wiring to be checked for crosstalk across the layers, is driven by the FB 301, and has the FBs 305 and 306 as loads.
[0018]
NET2, NET3, and NET4 are wirings that may give noise to NET1, respectively, and are driven by FB302, FB303, and FB304, respectively.
[0019]
The wiring capacitance between the wiring capacitance between NET1 and NET2 the wiring capacitance between the _C 1, NET1 and NET3 _C 3, NET1 and NET4 and _{C 4.} In this circuit configuration, the library storing the wiring system parameters extracted as each lower layout unit and the noise amount obtained as a result of the crosstalk check in each layout unit includes the crosstalk noise amount of each lower layout unit. Includes internal wiring capacitance.
[0020]
That is, inside the wiring capacitance _{C 1} of the crosstalk noise quantity _{V 1} and the macro 201 when checked NET1 macro 201 levels in a library of macro 201 are included. The total capacity _{C 2} of the load capacitance _{C 6} inside the wiring capacitance _{C 4} of the crosstalk noise amount _{V 2} and macros 202 when during library macro 202 checked NET1 macro 202 level FB306 is (not shown) include.
[0021]
Next, the operation of the electrical check method of the semiconductor integrated circuit device according to the present invention will be described with reference to FIG. FIG. 2 is a flowchart of the electrical check method according to the first embodiment of the present invention.
[0022]
According to the figure, in the macro including the functional blocks laid out in the lower hierarchy, the wiring capacity between the output wiring and the noise source wiring, which is the wiring to be checked after layout, and the wiring such as the load capacitance connected to the wiring to be checked Storing the system parameters and the amount of crosstalk noise due to the noise source wiring of the wiring to be checked of the macro as a library for each layout (S101);
The layout data at the time of performing the crosstalk check includes the load capacitance of the basic circuit function block of the wiring to be checked included in the characteristic library of the basic circuit function block, the load delay of the noise source wiring and the wiring to be checked included in the characteristic library. , Having a capacitance value and a resistance value of the laid out wiring, and performing an electrical check of a wiring to be checked of an upper layout connected to each lower layout unit and a library of each lower layout unit and an upper layout There is a step (S102) of adding and obtaining a check result based on data.
[0023]
Furthermore, as shown in FIG. 3, determining by its addition is subordinate macro as black box performs crosstalk the check target wiring in LSI level, obtaining the crosstalk noise quantity V ₀ which checked wiring a step (S201), and the noise amount V _n obtained as a result of the crosstalk check the layout units subordinate stored in the library, the wiring capacitance C _n to the check target wiring and the lower the layout unit extraction and step (S202), and the lower step to determine completion of the extraction of the noise amount V _n and the wiring capacitance C _n of each layout unit (S203), checked wiring and noise source wiring layout in the higher calculated as the wiring capacitance C ₀ by adding the wiring capacity and the check load capacitance connected to the wiring of the target and Step (S204) _{and, (V 1 · C 1 +} V 2 · C 2 + ·· + V n · C n + V 0 · C 0) as the total crosstalk noise amount _{V S} of the wiring to be checked _{/ (C} 1 + _{C 2 + ·· + C n + C 0} ) to calculate the step and (S205), a step (S206) for outputting the total crosstalk noise quantity _{V S.}
[0024]
As shown in FIG. 1, a crosstalk check of NET1 is performed using the macro 201, the macro 202, the lower layer macro 201 at the level of the LSI 101 including the FB 303 and the FB 305 that are the function blocks immediately below, and the macro 202 as a black box. obtaining the amount of noise _{V 0} which performs LSI101 level. From the noise amount _V 1, _{V 2} and the wiring capacitance contained in LSI101 level of the noise amount _{V 0} and macros 201 and 202, the total crosstalk noise amount _{V S} of NET1 is _{V S = (V 1 · C} 1 + V 2 · C ₂ + V ₀ · C ₀ ) / (C ₁ + C ₂ + C ₀ )
Is calculated. C ₀ (not shown) is the sum of the wiring capacitance C ₃ of NET ₁ and NET ₃ and the load capacitance C ₅ of FB 305 at the LSI 101 level.
[0025]
As shown in FIG. 4, the operation flow of the electrical check method of the present invention is the same as the step (S301) of extracting wiring system parameters for each wiring existing in the macro in each lower macro unit. A step (S02) of calculating a noise amount using wiring system parameters and a library of basic circuit function blocks for each wiring existing in the macro in each lower macro unit, and a wiring extracted in each macro unit A step of creating a library including system parameters, a library value of a basic circuit function block, and a noise amount (S303); and a step of extracting wiring system parameters for each wiring for each higher-level LSI (S304). , Calculates the amount of noise using the library of wiring parameters and basic circuit function blocks, and the library for each macro That the step (S305), and a step (S306) for calculating a total noise amount using the noise amount contained in the library of calculated amount of noise and macro-unit in LSI.
[0026]
Next, a second embodiment of the present invention will be described with reference to FIG. FIG. 5 is a configuration diagram of a semiconductor integrated circuit device showing a hierarchical layout of basic circuit function blocks for explaining an electrical check method according to a second embodiment of the present invention.
[0027]
The difference between the second embodiment of the present invention and the first embodiment is that the macro 401 is mounted on the lower layer of the macro 201 and the macro 402 is mounted on the lower layer of the macro 202 as shown in FIG. It is that you are.
[0028]
That is, in the electrical check method according to the second embodiment of the present invention, the wiring NET1 to be checked in the LSI 101 having a layout divided into three layers has the upper layout (101) and the lower layout (201, 202). This is an electrical check method of crosstalk noise when lower layouts (401, 402) are present in lower layouts, wherein a wiring system parameter extracted in units of lower layouts and a crosstalk check are checked. Storing the resulting noise amount as a low-level library of each layout unit; and performing an electrical check of a wiring to be checked of a lower-level layout connected to each lower-level layout unit with a lower-level library of each lower-level layout unit and a lower-level library. Check result based on layout data existing in A lower-order calculation step, a step of storing wiring system parameters extracted in each lower-order layout unit and a noise amount obtained as a result of the crosstalk check as a lower-order library of each layout unit, and a connection to each lower-order layout unit. An upper-level calculation step is performed in which an electrical check of a wiring to be checked in a higher-level layout is performed by adding a lower library of each lower-level layout unit and a check result based on layout data existing in a higher level.
[0029]
The connection configuration of the basic circuit functional blocks of the macro shown in FIGS. 1 and 5 is an example, and is not particularly limited. For example, the macro 401 and the macro 402 may be interchanged, or another connection configuration may be used, and there is no limitation.
[0030]
【The invention's effect】
In the electrical characteristic checking method of the present invention, since the upper-level check is performed using the result of the lower-level layout check, the layout data is not expanded at the time of the upper-level check, so that an enormous amount of data need not be handled. There is.
[Brief description of the drawings]
FIG. 1 is a configuration diagram of a semiconductor integrated circuit device showing a hierarchical layout of basic circuit function blocks for explaining an electrical check method according to a first embodiment of the present invention.
FIG. 2 is a basic flowchart of the electrical check method of the present invention.
FIG. 3 is a flowchart of an electrical check method according to the first embodiment of the present invention.
FIG. 4 is a flowchart of an electrical check method according to a general embodiment of the present invention.
FIG. 5 is a configuration diagram of a semiconductor integrated circuit device showing a hierarchical layout of basic circuit function blocks for explaining an electrical check method according to a second embodiment of the present invention.
[Explanation of symbols]
101 LSI
201, 202, 401, 402 Macro 301 to 306 Basic circuit function block (FB)
501, 502, 504, 506 Basic circuit function block (FB)

Claims (10)

An electrical check method of crosstalk noise when a wiring to be checked exists in an upper layout and a lower layout in a semiconductor integrated circuit having a layout divided into a plurality of hierarchies, wherein each lower layout unit Storing the wiring system parameters extracted in step (1) and the crosstalk noise amount obtained as a result of the crosstalk check as a library for each layout unit; and Electrical check of the semiconductor integrated circuit device, which comprises the step of adding a wiring system parameter, a crosstalk noise amount stored in the library of each lower layout unit, and a value of a check result based on layout data present at a higher level. Method for checking. The library includes a plurality of basic circuit function blocks, includes function blocks laid out in a hierarchy called a macro, which is an integrated circuit serving as an independent layout unit, and is extracted from output wiring of the function blocks after the layout. 2. The electrical check method for a semiconductor integrated circuit device according to claim 1, further comprising a wiring system parameter and a crosstalk noise amount of a crosstalk check performed for each macro. 3. The method according to claim 1, wherein the library further has a load capacity of a function block of a wiring to be checked of the function block. 2. The library according to claim 1, wherein the library has a wiring delay calculated using a wiring system parameter extracted from an output wiring of the functional block and a load capacitance and an impedance of an output terminal included in a characteristic library of the basic circuit functional block. 4. An electrical check method for a semiconductor integrated circuit device according to any one of claims 1 to 3. 5. The method according to claim 1, wherein the wiring parameters include a capacitance value and a resistance value of the wiring laid out in each of the layout units. 6. The method according to claim 1, wherein the wiring system parameter further includes an impedance of a wiring laid out in each of the layout units. 5. The semiconductor integrated circuit device according to claim 1, wherein the crosstalk noise amount is a crosstalk noise amount due to a noise source wiring of a wiring to be checked, which is an output wiring of a functional block included in the macro. Check method. The layout data at the time of performing the crosstalk check includes the load capacitance of the basic circuit function block of the wiring to be checked included in the characteristic library of the basic circuit function block, and the load delay of the noise source wiring and the wiring to be checked included in the characteristic library. 2. The method according to claim 1, wherein the data is layout data having a capacitance value and a resistance value of the laid out wiring. Determining by said addition is carried out crosstalk checking of the checked lines, determining a crosstalk noise quantity V _0, the results obtained crosstalk check the layout units lower stored in the library and a crosstalk noise amount V _n, extracting wiring capacitance C _n of the check target wiring and the lower of each layout units, wiring capacitance between the noise source wiring layout existing in the check target wiring and the upper and a step of obtaining a wiring capacitance C ₀ of the sum of the load capacitance connected to the check target wiring, as all crosstalk noise amount V _S of the check target wiring _{(V 1 · C 1 + V} 2 · C 2 + · _{· + V n · C n +} V 0 · C 0) / ( no _{C 1 + C 2 + ·· +} C n + C 0) according to claim 1 to 8 comprising the step of calculating An electrical check method for a semiconductor integrated circuit device according to any one of the preceding claims. Electrical check of crosstalk noise when a wiring to be checked exists in a semiconductor integrated circuit having a layout divided into a plurality of hierarchies in an upper layout, a lower layout, and a lower layout in the lower layout. In the method, a wiring system parameter extracted in a lower layout unit and a crosstalk noise amount obtained as a result of a crosstalk check are stored as a lower library of each layout unit, and a lower level connected to each of the lower layout units. A lower-level calculation step of adding an electrical check of the wiring to be checked for the layout by adding the check result based on the lower-level library of each lower-level layout unit and the layout data existing at the lower level; and a wiring system extracted for each lower-level layout unit. Parameters and cross toe Storing crosstalk noise amount obtained as a result of the check as a low-level library of each layout unit step and, each layout of electrical checking the subordinate checked wiring layout of the upper to be connected to the lower of each layout units An electrical check method for a semiconductor integrated circuit device, comprising an upper calculation step of adding and checking a check result based on a lower library of a unit and layout data existing in a higher order.

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