JP3544499B2 - Semiconductor integrated circuit device - Google Patents

Description

[0001]
[Industrial applications]
The present invention relates to a semiconductor integrated circuit device including an insulated gate field effect transistor element, and more particularly to a structure for preventing electrostatic breakdown thereof.
[0002]
[Prior art]
First, the general structure of the semiconductor integrated circuit device will be briefly described with reference to FIG. The semiconductor integrated circuit device 0 includes a connection portion 2 for connecting to an external circuit (not shown) and an internal circuit 1 for performing predetermined logic processing and the like. In each part, an insulated gate field effect (hereinafter referred to as MOS) transistor is integrated as a basic component. Here, in order to facilitate understanding of the present invention, the MOS transistor belonging to the connection portion 2 is particularly called a peripheral transistor, and the MOS transistor belonging to the internal circuit 1 is called an internal transistor.
[0003]
The connection unit 2 includes an input terminal 3, an output terminal 4, a power supply terminal 5, a ground terminal 6, and the like. Generally, an input protection circuit 7 is inserted between the input terminal 3 and the internal circuit 1. The output terminals 4 are roughly classified into two types. A CMOS output terminal using an inverter 8 composed of a pair of complementary MOS transistors or CMOS transistors, and an open drain output terminal using an N-channel MOS transistor 9 that is connected to an open drain. The above-described CMOS transistors and N-channel MOS transistors are examples of peripheral transistors. The power terminal 5 is connected to the power line VDD, and the ground terminal 6 is connected to the ground line GND.
[0004]
Next, a general structure of a MOS transistor will be briefly described with reference to FIG. The illustrated example is an N-channel MOS transistor having an N + single drain structure (hereinafter, this structure is referred to as a CONV structure). A gate electrode G is formed on a semiconductor substrate SUB made of silicon or the like via a gate insulating film OX made of silicon dioxide or the like. The substrate SUB is P-type, and the gate insulating film OX has a thickness of, for example, 100 to 800 °. On both sides of the gate electrode G, a source S and a drain D composed of an N + type impurity diffusion region are formed. A channel region ch that is controlled to be conductive by the gate electrode G is defined between the two diffusion regions.
[0005]
In order to increase the integration density of semiconductor integrated circuit devices, transistor elements tend to be increasingly miniaturized in recent years. That is, the length of the channel region ch (hereinafter referred to as channel length) is becoming shorter and shorter. However, when the channel length is reduced in the transistor having the CONV structure, the characteristic deterioration due to hot electrons frequently occurs.
[0006]
Referring to FIG. 24, a MOS transistor having a recently developed double drain structure (hereinafter referred to as an LDD structure) will be briefly described. This LDD structure has been developed in order to prevent deterioration of durability due to hot electrons, which has become conspicuous with miniaturization of elements. As shown in the drawing, the LDD structure has a drain D in which an N- type impurity diffusion region and an N + type impurity diffusion region are continuous. The source S has a similar structure. Note that when the channel length is shortened according to the so-called scaling rule, the thickness of the gate insulating film OX is similarly reduced. For example, while the thickness of the gate insulating film in the CONV structure is 300 to 400 °, the thickness of the gate insulating film in the miniaturized LDD structure is as thin as about 100 to 300 °. On the other hand, in the CONV structure, the drain withstand voltage or breakdown voltage is, for example, 10 V, whereas when the LDD structure is employed, the drain withstand voltage increases to, for example, about 20 V.
[0007]
[Problems to be solved by the invention]
With reference to FIG. 25, the problem of the related art to be solved by the present invention will be briefly described. FIG. 25 is a graph showing the relationship between the transistor breakdown voltage and the channel length (hereinafter, sometimes referred to as L length). As shown, the gate breakdown voltage of the miniaturized LDD structure is lower than the gate breakdown voltage or gate breakdown voltage of the CONV structure. This is because the gate insulating film is inevitably thinner due to the scaling rule. On the other hand, the drain withstand voltage or DC withstand voltage of the LDD structure is greatly increased as compared with the drain withstand voltage of the CONV structure. In addition, in the CONV structure, when the L length is less than 3 μm, a punch-through region frequently occurs and the IC falls below the rated voltage, whereas in the LDD structure, the punch-through region appears until the L length becomes about 1 μm. Absent.
[0008]
As is clear from the graph of FIG. 25, when the LDD structure is adopted by miniaturizing the element, the drain withstand voltage may exceed the gate withstand voltage and a reversal phenomenon may occur in some cases. Due to this reversal, there arises a problem that the resistance to electrostatic breakdown (hereinafter referred to as ESD resistance) of the MOS transistor is reduced. That is, when an electrostatic stress is applied to the drain electrode and a surge current flows, the drain withstand voltage is increased, so that the stress directly affects the gate insulating film and the probability of causing dielectric breakdown increases.
[0009]
Returning to FIG. 22, the problem of the conventional technique will be described in more detail. Conventionally, the internal transistor forming the internal circuit 1 and the peripheral transistor forming the connecting portion 2 have basically the same structure in a semiconductor manufacturing process. With miniaturization, the focus has been on improvement of hot electron durability degradation, and no practical countermeasures have been taken for ESD resistance. For internal transistors, it is important to prevent the deterioration of durability due to hot electrons or hot carriers and to ensure the reliability during operation. In addition, since the internal transistors are not directly exposed to external electrostatic stress, the reduction of the ESD resistance can be reduced. It doesn't matter much.
[0010]
On the other hand, since the peripheral transistors are directly affected by external static stress, there is a problem that a decrease in the ESD withstand voltage causes electrostatic breakdown of the transistors and causes many failures. For example, the N-channel MOS transistor 9 connected to the open-drain type output terminal 4 has a particularly poor ESD tolerance as compared with the case where the inverter 8 made of CMOS is used, causing a serious problem.
[0011]
[Means for Solving the Problems]
SUMMARY OF THE INVENTION In view of the above-described problems of the related art, an object of the present invention is to improve the ESD resistance of a peripheral transistor such as an N-channel MOS transistor connected to an open drain output terminal. The measures taken to achieve this objective are as follows. That is, basically, the peripheral transistor has a channel structure in which the electrostatic stress current is easily released as compared with the internal transistor. Here, the channel structure means a MOS structure including not only the channel itself but also the periphery thereof.
[0012]
Hereinafter, specific measures taken with reference to FIG. 1 will be listed. FIG. 1 is a schematic diagram showing the structure of an N-channel MOS transistor 9 connected to an open drain output terminal. The drain D is in an open state, and the electrostatic stress current ES may be accidentally applied from the outside. On the other hand, the source S is grounded, and the semiconductor substrate SUB is also grounded. The gate electrode G is supplied with a gate voltage from an internal circuit.
[0013]
As a first specific means, the channel length L of the peripheral transistor 9 is set shorter than the minimum channel length of the internal transistors within a range that satisfies the rated withstand voltage, so that the channel structure is easy to escape the electrostatic stress current ES. ing. The channel length L of the peripheral transistor 9 may be the same as the minimum channel length of the internal transistors. However, the limit to shorten the channel length is determined by the durability of hot electrons.
[0014]
In such a case, the peripheral transistor should be set to have a longer channel length than the lower limit channel length below the rated withstand voltage due to a drop in withstand voltage due to abrupt punch-through. That is, it is not practical to shorten the channel length without limit. Preferably, the L length of the peripheral transistor 9 may be partially shortened along the channel width direction. That is, the peripheral transistor 9 may have a channel structure having a first channel width portion set to a normal channel length and a second channel width portion set to a locally shortened channel length.
[0015]
As a second specific means, the structure is such that the substrate SUB contacts the ground line GND of the peripheral transistor 9 via the additional resistor R. Further, instead of or in addition to this, a structure in which a substrate contact for grounding is provided at a position away from the drain region D of the peripheral transistor 9 may be employed.
As a third specific means, the peripheral transistor 9 has a so-called asymmetric structure in which the distance between the source contact and the gate electrode G is set smaller than the distance between the drain contact and the gate electrode G. I made it. Further, it is preferable to use an epitaxial wafer as the semiconductor substrate SUB.
[0016]
As a fourth specific means, the internal transistor (not shown) has an LDD structure, while the peripheral transistor 9 has a CONV structure. Concomitantly or independently of this, the peripheral transistor 9 may have a structure in which the gate insulating film OX having a small thickness is at least partially provided along the end of the drain region D. Further, the peripheral transistor 9 may be provided with a surface impurity region having a higher concentration than the substrate region SUB at least partially along the end of the drain region D. Further, the peripheral transistor 9 may be connected to a metal gate line via a gate contact formed immediately above the gate electrode G.
[0017]
As a fifth specific means, the peripheral transistor 9 has an impurity diffusion self-alignment type DSA structure.
[0018]
[Action]
Subsequently, the operation of the present invention will be described in detail with reference to FIG. The middle part of FIG. 1 shows the connection of the open drain N-channel MOS transistor 9. The drain D is in an open state, while the source S is connected to the ground line GND via various resistance components R. The substrate SUB is also connected to the ground line GND via various resistance components R. As is clear from the figure, the N-type drain D, the P-type substrate SUB, and the N-type source S have an NPN junction, and can be regarded as an NPN bipolar transistor equivalently.
[0019]
The lower part of FIG. 1 shows the connection of an equivalent bipolar transistor. The collector C of the NPN bipolar transistor corresponds to the drain of the MOS transistor 9, the base B also corresponds to the substrate SUB, and the emitter E also corresponds to the source S. A diode Di is connected between the collector and the base. This diode is formed by the PN junction between the drain D and the substrate SUB. The collector C is in an open state, the base B is grounded via a base resistor RB, and the emitter E is also grounded via an emitter resistor RE. This is a so-called grounded emitter structure. Note that the base resistance RB and the emitter resistance RE respectively correspond to the resistance components R shown in the middle part of FIG.
[0020]
When a pulsed electrostatic stress current ES or surge current is applied to the collector terminal in the open state, the base current IBON flows to the base B of the transistor exceeding the breakdown voltage of the diode Di, and the bipolar transistor is turned on. Therefore, the collector current ICON flows directly between the collector C and the emitter E. Thus, the electrostatic stress current ES is guided to the ground line GND, and the electrostatic breakdown of the gate insulating film OX can be prevented. This collector current ICON flows as a punch-through current or a surface breakdown current. The more easily the electrostatic stress current ES is released, the greater the ESD resistance of the peripheral transistor.
[0021]
As is clear from the figure, the conductance between the emitter E and the collector C may be reduced first in order to easily release the electrostatic stress current ES. This is equivalent to increasing the hFE (current amplification factor) of the common-emitter bipolar transistor when viewed equivalently. For this purpose, the first specific measures described above have been taken. For example, by setting the channel length L of the peripheral transistor 9 shorter than the channel length of the internal transistor, the conductance is improved and a large amount of collector current ICON flows. For a similar purpose, a fifth measure was taken. That is, when the peripheral transistor 9 has the DSA structure, the channel length L can be significantly reduced.
[0022]
Second, by increasing the base resistance RB, the base current IBON easily flows, and the bipolar transistor easily exceeds the withstand voltage of the diode Di and quickly becomes conductive. The sooner the conductive state is established, the better the ESD resistance. To this end, the second specific measures described above have been taken. For example, the base resistance RB can be equivalently increased by connecting the substrate contact of the peripheral transistor 9 to the ground line GND via the additional resistance R.
[0023]
Third, by making the emitter resistance RE as small as possible, the collector current ICON flows more easily. To this end, the third measure described above has been taken. For example, by employing an asymmetric structure in which the distance between the source contact and the gate electrode is set smaller than the distance between the drain contact and the gate electrode, the emitter resistance RE can be reduced equivalently.
[0024]
Fourth, if the breakdown voltage of the diode Di is reduced, the bipolar transistor is easily turned on, and the ESD resistance is improved. For this purpose, the fourth specific means described above has been taken. For example, when only the peripheral transistor has the CONV structure, the breakdown voltage of the drain is reduced, and the withstand voltage of the diode Di can be equivalently reduced.
[0025]
As described above, the present invention pays attention to the fact that MOS peripheral transistors can equivalently perform a bipolar operation with respect to an electrostatic stress current to remove stress. The above-described channel structure is employed to cause a bipolar operation or a bipolar action at high speed and efficiently, and it is possible to greatly improve the ESD resistance of the MOS peripheral transistor.
[0026]
【Example】
Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the drawings.
FIG. 2 is a schematic plan view showing a first embodiment of the peripheral transistor 9 according to the present invention. In this example, the channel length L of the peripheral transistor 9 is set to be equal to or shorter than the minimum channel length of the internal transistors within a range satisfying the rated withstand voltage. The internal transistors have various channel lengths depending on a given function and required operation characteristics. Therefore, in order to increase the ESD resistance of the peripheral transistor 9 as compared with the internal transistor, the channel length L of the peripheral transistor 9 needs to be shorter than the minimum channel length of the internal transistor. However, the channel length L must be in a range that can maintain the IC rated withstand voltage. If the channel length L is extremely shortened, the DC breakdown voltage or the drain breakdown voltage falls below the rating.
[0027]
The peripheral transistor 9 is, for example, an N-channel MOS transistor used for an open drain output terminal. By reducing the channel length L, the conductance when the N-channel MOS transistor is regarded as an NPN transistor is improved, and the ability to release electrostatic stress is improved. On the other hand, a resistance is added to the open drain terminal in order to compensate for the disadvantage that the peripheral transistor has a low ESD resistance. Therefore, the drivability of the open drain transistor decreases. To compensate for this, it was necessary to increase the channel width. On the other hand, in this embodiment, since the ESD resistance is improved, it is not necessary to increase the channel width W without any additional resistance. As a result, both the channel length L and the channel width W can be reduced, which can contribute to miniaturization of peripheral transistors.
[0028]
FIG. 3 is a graph showing the relationship between the L length of the MOS transistor and the breakdown voltage. This shows the case of the LDD structure, in which the drain withstand voltage is high. In a region B having a relatively large L length, for example, a region of 3 μ or more, the transistor breakdown voltage TrBV exceeds the gate breakdown voltage. The L length of the conventional peripheral transistor is set in this region as in the case of the internal transistor. On the other hand, in a region having a small L length, for example, about 2 μm or less, the transistor breakdown voltage is reduced and the region becomes a punch-through region. In the present invention, the L length of the peripheral transistor is set in a range A which is higher than the rating and preferably lower than the gate breakdown voltage. For example, in the case of an IC with a power supply voltage rating of 5 V, the range is 0.4 to 1.2 μm, and in the case of a 3 V IC, the range is about 0.2 to 1.2 μm.
[0029]
As described above, even if the peripheral transistor has the LDD structure like the internal transistor, the ESD resistance can be improved by simply reducing the L length. Therefore, in the embodiment of FIG. 2, since the peripheral transistor and the internal transistor can be formed by the same semiconductor process, there is no need to add any steps.
FIG. 4 is a schematic plan view showing a second embodiment of the peripheral transistor according to the present invention. Peripheral transistor 9 has a first channel width portion 11 set to a normal channel length L1, and a second channel width portion 12 set to a locally shortened channel length L2. Unlike the first embodiment shown in FIG. 2, in this embodiment, the L length is partially shortened. Even when the voltage is high, the amount of the electrostatic stress current is small, so that the stress can be sufficiently released even if the second channel width portion 12 is narrow. On the other hand, in a normal operation, the probability that punch-through occurs in the second channel width section 12 is higher than in the first channel width section 11. However, since the size of the second channel width portion 12 is small, there is an advantage that a leak current can be reduced even when punch-through occurs.
[0030]
FIG. 5 is a graph showing the relationship between the ESD resistance of the peripheral transistor and the L length. As is clear from the figure, the shorter the L length, the higher the ESD resistance. However, if the length is shorter than the predetermined lower limit channel length LL, there is a danger that the ESD tolerance is reduced again. For this reason, the L length of the peripheral transistor should be set longer than the lower limit channel length LL. For example, in an IC with a power supply voltage rating of 5 V, the lower limit channel length is 0.4 μm, and in a 3 V IC, it is about 0.2 μm.
[0031]
FIG. 6 is a schematic plan view showing a third embodiment of the peripheral transistor 9 according to the present invention, in which an N-channel MOS transistor is connected to an open drain output terminal. A substrate contact 13 for grounding is provided at a position away from the drain region D of the peripheral transistor 9. For example, the substrate contact 13 is on the source region S side of the peripheral transistor 9, and the distance b between the substrate contact 13 and the drain region D is larger than the distance between the substrate contact 13 and the source region S. I have.
[0032]
In addition, the substrate contact 13 is connected to the ground line GND via the additional resistor 14. The additional resistor 14 can be formed by patterning a polysilicon film or the like, for example.
FIG. 7 is a diagram showing a schematic sectional structure of the third embodiment shown in FIG. Since the distance between the substrate contact 13 and the drain region D is large, a large resistance component R1 is applied between the two via the substrate SUB. Further, since the additional resistor 14 is interposed between the substrate contact 13 and the ground line GND, a resistance component R2 is similarly added. As a result, large resistance components R1 and R2 are added in series between the drain region D and the ground line GND.
[0033]
FIG. 8 is an equivalent circuit diagram when the MOS transistor shown in FIG. 7 is regarded as an NPN bipolar transistor. As shown in the figure, a base resistor RB composed of a series connection of resistance components R1 and R2 is added between the open collector and the base-side ground line GND via a diode Di. Increasing the base resistance RB makes it easier for the NPN bipolar transistor to turn on, thereby improving the ESD resistance. In other words, the bipolar transistor becomes conductive with a small base current IBON.
[0034]
FIG. 9 is a schematic plan view showing a fourth embodiment of the peripheral transistor 9 according to the present invention. In this example, the distance c between the source contact 15 and the gate electrode G is set to be smaller than the distance d between the drain contact 16 and the gate electrode G, and the peripheral transistor 9 has an asymmetric structure. . Incidentally, if the drain contact 16 is brought close to the gate electrode G together with the source contact 15, it is not preferable because the ESD resistance is deteriorated.
[0035]
FIG. 10 shows a schematic sectional structure of the embodiment shown in FIG. As shown in the drawing, since the distance between the gate electrode G and the source contact 15 is reduced, the effective current path passing through the source region S is shortened, and the resistance component R can be reduced.
FIG. 11 is an equivalent circuit diagram when the open drain type N-channel MOS transistor shown in FIG. 10 is regarded as an NPN bipolar transistor. As shown, an emitter resistor RE including a resistance component R shown in FIG. 10 is interposed between the emitter E and the ground. Since the emitter resistance RE is set as small as possible, the conductance of the NPN transistor is improved, the collector current ICON flows more easily, and the ESD resistance can be improved.
[0036]
FIG. 12 is a partial sectional view showing a fifth embodiment of the semiconductor integrated circuit device according to the present invention. In this example, the substrate SUB uses an epitaxial wafer. On this wafer, peripheral transistors 9 such as N-channel MOS transistors are formed. The epitaxial wafer has a high impurity concentration of, for example, P + and has excellent conductivity. An N-channel MOS transistor is provided on this wafer. In this case, the electrostatic stress current ES applied to the open drain D flows to the source S side via the substrate SUB which is partially excellent in conductivity. When equivalently viewed as an NPN bipolar transistor, the conductance between the emitter and the collector is improved, so that the ESD resistance of the peripheral transistor 9 is improved.
[0037]
FIG. 13 is a schematic plan view showing a sixth embodiment of the peripheral transistor 9 according to the present invention. The present embodiment is characterized in that the internal transistor (not shown) has a double-drain LDD structure, while the illustrated peripheral transistor 9 has at least partially a single-drain normal structure or a CONV structure. As shown, the first channel width portion 17 has an LDD structure, whereas only the second channel width portion 18 has a CONV structure selectively. Of course, the peripheral transistor 9 may have a complete CONV structure, but at that time, there is a concern that durability may be degraded due to hot electrons. If the portion of the CONV structure is localized as in this example, there is an advantage that deterioration due to hot electrons is not likely to spread to the entire channel width portion. Since the amount of electrostatic stress current is relatively small, it is possible to sufficiently cope with a narrow portion of the CONV structure.
[0038]
FIG. 14 shows a cross-sectional structure of the embodiment shown in FIG. 13. The left side shows a part of the CONV structure cut along the XX line, and the right side shows a part of the LDD structure cut along the YY line. Show. The CONV structure has a structure in which the P-type region of the substrate and the N + -type region of the drain D are in contact with each other, and the breakdown voltage of the PN + junction diode Di is relatively low. On the other hand, in the LDD structure, the P-type region of the substrate is in contact with the N-type region of the drain D, and the breakdown voltage of the PN-junction diode is relatively high.
[0039]
FIG. 15 is a graph showing the operating characteristics of the diode Di when the electrostatic stress is released. The PN junction diode Di in the CONV structure is turned on at a relatively low voltage and can quickly supply an on-current. On the other hand, the PN junction diode in the LDD structure does not turn on until a relatively high voltage is reached. Therefore, the responsiveness for releasing the electrostatic stress is poor.
[0040]
FIG. 16 is a graph showing the relationship between the gate L length of the transistor, that is, the channel length, and the ESD immunity of the peripheral transistor having the CONV structure along the entire channel width and the peripheral transistor having the same LDD structure. Based on. As is clear from the graph, regardless of the channel length, it can be understood that the MOS transistor having the CONV structure has a higher ESD resistance than the MOS transistor having the LDD structure.
[0041]
FIG. 17 is a schematic sectional view showing a seventh embodiment of the peripheral transistor according to the present invention. The peripheral transistor 9 is characterized in that it has a gate insulating film OX having a small thickness at least partially along the end of the drain region D. As described above, when the gate insulating film OX is thinned, the breakdown voltage of the PN junction diode Di located immediately below is reduced, and the bipolar transistor is easily turned on equivalently. In other words, since the surface breakdown current easily flows through the channel ch, the ESD resistance is improved. The gate insulating film OX may be thinned over the entire channel width portion. However, in order to prevent punch-through in normal operation, it is necessary to partially thin the gate insulating film as in this example. preferable. This embodiment is particularly effective for a semiconductor integrated circuit device or an IC driven with a power supply voltage of 3 V (the so-called 3 V system has a reference power supply voltage of 3.5 V) or less than the conventional standard power supply voltage of 5 V.
[0042]
FIG. 18 is a schematic partial sectional view showing an eighth embodiment of the peripheral transistor according to the present invention. The peripheral transistor 9 is characterized in that it has a surface impurity region 19 having a higher concentration than the substrate region SUB at least partially along the end of the drain region D. For example, when the peripheral transistor 9 is an N-channel type, the drain region D is an N-type impurity region. The substrate region SUB has a P-type impurity region. A P ± type surface impurity region 19 is diffused between the two regions. In this way, the withstand voltage of the PN junction diode Di decreases, and the ESD resistance of the transistor 9 can be improved. In other words, since surface breakdown easily occurs along the channel ch, the NPN bipolar transistor is easily turned on equivalently. It is preferable that the high-concentration surface impurity region 19 is partially formed along the channel width portion, as in the seventh embodiment. This embodiment is particularly effective for a low-voltage driven 3VIC. It is preferable that the concentration of surface impurity region 19 be set slightly higher than the impurity concentration of substrate region SUB.
[0043]
FIG. 19 is a schematic plan view showing a ninth embodiment of the peripheral transistor according to the present invention. The peripheral transistor 9 is connected to a metal gate line 21 via a gate contact 20 formed directly above the gate electrode G. By doing so, the resistance component interposed between the gate electrode G and the metal gate line 21 made of aluminum or the like can be reduced as compared with the related art.
[0044]
FIG. 20 shows a schematic sectional structure of the ninth embodiment shown in FIG. The gate contact 20 provided directly above the gate electrode G is directly connected to the metal gate line 21 overlaid thereon. As a result, the value of the resistance component R interposed between the two can be reduced as compared with the related art. By lowering the resistance component R, the potential of the gate electrode G can be made closer to the ground level. For this reason, there is an advantage that surface breakdown in the channel ch is likely to occur.
[0045]
Finally, FIG. 21 is a schematic sectional view showing a tenth embodiment of the peripheral transistor according to the present invention. The present embodiment is characterized in that the N-channel MOS transistor 9 has a DSA structure of an impurity diffusion self-alignment type. As shown in the figure, the DSA structure sequentially performs self-aligned N-type and P-type impurity diffusion on a P-type substrate SUB, and forms an N-type drain region D and an N-type source region S between the two. To form a P-type channel region ch interposed therebetween. As apparent from the figure, in the DSA structure, the channel length is extremely short because the channel ch is formed in the thickness direction of the impurity diffusion layer. Therefore, it is possible to equivalently increase the conductance of the NPN bipolar transistor.
[0046]
Although the first to tenth embodiments of the peripheral transistor according to the present invention have been described as examples used for the open drain terminal, other application examples will be described below. FIG. 26A shows a first application example in which the gate of the N-channel MOS transistor 9 according to the present invention is connected to the source (hereinafter referred to as off-connection) and added separately from the N-channel MOS output transistor 22 itself. FIG. 2 is a schematic block diagram showing a circuit. Although many embodiments have been described in which the ESD tolerance of the peripheral transistor itself such as an output is improved, this application is effective, for example, when the current IDS at the time of turning on the output transistor cannot be increased so much. This is because the conductance gm of the MOS transistor automatically increases when the channel length is shortened as in the first embodiment.
[0047]
As in the second embodiment, even if the channel portion is shortened, an increase in gm when the channel portion is turned on cannot be avoided. However, in this application example, the N-channel MOS transistor 9 having a short channel length is always off. Can be completely avoided. Since the N-channel MOS transistor 9 allows the electrostatic stress to escape, the ESD resistance of the circuit including the output transistor can be improved. Leakage current due to the short channel length of the off-connection N-channel MOS transistor 9 does not pose a problem because the channel width is sufficient even if the channel width is small as described in the second embodiment. In this application example, any of the transistors from the first to tenth embodiments may be used. Hereinafter, adding the N-channel MOS transistor 9 according to the present invention in the off connection as in the present application example is referred to as adding as a protection element.
[0048]
FIG. 26B is a schematic block diagram showing a circuit of a second application example in which the N-channel MOS transistor 9 according to the present invention is added as a protection element to a CMOS output terminal. The effect is the same as that of the first application example.
FIG. 26C is a schematic block diagram showing a circuit of a third application example in which the N-channel MOS transistor 9 according to the present invention is added to the input / output terminal as a protection element. The effect is the same as that of the first application example, but a further advantage is that a sufficient ESD resistance can be obtained without adding a resistance for protecting the input inverter 25 from electrostatic stress.
[0049]
FIG. 27A is a schematic block diagram showing a circuit of a fourth application example in which the N-channel MOS transistor 9 according to the present invention is added to the input terminal as a protection element. The conventional general input protection circuit is such that a protection diode 27 is used as shown in FIG. 1B, but the input protection resistor 26 has to be set to a notably high value, that is, if the input protection resistor 26 is severe from several kΩ, Unless the resistance is set to several tens kΩ, a sufficient ESD resistance cannot be secured. However, by adopting this application example, the input protection resistor 26 can secure a resistance value of several kΩ or less (5 kΩ or less) or a sufficient ESD withstand voltage without adding it, which is very effective. In particular, at the input terminal of a semiconductor integrated circuit device requiring a high-speed response, a delay due to an increase in the CR time constant of the input protection resistor 26 can be largely avoided, which is very useful. Here, the input protection resistor 26 is located on the left side of the N-channel MOS transistor of the present invention in the figure, but the same effect can be obtained even if it is located on the right side.
[0050]
In recent years, progress in high integration and high speed due to miniaturization of semiconductor integrated circuit devices has been remarkable, but in order to realize higher speed, the junction capacitance of the source S and drain D of the MOS transistor to the substrate SUB is a problem. It becomes. Therefore, the following element structure is being realized.
FIG. 28 is a schematic sectional view showing a thin film transistor formed on an insulating film. It is referred to as a so-called TFT transistor or SOI transistor. Hereinafter, it is referred to as an SOI transistor for simplicity. As can be seen from FIG. 28, the bottom surfaces of the source S and the drain D are in contact with the insulating film 30 instead of the substrate SUB29 to reduce the junction capacitance, and the substrate SUB29 has almost only the channel region ch. The substrate SUB cannot take the potential 29, and the PN junction 28 has an extremely small area as compared with the conventional MOS transistor. As a result, the ESD resistance of the transistor itself is greatly reduced. Even if a general protection diode 27 as shown in the application example 4 is used, almost no effect can be expected.
[0051]
Therefore, it is very effective to use the N-channel MOS transistor according to the present invention for the input and output terminals of the semiconductor integrated circuit device including the SOI transistor as shown in the first to fourth application examples. This is a fifth application example (not shown). Of course, such an N-channel MOS transistor may be any of the first to tenth embodiments. Not only for input and output but also for MOS transistors constituting a power supply system (for example, inserting an N-channel MOS transistor between the power supply terminal 5 and the ground terminal 6 in FIG. 22) is very effective. Also, it is more effective to apply to all MOS transistors in the internal circuit.
[0052]
【The invention's effect】
As described above, according to the present invention, a semiconductor integrated circuit including an insulated gate field effect type peripheral transistor provided at a connection portion with an external circuit and an insulated gate field effect type internal transistor forming an internal circuit In the circuit device, since the peripheral transistor has a channel structure in which the electrostatic stress current is more easily released than the internal transistor, there is an effect that the ESD resistance of the peripheral transistor can be made higher than that of the internal transistor. In general, peripheral transistors are directly affected by electrostatic stress as compared with internal transistors. Therefore, by improving the ESD resistance of the peripheral transistors, the reliability of the entire semiconductor integrated circuit device can be improved. Further, in the present invention, while the ESD resistance of the peripheral transistor is selectively improved, the internal transistor does not require any change in the structure and operating characteristics. It is durable.
[Brief description of the drawings]
FIG. 1 is a schematic diagram for explaining a basic configuration and operation of a peripheral transistor incorporated in a semiconductor integrated circuit device according to the present invention.
FIG. 2 is a schematic plan view showing a first embodiment of a peripheral transistor according to the present invention.
FIG. 3 is a graph for explaining the operation of the first embodiment.
FIG. 4 is a schematic plan view showing a second embodiment of the peripheral transistor according to the present invention.
FIG. 5 is a graph showing a relationship between a channel length and an ESD withstand voltage in a peripheral transistor.
FIG. 6 is a schematic plan view showing a third embodiment of the peripheral transistor according to the present invention.
FIG. 7 is a schematic partial sectional view showing the structure of the third embodiment.
FIG. 8 is an equivalent circuit diagram for explaining the operation of the third embodiment.
FIG. 9 is a plan view showing a fourth embodiment of the peripheral transistor according to the present invention.
FIG. 10 is a schematic sectional view showing the structure of the fourth embodiment.
FIG. 11 is an equivalent circuit diagram for explaining the operation of the fourth embodiment.
FIG. 12 is a schematic partial sectional view showing a fifth embodiment of the peripheral transistor according to the present invention.
FIG. 13 is a schematic plan view showing a sixth embodiment of the peripheral transistor according to the present invention.
FIG. 14 is a partial sectional view showing the structure of the sixth embodiment.
FIG. 15 is a current-voltage characteristic graph for explaining the operation of the sixth embodiment.
FIG. 16 is a graph showing a relationship between a channel length of a peripheral transistor and an ESD tolerance.
FIG. 17 is a schematic partial sectional view showing a seventh embodiment of the peripheral transistor according to the present invention.
FIG. 18 is a schematic partial sectional view showing an eighth embodiment of the peripheral transistor according to the present invention.
FIG. 19 is a schematic plan view showing a ninth embodiment of a peripheral transistor according to the present invention.
FIG. 20 is a schematic partial sectional view showing the structure of the ninth embodiment.
FIG. 21 is a schematic partial sectional view showing a tenth embodiment of a peripheral transistor according to the present invention.
FIG. 22 is a schematic block diagram showing a general configuration of a semiconductor integrated circuit device.
FIG. 23 is a sectional view showing a general CONV structure of an N-channel MOS transistor.
FIG. 24 is a sectional view showing a general LDD structure of an N-channel MOS transistor.
FIG. 25 is a graph showing the relationship between the general channel length of a MOS transistor and the transistor breakdown voltage.
FIG. 26A is a schematic block diagram showing a circuit of a first application example in which an N-channel MOS transistor 9 according to the present invention is added as a protection element to an N-channel open drain output.
(B) A schematic block diagram showing a circuit of a second application example in which an N-channel MOS transistor 9 according to the present invention is added to a CMOS output terminal as a protection element.
(C) is a schematic block diagram showing a circuit of a third application example in which an N-channel MOS transistor 9 according to the present invention is added as a protection element to an input / output terminal.
FIG. 27A is a schematic block diagram showing a circuit of a fourth application example in which an N-channel MOS transistor 9 according to the present invention is added as a protection element to an input terminal.
FIG. 1B is a schematic block diagram showing a conventional general input protection circuit.
FIG. 28 is a schematic sectional view showing a thin film transistor formed on an insulating film.
[Explanation of symbols]
0 Semiconductor integrated circuit device
1 Internal circuit
2 Connection
3 Input terminal
4 Output terminal
5 Power supply terminal
6 Ground terminal
7 Input protection circuit
8 CMOS inverter
9 N-channel MOS transistor

Claims (1)

An input terminal, an output terminal, a power supply terminal, and a ground terminal; and an internal circuit including an internal MOS transistor on the same semiconductor substrate. The input terminal, the output terminal, the power supply terminal, and the ground terminal A semiconductor integrated circuit having a connection portion including a peripheral MOS transistor interposed between any one of the internal circuits and
The peripheral MOS transistor has a first channel width portion having a first channel length, and a second channel width portion having a second channel length shorter than the first channel length,
The second channel width portion is sandwiched between the two first channel width portions, and the width of the second channel width portion in the channel width direction is equal to the width of any of the first channel width portions. Formed shorter than the width of
The semiconductor integrated circuit according to claim 1, wherein the second channel length is shorter than a shortest channel length of the internal transistor.

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