JP3688703B2 - Semiconductor memory device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a semiconductor memory device and a manufacturing method thereof.

  When trying to manufacture highly reliable semiconductor memory devices such as DRAMs, it reduces the resistance of capacitor electrodes and wiring, and reduces the number of processes to provide an inexpensive device. There are various demands such as flattening the surface when performing lithography in order to widen the process margin.

  As a conventional method of manufacturing a DRAM having a stack type capacitor, after forming a wiring such as a bit line, a contact and a storage electrode for a storage electrode of the capacitor are formed, and then a capacitor insulating film and a counter electrode are formed. There is one that forms wiring (for example, Non-Patent Document 1).

  However, when the manufacturing method as described above is used, even if the counter electrode material is devised to reduce the resistance of the capacitor electrode, flattening at the time of performing lithography is not realized. Therefore, it is not easy to manufacture a device having a fine pattern such as 1GDRAM.

  On the other hand, there is another example of a conventional stacked capacitor (for example, Non-Patent Document 2). Hereinafter, the prior art described in Non-Patent Document 2 will be briefly described with reference to FIG.

First, a thermal oxide film 162 having a thickness of 600 nm is formed on a silicon substrate 161, and a contact hole is opened in the thermal oxide film 162. Subsequently, a polycrystalline silicon plug 163 is formed in the contact hole (FIG. 35A). Next, a TiN film 164 and a RuO ₂ film 165 having a thickness of 500 nm are formed on the entire surface by sputtering (FIG. 35B). Next, an island-shaped resist mask 166 is formed on the RuO ₂ film 165 using a lithography process, and the RuO ₂ film 165 and the TiN film 164 are patterned by the RIE method using the resist mask 166 as a mask (FIG. 35C). Next, after surface treatment is performed on the RuO ₂ film 165, an SrTiO ₃ film 167 is deposited at 450 ° C. by using the ECRMOCVD method. Finally, a TiN film and an Al film 168 are formed on the entire surface by sputtering, Al is used as the plate electrode 168, SrTiO ₃ as the capacitor insulating film 167, and the RuO ₂ film as the storage electrode 165 (Al / TiN / SrTiO ₃ / RuO). ₂ / TiN / poly-Si) stacked capacitor is completed (FIG. 35D).

  The above prior art shows a manufacturing process of only storage electrode contacts and capacitors. When applied to an actual DRAM, in addition to the above processes, a MOSFET forming process and a bit line forming process are added. Then, it can be considered that the polycrystalline silicon plug is connected not to the silicon substrate but to the source or drain of the MOSFET.

  However, in the above prior art, the storage nodes are separated by patterning the storage node conductive film using the island-shaped resist pattern as a mask. Therefore, there is a problem that the storage nodes adjacent to each other beyond the limit of lithography cannot be brought close to each other, and the effective storage node electrode area cannot be increased so much.

Further, in the above prior art, when the plurality of storage node electrodes 165 are arranged in a matrix as shown in FIG. 36A, FIG. 36B, which is a cross-sectional view taken along line AA ′ of FIG. As shown, when the storage node electrode 165 is misaligned with respect to the storage node contact 163, a capacitor having a structure in which the plate electrode 168 and the storage node contact 163 directly face each other with the capacitor insulating film 167 interposed therebetween is formed. There is a problem that the characteristics of the capacitor insulating film 167 deteriorate due to the combination of materials, leading to deterioration of capacitor characteristics.
IEDM95-907 PY.Lesaicherre etal., "A Gbit-scale DRAM stacked capacitor technology with ECR MOCVD SrTiO3 and RIE patterned RuO2 / TiN storage nodes", IEDM Technical Digest, pp.831-834,1994

  As described above, conventionally, there has been a problem that it is difficult to form a fine pattern because it is difficult to flatten when performing lithography.

  In addition, it is difficult to increase the area of the storage node electrode because the storage nodes cannot be closer than the limit of lithography, and the capacitor characteristics are deteriorated due to misalignment of the storage node electrode and the storage node contact. There was a problem that it was easy.

  SUMMARY OF THE INVENTION A first object of the present invention is to provide a semiconductor memory device capable of easily forming a layer where a capacitor is formed and a region where the capacitor is not formed in the same layer as the capacitor and whose upper surface is flattened. And a manufacturing method thereof.

  A second object of the present invention is to provide a semiconductor memory device that can achieve a large capacitor area and is excellent in electrical characteristics and reliability, and a manufacturing method thereof.

The present invention includes a first conductive film, a first insulating film formed on the first conductive film, and a second conductive film formed on the first insulating film. In the semiconductor memory device in which the storage capacitor is formed on the main surface side of the semiconductor substrate, the capacitor is formed in the first recess of the second insulating film, and the second insulating film includes the second insulating film. The third conductor film is embedded in the first recess and the second recess, and the third conductor film is embedded in the first recess. Is provided so as to entirely cover the second conductive film, and the distance between the upper surface of the third conductive film embedded in the first recess and the upper surface of the semiconductor substrate is the second conductive film. Approximately equal to the distance between the upper surface of the third conductive film embedded in the recess and the upper surface of the semiconductor substrate. And it features.

The present invention also includes a first conductor film, a first insulating film formed on the first conductor film, and a second conductor film formed on the first insulating film. In the semiconductor memory device in which the configured storage capacitor is formed on the main surface side of the semiconductor substrate, the capacitor is formed in the first recess of the second insulating film, and the second insulating film includes A second recess is formed, and the third conductor film is embedded in the first recess and the second recess, and the third conductive film is embedded in the first recess. The body film is provided so as to entirely cover the second conductor film, and a distance between the upper surface of the second conductor film of the capacitor formed in the first recess and the upper surface of the semiconductor substrate. Between the upper surface of the third conductor film embedded in the second recess and the upper surface of the semiconductor substrate Characterized in that it is away or less.

  According to the semiconductor memory device, the third conductor film can reduce the resistance, and the region where the first recess is formed (corresponding to the region having the capacitor) and the second recess are formed. Since the height of the third conductor film can be made substantially equal in the formed region (corresponding to the region having no capacitor), planarization can be achieved.

The present invention also includes a first conductor film, a first insulating film formed on the first conductor film, and a second conductor film formed on the first insulating film. In a method of manufacturing a semiconductor memory device in which a configured storage capacitor is formed on the main surface side of a semiconductor substrate, a second insulating film having a first recess and the first conductive film provided in the first recess Forming a body film; forming a second recess in the second insulating film; and forming the first conductive film, the first insulating film, and the second conductive film. And a step of embedding a third conductive film in the first concave portion and the second concave portion at the same time and covering the entire surface of the second conductive film in the first concave portion. It is characterized (referred to as manufacturing method A).

The present invention also includes a first conductor film, a first insulating film formed on the first conductor film, and a second conductor film formed on the first insulating film. In the method for manufacturing a semiconductor memory device in which the configured storage capacitor is formed on the main surface side of the semiconductor substrate, a step of forming a second insulating film and a step of selectively removing the second insulating film And a step of burying the first conductor film in a portion where the second insulating film is selectively removed, and further selectively removing the second insulating film to form the first conductor. Forming a first recess for projecting the film; forming a second recess in the second insulating film; and the first conductor film, the first insulating film, and the second conductor. At the same time the film and is formed of the first recess and the second recess, and the second conductive film of the first recess Characterized by a step of embedding a third conductive film covering a surface manner (the production method B).

  In this case, another insulating film is provided under the second insulating film, and the second insulating film is selectively removed (etched) to be used as an etching stopper when forming the first recess. May be.

  According to the semiconductor memory device manufacturing methods A and B, since the third conductor film is buried in the first recess and the second recess at the same time, the resistance can be reduced without increasing the manufacturing process. The height of the third conductor film can be increased in a region where the first recess is formed (corresponding to a region having a capacitor) and a region where the second recess is formed (corresponding to a region having no capacitor). Since the thicknesses can be made substantially equal, planarization can be achieved, and the process margin in lithography can be increased.

  In the manufacturing methods A and B, in the manufacturing method A, after the step of forming the second insulating film having the first recess and the first conductor film provided in the first recess, the manufacturing method B In the step, the first insulating film and the second conductor are formed after the step of further selectively removing the second insulating film to form a first recess for projecting the first conductor film. Forming a film, and forming a second recess in the second insulating film by selectively removing the second conductor film, the first insulating film, and the second insulating film. And, after forming the third conductor film, removing the third conductor film, the second conductor film, and the first insulating film by a predetermined thickness, thereby removing the first conductor film. The first recess formed with the film, the first insulating film, and the second conductor film; It may be a recess and at the same time and a step of embedding said third conductive film.

  In the manufacturing method A, the second insulating film is composed of an insulating film X and an insulating film Y on the insulating film X, and the second insulating film having the first recess and the first recess Forming the first conductive film provided on the substrate, forming the insulating film X, selectively removing the insulating film X, and a portion where the insulating film X is selectively removed A step of embedding the first conductive film, a step of forming the insulating layer Y on the insulating film X and the first conductive film, and selecting the insulating film X and the insulating film Y. May be removed by the step of forming the first concave portion in which the first conductive film is formed.

  In the manufacturing method A, the step of forming the first conductive film includes forming the second insulating film having the first concave portion and the first conductive film provided in the first concave portion. Forming the second insulating film so as to cover the first conductive film, and selectively removing the second insulating film to form the first conductive film. Alternatively, the first recess may be formed.

  In the manufacturing method A, the step of forming the second insulating film having the first recess and the first conductor film provided in the first recess includes the first conductor film, A step of forming a first insulating film and the second conductor film, a step of forming the second insulating film so as to cover the second conductor film, and the second insulating film being selected. Removing the first conductive film, and forming the first recess in which the first conductive film, the first insulating film, and the second conductive film are formed.

  The present invention also provides a third insulating film formed on the main surface side of the semiconductor substrate, a first contact formed in the third insulating film and connected to the semiconductor substrate, and the third contact A fourth conductor film formed on the insulating film and in contact with the first contact and a region on the third insulating film where the fourth conductor film is not formed are selectively selected with a uniform thickness. And a fourth insulating film covering.

  The present invention also provides a third insulating film formed on the main surface side of the semiconductor substrate, a first contact formed in the third insulating film and connected to the semiconductor substrate, and the third contact A fourth conductor film formed on the insulating film and in contact with the first contact and a region on the third insulating film where the fourth conductor film is not formed are selectively selected with a uniform thickness. A fourth insulating film covering the first insulating film; a fifth insulating film formed on the fourth conductive film and the fourth insulating film; and a fifth conductive film formed on the fifth insulating film. And a body membrane.

  In the present invention, the semiconductor device further includes a MOS transistor formed on the main surface side of the semiconductor substrate and surrounded by an element isolation film, and the first contact is connected to one of a source and a drain of the MOS transistor. It is preferable.

  In the present invention, a second contact formed in the third insulating film and connected to the other of the source and drain of the MOS transistor and a bit line connected to the second contact are further provided. It is preferable to have.

  The present invention also provides a MOS transistor formed on a semiconductor substrate and surrounded by an element isolation film, a sixth insulating film formed on the main surface side of the semiconductor substrate on which the MOS transistor is formed, A second contact formed in the sixth insulating film and connected to one of the source and drain of the MOS transistor, and a bit formed on the sixth insulating film and connected to the second contact A MOS transistor, and a seventh insulating film formed on the sixth insulating film on which the bit line is formed, and the MOS type formed through the sixth insulating film and the seventh insulating film A first contact connected to the other of the source and drain of the transistor; a fourth conductor film formed on the seventh insulating film and in contact with the first contact; and on the seventh insulating film The fourth conductor A fourth insulating film that selectively covers a region where the film is not formed with a uniform thickness; a fourth insulating film formed on the fourth conductive film and the fourth insulating film; and And a fifth conductor film formed on the fifth insulating film.

  According to the semiconductor device, the fourth insulating film (generally the stopper in the etching process) is formed in the region where the fourth conductor film (generally the storage node electrode) is not formed on the third insulating film. Therefore, even if there is a shift between the first contact (generally a storage node contact) and the fourth conductor film, the fifth insulating layer is not formed in the shifted region. Since the fourth insulating film is formed in addition to the film (generally the capacitor insulating film), the capacitors (fourth conductor film and fifth conductor film (general Insulating deterioration caused by the fourth insulating film and the fifth insulating film sandwiched between the first and second plate electrodes) can be suppressed. Therefore, it is possible to prevent deterioration of the performance of the entire capacitor, and to obtain a highly reliable semiconductor device (DRAM or the like).

  The present invention also includes a step of forming a third insulating film on the main surface side of the semiconductor substrate, a step of forming a first contact connected to the semiconductor substrate in the third insulating film, Forming a fourth insulating film on the third insulating film; forming an eighth insulating film on the fourth insulating film; and the fourth insulating film and the eighth insulating film. Forming a groove portion through which the surface of the first contact is exposed, forming a fourth conductor film in the groove portion, and removing the eighth insulating film. It is characterized by.

  The present invention also includes a step of forming a third insulating film on the main surface side of the semiconductor substrate, a step of forming a first contact connected to the semiconductor substrate in the third insulating film, Forming a fourth insulating film on the third insulating film; forming an eighth insulating film on the fourth insulating film; and the fourth insulating film and the eighth insulating film. A step of forming a groove through which the surface of the first contact is exposed, a step of forming a fourth conductor film in the groove, and removing the eighth insulating film to form the fourth insulating film. A step of exposing a surface of the insulating film, a step of forming a fifth insulating film on the exposed fourth insulating film and the fourth conductor film, and a fifth insulating film on the fifth insulating film. And a step of forming a conductor film.

  In the present invention, the semiconductor device further includes a step of forming a MOS transistor surrounded by an element isolation film on a main surface side of the semiconductor substrate, and the first contact is connected to one of a source and a drain of the MOS transistor. It is preferable.

  In the invention, a step of forming a second contact connected to the other of the source and the drain of the MOS transistor in the third insulating film, and the second insulating film in the third insulating film. It is preferable to further include a step of forming a bit line connected to the contact.

  The present invention also includes a step of forming a MOS transistor surrounded by an element isolation film on a main surface side of a semiconductor substrate, and a sixth insulating film on the main surface side of the semiconductor substrate on which the MOS transistor is formed. Forming a second contact connected to one of a source and a drain of the MOS transistor in the sixth insulating film, and forming the second contact on the sixth insulating film. Forming a bit line connected to the bit line; forming a seventh insulating film on the sixth insulating film on which the bit line is formed; the sixth insulating film and the seventh insulating film; Forming a first contact that passes through the first insulating film and connects to the other of the source and drain of the MOS transistor, forming a fourth insulating film on the seventh insulating film, and the fourth insulation 8th insulation on membrane Forming a groove portion penetrating the fourth insulating film and the eighth insulating film and exposing the surface of the first contact, and forming a fourth conductor film in the groove portion. A step of forming, a step of removing the eighth insulating film to expose a surface of the fourth insulating film, and a fifth layer on the exposed fourth insulating film and the fourth conductor film. The method includes a step of forming an insulating film and a step of forming a fifth conductor film on the fifth insulating film.

  In the invention, the step of forming the groove includes the step of anisotropically etching the eighth insulating film in the vertical direction using the fourth insulating film as a stopper, and the fourth insulating film after this step. It is preferable to have a step of isotropically etching the eighth insulating film in the lateral direction by using as a stopper and a step of etching the fourth insulating film exposed after this step.

  In the above invention, it is preferable that the eighth insulating film is used as a mask when the fourth insulating film is etched.

  According to the semiconductor device manufacturing method, a misalignment occurs between the first contact (generally a storage node contact) and the fourth conductor film (generally a storage node electrode) due to misalignment or the like. However, in addition to the fifth insulating film (generally a capacitor insulating film), a fourth insulating film (generally a stopper insulating film in the etching process) is also formed in this shifted region. The capacitor is formed in a region where the fourth insulating film and the fifth insulating film are sandwiched between the fourth conductor film and the fifth conductor film (generally a plate electrode). The deterioration of the insulating property caused by () can be suppressed. Therefore, it is possible to prevent deterioration of the performance of the entire capacitor and to manufacture a highly reliable semiconductor device (DRAM or the like). Further, since the fourth conductor film is embedded in the groove portion, if the groove portion is widened by isotropic etching such as wet etching, the area of the fourth conductor film embedded in the groove portion is reduced accordingly. Can be bigger. Therefore, the capacitor area, that is, the capacitance of the capacitor can be increased.

A semiconductor memory device according to another aspect of the present invention includes a semiconductor substrate, a storage electrode formed on the bottom surface of the recess of the insulating layer, a capacitor insulating film formed on the storage electrode, and the capacitor insulating film A plurality of multilayer capacitors formed on the semiconductor substrate having a plate electrode formed on and lower than an upper edge of the recess; and the plate electrode is entirely covered and embedded in the recess a memory cell unit formed on the semiconductor substrate and a connected plate wiring layer on the plate electrode with being, the adjacent memory cell portion is formed on the semiconductor substrate, a wiring layer A peripheral circuit section provided, and the wiring layer has an upper surface substantially the same height as the upper surface of the plate wiring layer.

A semiconductor memory device according to another aspect of the present invention includes a semiconductor substrate, a storage electrode formed on the bottom surface of the recess of the insulating layer, a capacitor insulating film formed on the storage electrode, and the capacitor insulating film A plurality of multilayer capacitors formed on the semiconductor substrate having a plate electrode formed on and lower than an upper edge of the recess; and the plate electrode is entirely covered and embedded in the recess a memory cell unit formed on the semiconductor substrate and a connected plate wiring layer on the plate electrode with being, the adjacent memory cell portion is formed on the semiconductor substrate, a wiring layer The plate wiring layer and the wiring layer are formed of the same material, and the upper surface of the plate wiring layer is the upper surface of the wiring layer. It is characterized in that it is qualitatively the same height.

Furthermore, a semiconductor memory device according to another aspect of the present invention includes a semiconductor substrate, a transistor formed on the semiconductor substrate and having a gate, a source region, and a drain region, and first, second, And a third insulating layer having a recess on the surface; a first contact plug formed in the first insulating layer and connected to one of the source region and the drain region of the transistor; A bit line formed on the first insulating layer and connected to one of the source region and the drain region of the transistor via the first contact plug, and formed in the first insulating layer A second contact plug connected to the other of the source region and the drain region of the transistor, and formed in the second insulating layer. A third contact plug connected to the second contact plug, and the source region of the transistor and the third contact plug formed on the second insulating layer and through the third and second contact plugs. A capacitor having a storage electrode, a capacitor insulating film, and a plate electrode electrically connected to the other of the drain regions, and embedded in the concave portion of the third insulating layer to cover the plate electrode entirely. a plate wiring layer formed Te, comprising a wiring layer formed in the peripheral circuit region, wherein the plate wiring layer and the wiring layer with are formed of the same material, the upper surface of the plate wiring layer The wiring layer is substantially the same height as the upper surface of the wiring layer.

  In the semiconductor memory device according to the present invention, the resistance can be reduced, and the third conductor film is formed in the region where the first hole is formed and the region where the second hole is formed. Since the heights can be made substantially equal, it is possible to achieve flattening. That is, a layer that covers the region where the capacitor is formed and the region where the capacitor is not formed in the same layer as the capacitor and has a flat upper surface is easily formed.

  In the method for manufacturing a semiconductor memory device according to the present invention, since the third conductor film is buried in the first hole and the second hole at the same time, low resistance can be realized without increasing the manufacturing process. In addition, the height of the third conductor film can be made substantially equal in the region in which the first hole is formed and the region in which the second hole is formed, thereby achieving flattening. It is possible to increase the process margin in lithography. That is, it is possible to easily form a layer that covers a region where the capacitor is formed and a region where the capacitor is not formed in the same layer as the capacitor and has a flat upper surface.

  In the semiconductor memory device of the present invention, even if there is a deviation between the first contact (generally a storage node contact) and the fourth conductor film (generally a storage node electrode), In addition to the fifth insulating film (generally a capacitor insulating film), a fourth insulating film (generally a stopper insulating film in an etching process) is also formed in the shifted region. It is possible to suppress deterioration of insulation caused by the formed capacitor, and to prevent performance deterioration of the entire capacitor.

  Further, in the method for manufacturing a semiconductor memory device according to the present invention, even if a shift occurs between the first contact and the fourth conductor film, the insulation deterioration caused by the capacitor formed in the shifted region, etc. Since the fourth conductor film is embedded in the groove, the area of the fourth conductor film embedded in the groove can be increased by expanding the groove by isotropic etching. The capacitor area, that is, the capacitance of the capacitor can be increased.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings when applied to a dynamic RAM equipped with a stacked capacitor.

  First, 1st Embodiment of this invention is described according to the manufacturing process shown to FIG. 1 (A1)-FIG. 4 (A8). In each of the process diagrams (A1) to (A8), the portion shown on the left side mainly indicates a region having a capacitor (memory array region), and the portion shown on the right side mainly has a region having no capacitor ( Peripheral circuit region), and both are formed on the same semiconductor substrate (the same applies to drawings according to other embodiments).

  First, a gate insulating film and a gate wiring 14 (not shown) are formed on a silicon substrate 11 (semiconductor substrate) on which an element isolation insulating film 12 is formed, and source / drain diffusion layers (not shown) are formed on the surface of the silicon substrate 11. Thus, a plurality of transistors are arranged. Further, an insulating film 15 is formed around the gate wiring 14, and an interlayer insulating film 13 is embedded between the gate wirings 14. Subsequently, a contact hole is formed in a predetermined region of the interlayer insulating film 13 by RIE. Subsequently, after depositing a conductive film such as polysilicon, the conductive layer is etched back to form a plug 16 made of the conductive film in the contact hole (A1).

  Next, an interlayer insulating film 17 is deposited, and the interlayer insulating film 17 and the interlayer insulating film 13 are selectively removed by RIE or the like to form contact holes and wiring grooves 18a and 18b. Subsequently, after depositing a conductive film such as W, the conductive film is planarized by a method such as RIE or CMP to form a wiring 19 (A2).

  Note that although not illustrated, the wiring 19 functions as a bit line in the DRAM cell array region in FIG. 1A2, so that the bit line of the memory cell array can be formed simultaneously in the step A2. That is, in the contact hole forming step, the bit line contact hole and the bit line wiring groove can be simultaneously formed. Further, a bit line plug and a bit line can be formed in the same process as the formation of the wiring 19. The bit line is connected to one of the source / drain diffusion layers of the transistor, and a capacitor to be described later is connected to the other.

  Next, an interlayer insulating film 20 is deposited, and the interlayer insulating film 20 and the interlayer insulating film 17 are selectively removed by RIE or the like to form a contact hole 21, and the contact hole 21 is connected to the plug 16. The plug 22 is formed (A3).

Next, an interlayer insulating film 23 is deposited, a predetermined region of the interlayer insulating film 23 is removed, a hole 24 is formed, and the surface of the plug 22 is exposed. Subsequently, after filling the hole 24 with a conductive film, the upper surface of the conductive film is made lower than the upper surface of the interlayer insulating film 23 by RIE or the like, and the capacitor lower electrode layer 25 connected to the plug 22 is used. Form. As the constituent material of the conductive film to be the lower electrode layer 25 can be a Pt (platinum) and Ru (ruthenium), or RuO ₂ or the like (A4).

  Next, the region not having the capacitor is covered with a resist, and the interlayer insulating film 23 in the region having the capacitor is removed by CDE (Chemical Dry Etching), wet etching, or the like to expose the interlayer insulating film 20 to be used for the capacitor. A hole 26 having a lower electrode layer 25 is formed (A5).

Next, the capacitor insulating film 27 and the capacitor upper electrode layer 28 are deposited, the region having the capacitor is covered with a resist, and the capacitor insulating film 27 and the capacitor upper electrode layer 28 in the region not having the capacitor are etched away. To form a capacitor. As the capacitor insulating film 27, a high dielectric thin film such as SrTiO ₃ or Ba _x Sr _1-x TiO can be used. Further, as the constituent material of the conductive film to be the capacitor upper electrode layer 28, Pt, Ru, RuO ₂ or the like can be used as in the lower electrode layer 25 (A6).

  Next, the interlayer insulating film 23 and the interlayer insulating film 20 are selectively removed by RIE or the like to form contact holes and wiring grooves 29a and 29b, and the surface of the wiring 19 is exposed (A7).

  Subsequently, after depositing a conductive film such as W, the conductive film is flattened by a method such as etch back or CMP (Chemical Mechanical Polishing), and in the region having the capacitor, the upper electrode layer 28 for the capacitor is backed. The plate wiring 30a is formed in the hole 26, and the wiring 30b is formed in the holes 29a and 29b in the region having no capacitor (A8).

  In the device manufactured by the above process, the distance between the upper surface of the capacitor upper electrode layer 28 and the upper surface of the silicon substrate 11 is equal to or smaller than the distance between the upper surface of the wiring 30b and the upper surface of the silicon substrate 11 (in FIG. The distance between the upper surface of the electrode layer 28 and the upper surface of the silicon substrate 11 is smaller than the distance between the upper surface of the wiring 30b and the upper surface of the silicon substrate 11, and the plate wiring 30a, the wiring 30b, and the interlayer insulating film 23 All the distances between the upper surface and the upper surface of the silicon substrate 11 are equal. Therefore, planarization between the region having the capacitor and the region not having the capacitor can be realized.

  In the above-described steps, the conductive film is simultaneously embedded in the hole 26 and the holes 29a and 29b to form the plate wiring 30a and the wiring 30b at the same time, so that the manufacturing process can be shortened.

  Next, 2nd Embodiment of this invention is described according to the manufacturing process shown to FIG. 5 (B1)-FIG. 7 (B5). The basic components are substantially the same as those of the first embodiment, and there are manufacturing steps common to the first embodiment. Therefore, unless otherwise indicated, these are the corresponding drawings and corresponding steps of the first embodiment. The description will be referred to and the description will be omitted.

  After the step (A3) of FIG. 2 in the first embodiment, the insulating film 31 and the interlayer insulating film 23 are formed. The insulating film 31 serves as an etching stopper when a hole is formed in the interlayer insulating film 23 in a later step (B1).

  Next, a predetermined region of the interlayer insulating film 23 and the insulating film 31 is removed to form a hole 24 to expose the surface of the plug 22. Subsequently, after filling the hole 24 with a conductive film, the upper surface of the conductive film is made lower than the upper surface of the interlayer insulating film 23 by RIE or the like to form the capacitor lower electrode layer 25 (B2). .

  Next, the region not having the capacitor is covered with a resist, and the interlayer insulating film 23 in the region having the capacitor is removed by CDE, wet etching, or the like, thereby forming a hole 26 having the capacitor lower electrode layer 25. At this time, since the insulating film 31 serving as an etching stopper is formed under the interlayer insulating film 23, the etching of the interlayer insulating film 23 can be stopped by the insulating film 31 (B3).

  Next, the capacitor insulating film 27 and the capacitor upper electrode layer 28 are deposited, the region having the capacitor is covered with a resist, and the capacitor insulating film 27 and the capacitor upper electrode layer 28 in the region not having the capacitor are etched away. To form a capacitor. Next, the interlayer insulating film 23, the insulating film 31, and the interlayer insulating film 20 are selectively removed by RIE or the like to form contact holes and wiring grooves 29a and 29b, and the surface of the wiring 19 is exposed (B4).

  Thereafter, in the same manner as in the step (A8) in the first embodiment, in the region having the capacitor, the plate wiring 30a serving as the backing of the capacitor upper electrode layer 28 is formed in the hole 26, and in the region having no capacitor. Forms the wiring 30b in the holes 29a and 29b (B5).

  The same effects as those of the first embodiment can be obtained even in the case manufactured by the above steps.

  Next, 3rd Embodiment of this invention is described according to the manufacturing process shown to FIG. 8 (C1)-FIG. 10 (C6). The basic components are substantially the same as those of the first embodiment, and there are manufacturing steps common to the first embodiment. Therefore, unless otherwise indicated, these are the corresponding drawings and corresponding steps of the first embodiment. The description will be referred to and the description will be omitted.

  After the step (A3) of FIG. 2 in the first embodiment, an interlayer insulating film 32 is deposited, and a predetermined region of the interlayer insulating film 32 is removed to form a hole. Subsequently, a conductive film is deposited, and planarized using a technique such as CMP to fill the conductive film in the previously formed hole, thereby forming a capacitor lower electrode layer 25 (C1).

  Next, an interlayer insulating film 33 is further deposited on the interlayer insulating film 32 and the capacitor lower electrode layer 25 (C2).

  Next, the region not having the capacitor is covered with a resist, and the interlayer insulating films 32 and 33 in the region having the capacitor are removed by CDE, wet etching, or the like to expose the interlayer insulating film 20, and the capacitor lower electrode layer 25 is removed. A hole 26 having C is formed (C3).

  The subsequent steps (C4) to (C6) are substantially the same as the steps (A6) to (A8) in the first embodiment, and as shown in FIG. A plate wiring 30a serving as the backing of the electrode layer 28 is formed in the hole 26, and a wiring 30b is formed in the holes 29a and 29b in a region having no capacitor.

  The same effects as those of the first embodiment can be obtained even in the case manufactured by the above steps.

  Next, 4th Embodiment of this invention is described according to the manufacturing process shown in FIG.11 (D1)-FIG.12 (D4). The basic components are substantially the same as those of the first embodiment, and there are manufacturing steps common to the first embodiment. Therefore, unless otherwise indicated, these are the corresponding drawings and corresponding steps of the first embodiment. The description will be referred to and the description will be omitted.

  After the step (A3) of FIG. 2 in the first embodiment, a conductive film is deposited and patterned into a predetermined shape to form a lower electrode layer 25 of the capacitor (D1).

  Next, the interlayer insulating film 34 is deposited on the interlayer insulating film 20 and the capacitor lower electrode layer 25 so that the upper surface thereof is higher than the upper surface of the capacitor lower electrode layer 25 (D2).

  Next, the region not having the capacitor is covered with a resist, and the interlayer insulating film 34 in the region having the capacitor is removed by CDE, wet etching, or the like to expose the interlayer insulating film 20, and the capacitor lower electrode layer 25 is provided. The hole 26 is formed (D3).

  Thereafter, plate wiring 30a serving as the backing of the capacitor upper electrode layer 28 in the region having the capacitor, as shown in FIG. 12D4, by the same steps as steps (A6) to (A8) in the first embodiment. Is formed in the hole 26, and the wiring 30b is formed in the holes 29a and 29b in the region having no capacitor (D4).

  The same effects as those of the first embodiment can be obtained even in the case manufactured by the above steps.

  Next, 5th Embodiment of this invention is described according to the manufacturing process shown in FIG.13 (E1)-FIG.15 (E5). The basic components are substantially the same as those of the first embodiment, and there are manufacturing steps common to the first embodiment. Therefore, unless otherwise indicated, these are the corresponding drawings and corresponding steps of the first embodiment. The description will be referred to and the description will be omitted.

  A hole 26 having a capacitor lower electrode layer 25 is formed (E1) in the same manner as in step (A1) in FIG. 1 to step (A5) in FIG. In addition, you may make it comprise a shape as shown in FIG.13 (E1) with the method used in each embodiment other than 1st Embodiment.

  Next, an insulating film and a conductive film for forming the capacitor insulating film 27 and the capacitor upper electrode layer 28 are sequentially deposited (E2).

  Next, the capacitor upper electrode layer 28, the capacitor insulating film 27, the interlayer insulating film 23, and the interlayer insulating film 20 are selectively removed by RIE or the like to form contact holes and wiring grooves 29a and 29b, and the wiring 19 The surface of is exposed (E3).

  Next, a conductive film 30 such as W is deposited (E4).

  Subsequently, planarization is performed by removing the conductive film 30, the capacitor upper electrode layer 28, and the capacitor insulating film 27 by a method such as etch back or CMP, and in the region having the capacitor, the capacitor upper electrode layer 28 is formed. The plate wiring 30a serving as the backing is formed in the hole 26, and the wiring 30b is formed in the holes 29a and 29b in the region having no capacitor (E5).

  The same effects as those of the first embodiment can be obtained even in the case manufactured by the above steps.

  Next, a sixth embodiment of the present invention will be described in accordance with the manufacturing steps shown in FIGS. 16 (F1) to 18 (F6). The basic components are substantially the same as those of the first embodiment, and there are manufacturing steps common to the first embodiment. Therefore, unless otherwise indicated, these are the corresponding drawings and corresponding steps of the first embodiment. The description will be referred to and the description will be omitted.

  After the step (A3) of FIG. 2 in the first embodiment, a conductive film is deposited and patterned into a predetermined shape to form a capacitor lower electrode layer 25 (F1).

  Next, a capacitor insulating film 27 and a capacitor upper electrode layer 28 are sequentially deposited and patterned into a predetermined shape to form a capacitor (F2).

  Next, an interlayer insulating film 35 is deposited on the interlayer insulating film 20 and the capacitor (F3).

  Next, the region not having the capacitor is covered with a resist, and the interlayer insulating film 35 in the region having the capacitor is removed by CDE, wet etching, or the like to form the hole 26 having the capacitor (F4).

  Next, the interlayer insulating film 35 and the interlayer insulating film 20 are selectively removed by RIE or the like to form contact holes and wiring grooves 29a and 29b, and the surface of the wiring 19 is exposed (F5).

  Subsequently, after depositing a conductive film such as W, the conductive film is planarized by a method such as etchback or CMP, and in the region having the capacitor, the plate wiring 30a serving as the backing of the capacitor upper electrode layer 28 is formed in the hole. In addition, the wiring 30b is formed in the holes 29a and 29b in the region having no capacitor (F6).

  The same effects as those of the first embodiment can be obtained even in the case manufactured by the above steps.

  Hereinafter, a seventh embodiment of the present invention will be described in detail with reference to FIGS. 19 to 28.

  In addition, each figure (a) is AA 'cross section of each figure (c) (The figure corresponding to the plane pattern at the time of performing photolithography), Each figure (b) is BB' of each figure (c). A cross section is shown.

  First, an element isolation region 102 is formed on a semiconductor substrate 101 using silicon by STI (Shallow Trench Isolation), and a P-well region is formed by impurity ion implantation (FIG. 19).

Next, in order to form a transistor, a gate oxide film (not shown) of, for example, 6 nm is formed on the semiconductor substrate 101, and then a polycrystalline silicon film 103 a of about 50 nm and a tungsten silicide (about 100 nm) are formed as the gate electrode 103. A WSi) or tungsten (W) film 103b and a silicon nitride (SiN) 103c film of about 100 nm are deposited. After patterning the gate electrode 103, N-type impurities such as P and As are ion-implanted to form the source / drain diffusion layer 104. Subsequently, for example, a silicon nitride film 105 of 30 nm is deposited and etched back to form a sidewall on the gate electrode 103. After the formation of the transistor, an insulating film 106 (for example, BPSG or plasma SiO ₂ ) having a thickness of about 250 to 300 nm is deposited (FIG. 20).

  Next, the insulating film 106 is planarized using a CMP (Chemical Mechanical Polishing) method using the SiN film 103 c as a stopper, and then the insulating film 106 is patterned using a resist mask 107 (opening pattern). Thus, contact holes are formed in a self-aligned manner (FIG. 21).

  Next, the resist is removed, and a conductive film 108 for forming a plug, for example, a poly-Si film doped with P or As is deposited (FIG. 22).

Next, the conductive film 108 for forming the plug is planarized by CMP using the SiN film 103c as a stopper. Subsequently, an insulating film 109 (for example, BPSG or plasma SiO ₂ ) having a thickness of about 100 to 200 nm is deposited and planarized by CMP to form a bit line contact 110 that reaches the plug 108 formed earlier. Subsequently, a conductive film 111a made of, for example, about 20 nm of Ti / TiN and about 100 nm of W is deposited on the insulating film 109, an SiN film 111b of about 150 nm is deposited thereon, and these are patterned to form a bit. Line 111 is formed. Further, after depositing a SiN film 112 of about 30 nm, this is etched to form a sidewall on the side wall of the bit line.

Next, an insulating film 113 (for example, BPSG or plasma SiO ₂ ) having a thickness of about 400 nm is deposited so as to cover the bit line 111, and is planarized using a CMP method. Subsequently, the insulating film 113 is etched in a self-aligned manner with respect to the bit line 111 using a resist mask, and a contact hole is opened so as to reach the previously formed plug 108. Subsequently, after removing the resist, in order to form the storage node contact 114, the contact hole is filled with a conductive material, for example, barrier metal (Ti / TiN) and W, or poly Si doped with P, and planarized. (FIG. 23).

Next, a film having a high etching selection ratio with respect to the oxide film, for example, a 50 nm SiN film 115 is formed on the entire surface with a uniform thickness, and then an insulating film 116 (for example, BPSG or plasma SiO ₂ ) is formed on the entire surface. The insulating film 116 and the SiN film 115 are etched using the resist mask 121 having a hole pattern and etched using the RIE method to form the groove 117. (FIG. 24).

Next, a storage node electrode material 118 such as tungsten nitride (W / N), ruthenium (Ru), or ruthenium oxide (RuO _x ) having a thickness of 200 nm is deposited by sputtering so as to fill the trench 117 (FIG. 25).

  Next, the storage node electrode material 118 is polished and planarized by CMP to the upper surface of the insulating film 116 to form a storage node electrode. Ruthenium or a ruthenium compound used as the storage node electrode 118 is suitable as an electrode of a capacitor using a high dielectric film such as barium strontium titanate (BSTO), but is difficult to etch using RIE or the like. Therefore, as in this example, the storage node electrode 118 can be easily formed by embedding ruthenium or the like in the groove (FIG. 26).

  Next, the insulating film 116 is completely removed by wet etching so that the side surface of the storage node electrode 118 is exposed. At this time, since the SiN film 115 acts as a wet etching stopper, the insulating film 113 is not etched. The exposed SiN film 115 selectively covers a region where the storage node electrode 118 is not formed with a uniform thickness. That is, the SiN film 115 is not formed in the region above the thickness of the SiN film 115 on the side surface of the storage node electrode 118 and the upper surface of the storage node electrode 118 (FIG. 27).

  Next, as the capacitor dielectric film 119, for example, barium strontium titanate (BSTO) is deposited by CVD or sputtering. Subsequently, as the plate electrode 120, for example, a tungsten nitride film, ruthenium film or ruthenium oxide film with a thickness of about 100 nm is deposited and planarized by CMP to form a capacitor (FIG. 28).

  Thereafter, a DRAM is completed by forming wirings and the like using a normal method.

  FIG. 29 shows a state where the storage node contact 114 and the storage node electrode 118 are displaced. In this embodiment, since the stopper film 115 is formed under the capacitor dielectric film 119, even if such a shift occurs, it is possible to prevent deterioration of capacitor characteristics and the like.

  Next, an eighth embodiment of the present invention will be described in detail with reference to FIGS.

  Since the eighth embodiment is obtained by changing a part of the steps of the seventh embodiment shown in FIGS. 19 to 28, only the necessary explanation is given here, and the rest corresponds to the seventh embodiment. Reference should be made to the description and corresponding drawings.

  Since the first half of the process is the same as the process of the seventh embodiment (the process of FIGS. 19 to 23), the subsequent process will be described below. The following steps of FIGS. 30 to 34 substantially correspond to the steps of FIGS. 24 to 28 in the seventh embodiment.

After the step of FIG. 23, a film having a high etching selectivity with respect to the oxide film, for example, a SiN film 115 of 50 nm is deposited on the entire surface with a uniform thickness, and then an insulating film 116 of about 300 nm (for example, BPSG or plasma SiO ₂ ) etc. is deposited on the entire surface. Subsequently, the insulating film 116 is anisotropically etched in the vertical direction by the RIE method using a resist mask having a hole pattern to form a groove 117. At this time, the SiN film 115 is used as an etching stopper. Subsequently, wet etching using the SiN film 115 as a stopper is performed, and the insulating film 116 is isotropically etched in the lateral direction by about 20 nm. Subsequently, using the patterned insulating film 116 as a mask, the SiN film 115 left at the bottom of the trench is removed by etching using the RIE method. Thus, by isotropically etching the insulating film 116, the width of the groove 117 is expanded (the width L2 is wider than the width L1 in the seventh embodiment (FIG. 24)), and the bottom area of the capacitor is increased ( FIG. 30).

Next, for example, tungsten nitride (W / N), ruthenium (Ru), or ruthenium oxide (RuO _x ) of about 200 nm is deposited as a storage node electrode material 118 by a sputtering method so as to fill the trench 117 (FIG. 31).

  Next, the storage node electrode material 118 is polished and planarized by CMP to the upper surface of the insulating film 116 to form a storage node electrode (FIG. 32).

  Next, the insulating film 116 is completely removed by wet etching so that the side surface of the storage node electrode 118 is exposed. At this time, since the SiN film 115 acts as a wet etching stopper, the insulating film 113 is not etched. The exposed SiN film 115 selectively covers a region where the storage node electrode 118 is not formed with a uniform thickness (FIG. 33).

  Next, as the capacitor dielectric film 119, for example, barium strontium titanate (BSTO) is deposited by CVD or sputtering. Subsequently, as the plate electrode 120, for example, a tungsten nitride film, ruthenium film or ruthenium oxide film with a thickness of about 100 nm is deposited and planarized by CMP to form a capacitor (FIG. 34).

  Thereafter, a DRAM is completed by forming wirings and the like using a normal method.

  In the eighth embodiment, the same effect as in the seventh embodiment can be obtained, and the bottom area of the groove can be increased, so that the capacitance of the capacitor can be increased.

  The present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit of the present invention.

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Explanation of symbols

DESCRIPTION OF SYMBOLS 11,101 ... Semiconductor substrate, 23, 32, 33, 34, 35 ... 2nd insulating film, 25 ... 1st conductor film, 26 ... 1st hole, 27 ... 1st insulating film, 28 ... 1st 2 conductor film, 29a, 29b ... second hole, 30a, 30b ... third conductor film, 109 ... third insulating film (sixth insulating film), 110 ... second contact, 111 ... Bit line, 113 ... third insulating film (seventh insulating film), 114 ... first contact, 115 ... fourth insulating film, 116 ... eighth insulating film, 118 ... fourth conductor film, 119: fifth insulating film, 120: fifth conductor film

Claims (11)

A memory device comprising a first conductor film, a first insulating film formed on the first conductor film, and a second conductor film formed on the first insulating film. In the semiconductor memory device in which the capacitor is formed on the main surface side of the semiconductor substrate,
The capacitor is formed in a first recess of a second insulating film, a second recess is formed in the second insulating film, and a second recess is formed in the first recess and the second recess. 3 conductor film is embedded, and the third conductor film embedded in the first recess is provided to cover the second conductor film over the entire surface . The distance between the upper surface of the third conductor film embedded in one recess and the upper surface of the semiconductor substrate is the distance between the upper surface of the third conductor film embedded in the second recess and the upper surface of the semiconductor substrate. A semiconductor memory device characterized by being approximately equal to a distance. A memory device comprising a first conductor film, a first insulating film formed on the first conductor film, and a second conductor film formed on the first insulating film. In the semiconductor memory device in which the capacitor is formed on the main surface side of the semiconductor substrate,
The capacitor is formed in a first recess of a second insulating film, a second recess is formed in the second insulating film, and a second recess is formed in the first recess and the second recess. 3 conductor film is embedded, and the third conductor film embedded in the first recess is provided to cover the second conductor film over the entire surface . The distance between the upper surface of the second conductor film of the capacitor formed in one recess and the upper surface of the semiconductor substrate is the upper surface of the third conductor film embedded in the second recess and the upper surface of the semiconductor substrate. A semiconductor memory device, wherein the distance is equal to or less than the distance from the upper surface. A memory device comprising a first conductor film, a first insulating film formed on the first conductor film, and a second conductor film formed on the first insulating film. In the method of manufacturing a semiconductor memory device in which the capacitor is formed on the main surface side of the semiconductor substrate,
Forming a second insulating film having a first recess and the first conductor film provided in the first recess; forming a second recess in the second insulating film; The first conductor film, the first insulating film, and the second conductor film are formed in the first recess and the second recess at the same time , and the second in the first recess. And a step of covering the entire surface of the conductive film and embedding a third conductive film. A memory device comprising a first conductor film, a first insulating film formed on the first conductor film, and a second conductor film formed on the first insulating film. In the method of manufacturing a semiconductor memory device in which the capacitor is formed on the main surface side of the semiconductor substrate,
Forming a second insulating film; selectively removing the second insulating film; and burying the first conductor film in a portion where the second insulating film is selectively removed. A step of selectively removing the second insulating film to form a first recess for projecting the first conductor film; and a second recess in the second insulating film. Forming the first conductor film, the first insulating film, and the second conductor film in the first recess and the second recess at the same time ; and A method of manufacturing a semiconductor memory device, comprising the step of covering the entire surface of the second conductor film in the recess and embedding a third conductor film.   After the step of forming the second insulating film having the first recess and the first conductor film provided in the first recess, the first insulating film and the second conductor film are formed. Forming a second recess in the second insulating film by selectively removing the second conductive film, the first insulating film, and the second insulating film; After forming the third conductor film, the first conductor film, the second conductor film, and the first insulating film are removed by a predetermined thickness by removing the third conductor film, the second conductor film, and the first insulating film, And burying the third conductor film in the first recess and the second recess formed with the first insulating film and the second conductor film at the same time. A method for manufacturing a semiconductor memory device according to claim 3. A semiconductor substrate;
A storage electrode formed on the bottom surface of the recess of the insulating layer; a capacitor insulating film formed on the storage electrode; and a plate electrode formed on the capacitor insulating film and formed below the upper edge of the recess. A plurality of multilayer capacitors formed on the semiconductor substrate, and a plate wiring layer that covers the entire surface of the plate electrode and is embedded in the recess and connected to the plate electrode. A memory cell portion formed on a semiconductor substrate;
A peripheral circuit portion formed on the semiconductor substrate adjacent to the memory cell portion and provided with a wiring layer;
The semiconductor memory device is characterized in that the wiring layer has an upper surface substantially the same height as the upper surface of the plate wiring layer. A semiconductor substrate;
A storage electrode formed on the bottom surface of the recess of the insulating layer; a capacitor insulating film formed on the storage electrode; and a plate electrode formed on the capacitor insulating film and formed below the upper edge of the recess. A plurality of multilayer capacitors formed on the semiconductor substrate, and a plate wiring layer that covers the entire surface of the plate electrode and is embedded in the recess and connected to the plate electrode. A memory cell portion formed on a semiconductor substrate;
A peripheral circuit portion formed on the semiconductor substrate adjacent to the memory cell portion and provided with a wiring layer;
And the plate wiring layer and the wiring layer are formed of the same material, and the upper surface of the plate wiring layer is substantially the same height as the upper surface of the wiring layer. apparatus. A semiconductor substrate;
A transistor formed on the semiconductor substrate and having a gate, a source region, and a drain region;
A first insulating layer, a second insulating layer, and a third insulating layer having recesses on the surface, which are sequentially stacked;
A first contact plug formed in the first insulating layer and connected to one of the source region and the drain region of the transistor;
A bit line formed on the first insulating layer and connected to one of the source region and the drain region of the transistor via the first contact plug;
A second contact plug formed in the first insulating layer and connected to the other of the source region and the drain region of the transistor;
A third contact plug formed in the second insulating layer and connected to the second contact plug;
A storage electrode formed on the second insulating layer and electrically connected to the other of the source region and the drain region of the transistor via the third and second contact plugs; and a capacitor insulating film And a capacitor having a plate electrode;
A plate wiring layer embedded in the concave portion of the third insulating layer and entirely covering the plate electrode ;
A wiring layer formed in the peripheral circuit region;
And the plate wiring layer and the wiring layer are formed of the same material, and the upper surface of the plate wiring layer is substantially the same height as the upper surface of the wiring layer. apparatus.   9. The semiconductor memory device according to claim 6, wherein an upper surface of the plate electrode of the capacitor is formed lower than an upper surface of the plate wiring layer. An interlayer insulating film laminated in a plurality of layers on the semiconductor substrate;
A bit line in the interlayer insulating film laminated in a plurality of layers;
9. The semiconductor memory device according to claim 6, wherein the bit line is formed at a position lower than the storage electrode.   The semiconductor memory device according to claim 6, wherein the plate wiring layer includes a portion that is formed so as to fill the recess and is connected to the plate electrode.

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