JP3697926B2 - Manufacturing method of semiconductor device - Google Patents
Manufacturing method of semiconductor device Download PDFInfo
- Publication number
- JP3697926B2 JP3697926B2 JP05881999A JP5881999A JP3697926B2 JP 3697926 B2 JP3697926 B2 JP 3697926B2 JP 05881999 A JP05881999 A JP 05881999A JP 5881999 A JP5881999 A JP 5881999A JP 3697926 B2 JP3697926 B2 JP 3697926B2
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- JP
- Japan
- Prior art keywords
- semiconductor chip
- semiconductor
- pad
- chip
- manufacturing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000004065 semiconductor Substances 0.000 title claims description 49
- 238000004519 manufacturing process Methods 0.000 title claims description 9
- 229910000679 solder Inorganic materials 0.000 claims description 10
- 238000007747 plating Methods 0.000 claims description 6
- 235000012431 wafers Nutrition 0.000 claims description 6
- 238000010030 laminating Methods 0.000 claims 1
- 238000000034 method Methods 0.000 description 5
- 239000000463 material Substances 0.000 description 3
- 239000004020 conductor Substances 0.000 description 2
- 238000002844 melting Methods 0.000 description 2
- 230000008018 melting Effects 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 229910001111 Fine metal Inorganic materials 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
Landscapes
- Wire Bonding (AREA)
Description
【０００１】
【発明の属する技術分野】
本発明は、複数個の半導体チップを積層した、より高い機能を有する半導体装置の製造方法に関する。
【０００２】
【従来の技術】
昨今の急速な半導体技術の進歩により、半導体チップの高性能化とチップサイズの小型化が図られてきた。しかしながら、チップ自体の小型化によりそれをパッケージ化し実装するのが困難となってきており、また実装コストの大幅な増加の原因にもなっている。
【０００３】
さらに、半導体装置に複合的な高い機能が要求されるようになり、複数の半導体装置を組み込んだシステムが要求され、結果的に基板上に半導体の占める面積が大きくなってきている。この課題を解決すべく３次元構造を持った半導体チップ・パッケージのアイデアがすでに多数検討されている。例えば、特開平５−６３１３７号や特開平６−２９１２５０号（特許番号第２６０５９６８号）や特開平８−２６４７１２号や特開平１０−１６３４１１号などである。これらに共通する基本構造を図３に示す。半導体チップ１−１、１−２、１−３を重ねあわせ、スルーホール４に形成された導電体物質を介して電気的接続を得るものである。
【０００４】
【発明が解決しようとする課題】
本発明は、図４に示したような３次元構造を容易に実現させるべく創作されたものであり、小型で実装面積が少なくかつ多機能である３次元構造の半導体チップを得ることを目的とする。
【０００５】
【課題を解決するための手段】
請求項１の半導体装置の製造方法は、電気信号取り出し用の配線および電極パッドを形成した第１の半導体チップと、前記第１の半導体チップと同じ位置に電気信号取り出し用の配線および電極パッドを形成した第２の半導体チップを積層する半導体装置の製造方法において、チップに切断する前のウェハーの状態で前記電極パッドにスルーホールを形成し、複数の前記ウェハーを積層したのち半田めっきを施したワイヤーをスルーホールに通し、一括してリフローにより前記半田めっきを溶融させて電気的接合部を形成し、前記ウェハーをチップサイズにダイシングすることを特徴とする。
【０００７】
【発明の実施の形態】
以下、本発明を実施の形態に基づき、詳細に説明する。
【０００８】
＜実施の形態１＞
図２は、実施の形態１により作成された半導体装置の構造を示した断面図である。半導体チップ１−１、１−２、１−３がパッド３−１、３−２、３−３に開けられたスルーホール内に挿入された金属ワイヤー４−１により、互いに電気的に接続されている。
【０００９】
次に、本発明の製造方法を、図１に基づいて詳細に述べる。
【００１０】
図１−ａに示したように、半導体チップ１−１上に、電気的接続をとるためのパッド３−１が形成してある。パッド部のサイズは１００ミクロン角である。このパッドの中央に直径８０ミクロンの大きさのスルーホール２−１を作成する。スルーホールの開口方法は、レーザーで開ける方法やシリコンを異方性エッチングで開けておく方法などがある。なお、パッドの材質は通常Ａｌが一般的だが、ここではＡｌ上にバリヤ層としてＴｉ／ＴｉＮ層を形成した上に、Ｃｕが形成してあるパッドを使用した。
【００１１】
次に、図１−ｂに示したように、スルーホールを形成した半導体チップ１−１、１−２、１−３を位置合わせしながら重ねあわせ、次に、図１−ｃに示したように、表面に１０μｍの半田めっきを施した直径７０μｍのＡｕ細線ワイヤー４−１を用意しておき、これをスルーホールに貫通させた。
【００１２】
この状態でリフロー炉で半田を溶解せしめることにより、半導体チップ１−１、１−２、１−３をスルーホールを介して電気的に接続することができた。
【００１３】
＜実施の形態２＞
図３は、実施の形態２により作成された半導体装置の構成を示した図である。第１の半導体チップ１−１の上に第２の半導体チップ１−２が積層されている。それぞれのチップ上にはパッド３が複数個形成されており、半導体チップ１−１に形成されたパッド群５はワイヤーボンディングするためのパッドである。またチップ１−２上に形成されたパッド群７もワイヤーボンディングするためのパッドである。ここで、パッド３に中央に半田めっきを施した金属ワイヤー４を形成してあるパッド群６により、上下のチップの電気的接続を取っている。
【００１４】
次に、実施の形態２の製造方法を、図３に基づいて詳細に述べる。
【００１５】
図３に示したように、半導体チップ１−１上に、電気的接続をとるためのパッド３がすでに形成してある。このパッド３が複数個形成され、パッド群５とパッド群６が形成されている。このパッド部のサイズは１００ミクロン角である。このうちのパッド群６についてのみ、中央に直径８０ミクロンの大きさのスルーホールを作成する。スルーホールの開口方法は、レーザーで開ける方法をもちいた。なお、パッドの材質は通常Ａｌが一般的だが、ここではＡｌ上にＡｕが形成してあるパッドを使用した。
【００１６】
次に、同様に、半導体チップ１−２上にも、電気的接続をとるためのパッド３が形成してある。このパッド３が複数個形成され、パッド群６とパッド群７が形成されている。このパッド部のサイズは１００ミクロン角である。このうちのパッド群６についてのみ、中央に直径８０ミクロンの大きさのスルーホールを作成する。形成方法は先ほどと同じである。またパッド群６については、チップ１−１と１−２を積層した際に、スルーホールが貫通するように正確にアライメントできるように形成されている。スルーホールを形成した半導体チップ１−１、１−２を位置合わせしながら重ねあわせ、次に、表面に１０μｍの半田めっきを施した直径７０μｍのＡｕ細線ワイヤー４を用意しておき、これをスルーホールに貫通させた。
【００１７】
この状態でリフロー炉で半田を溶解せしめることにより、半導体チップ１−１、１−２をスルーホールを介して電気的に接続できた。
【００１８】
【発明の効果】
本発明により、図４に記したような３次元構造を容易に実現することができ、小型で実装面積の少なく、かつ多機能である３次元構造の半導体チップ、例えば第１のチップとしてマイコンチップと第２のチップとしてメモリーを組み合わせることにより、従来より小型で多機能な半導体チップのような半導体装置を得ることができた。
【図面の簡単な説明】
【図１】本発明の製造方法を示した図。
【図２】実施の形態１により形成した半導体チップの断面図。
【図３】実施の形態２により作成した半導体チップの平面図。
【図４】一般的な半導体チップを積層した３次元構造の断面図。
【符号の説明】
１−１．第１の半導体チップ
１−２．第２の半導体チップ
１−３．第３の半導体チップ
２．スルーホール
３−１．第１の半導体チップの電極パッド
３−２．第２の半導体チップの電極パッド
３−３．第３の半導体チップの電極パッド
４−１．表面に半田めっきを施した金属細線ワイヤー
４−２．導電性材料
５．第１の半導体チップのパッド群
６．第１の半導体チップと第２の半導体チップを接続するためのパッド群
７．第２の半導体チップのパッド群[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for manufacturing a semiconductor device having a higher function in which a plurality of semiconductor chips are stacked.
[0002]
[Prior art]
Recent rapid advances in semiconductor technology have led to higher performance of semiconductor chips and smaller chip sizes. However, due to the miniaturization of the chip itself, it has become difficult to package and mount it, and this also causes a significant increase in mounting cost.
[0003]
Furthermore, a complex high function is required for a semiconductor device, and a system incorporating a plurality of semiconductor devices is required. As a result, the area occupied by the semiconductor on the substrate is increasing. In order to solve this problem, many ideas of a semiconductor chip package having a three-dimensional structure have already been studied. Examples thereof include JP-A-5-63137, JP-A-6-291250 (Japanese Patent No. 2605968), JP-A-8-264712, and JP-A-10-163411. The basic structure common to these is shown in FIG. The semiconductor chips 1-1, 1-2, and 1-3 are overlapped to obtain electrical connection via a conductor material formed in the through hole 4.
[0004]
[Problems to be solved by the invention]
The present invention was created in order to easily realize the three-dimensional structure as shown in FIG. 4, and an object thereof is to obtain a three-dimensional semiconductor chip having a small size, a small mounting area, and a multi-function. To do.
[0005]
[Means for Solving the Problems]
According to a first aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: a first semiconductor chip on which an electric signal extraction wiring and an electrode pad are formed; In the method of manufacturing a semiconductor device in which the formed second semiconductor chips are stacked, through holes are formed in the electrode pads in a wafer state before being cut into chips, and a plurality of the wafers are stacked, and then solder plating is performed. A wire is passed through a through-hole, and the solder plating is melted by reflow at a time to form an electrical joint, and the wafer is diced to a chip size.
[0007]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, the present invention will be described in detail based on embodiments.
[0008]
<
FIG. 2 is a cross-sectional view showing the structure of the semiconductor device fabricated according to the first embodiment. The semiconductor chips 1-1, 1-2, 1-3 are electrically connected to each other by metal wires 4-1 inserted into through holes opened in the pads 3-1, 3-2, 3-3. ing.
[0009]
Next, the manufacturing method of the present invention will be described in detail with reference to FIG.
[0010]
As shown in FIG. 1A, a pad 3-1 for electrical connection is formed on the semiconductor chip 1-1. The size of the pad portion is 100 micron square. A through hole 2-1 having a diameter of 80 microns is formed in the center of the pad. As a method for opening a through hole, there are a method of opening with a laser and a method of opening silicon with anisotropic etching. The material of the pad is usually Al, but here, a pad on which a Ti / TiN layer is formed as a barrier layer on Al and Cu is formed is used.
[0011]
Next, as shown in FIG. 1B, the semiconductor chips 1-1, 1-2, and 1-3 in which the through holes are formed are overlaid while being aligned, and then as shown in FIG. 1C. In addition, a 70 μm diameter Au fine wire 4-1 having a surface plated with 10 μm solder was prepared, and this was passed through the through hole.
[0012]
In this state, the semiconductor chips 1-1, 1-2, and 1-3 could be electrically connected through the through holes by melting the solder in a reflow furnace.
[0013]
<
FIG. 3 is a diagram showing a configuration of the semiconductor device created according to the second embodiment. A second semiconductor chip 1-2 is stacked on the first semiconductor chip 1-1. A plurality of pads 3 are formed on each chip, and a
[0014]
Next, the manufacturing method of
[0015]
As shown in FIG. 3, pads 3 for electrical connection have already been formed on the semiconductor chip 1-1. A plurality of pads 3 are formed, and a
[0016]
Next, similarly, a pad 3 for electrical connection is formed on the semiconductor chip 1-2. A plurality of pads 3 are formed, and a
[0017]
In this state, the semiconductor chips 1-1 and 1-2 could be electrically connected through the through holes by melting the solder in a reflow furnace.
[0018]
【The invention's effect】
According to the present invention, a three-dimensional structure as shown in FIG. 4 can be easily realized, a small-sized, small mounting area, and multifunctional three-dimensional structure semiconductor chip, for example, a microcomputer chip as a first chip By combining a memory as the second chip, it was possible to obtain a semiconductor device such as a semiconductor chip that was smaller and multifunctional than before.
[Brief description of the drawings]
FIG. 1 is a view showing a manufacturing method of the present invention.
2 is a cross-sectional view of a semiconductor chip formed according to
3 is a plan view of a semiconductor chip created according to
FIG. 4 is a cross-sectional view of a three-dimensional structure in which general semiconductor chips are stacked.
[Explanation of symbols]
1-1. First semiconductor chip 1-2. Second semiconductor chip 1-3.
Claims (1)
チップに切断する前のウェハーの状態で前記電極パッドにスルーホールを形成し、複数の前記ウェハーを積層したのち半田めっきを施したワイヤーをスルーホールに通し、一括してリフローにより前記半田めっきを溶融させて電気的接合部を形成し、前記ウェハーをチップサイズにダイシングすることを特徴とする半導体装置の製造方法。 The semiconductor stacking a first semiconductor chip having a wiring and the electrode pad for electrical signal taken out, the first second semiconductor chip having a wiring and the electrode pad for electrical signal taken out to the semiconductor chip in the same position In the device manufacturing method,
Forming a through hole to the electrode pad in a state before the wafer is cut into chips, through a wire subjected to solder plating After laminating a plurality of the wafers in the through-holes, melt the solder plating by reflow collectively A method of manufacturing a semiconductor device, comprising: forming an electrical joint portion and dicing the wafer into a chip size.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP05881999A JP3697926B2 (en) | 1999-03-05 | 1999-03-05 | Manufacturing method of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP05881999A JP3697926B2 (en) | 1999-03-05 | 1999-03-05 | Manufacturing method of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2000260933A JP2000260933A (en) | 2000-09-22 |
| JP3697926B2 true JP3697926B2 (en) | 2005-09-21 |
Family
ID=13095245
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP05881999A Expired - Fee Related JP3697926B2 (en) | 1999-03-05 | 1999-03-05 | Manufacturing method of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3697926B2 (en) |
Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100435813B1 (en) | 2001-12-06 | 2004-06-12 | 삼성전자주식회사 | Multi chip package using metal bar and manufacturing method thereof |
| KR100817718B1 (en) | 2006-12-27 | 2008-03-27 | 동부일렉트로닉스 주식회사 | Semiconductor device manufacturing method |
| JP5212118B2 (en) | 2009-01-05 | 2013-06-19 | 日立金属株式会社 | Semiconductor device and manufacturing method thereof |
| KR101069288B1 (en) | 2009-08-10 | 2011-10-05 | 주식회사 하이닉스반도체 | Semiconductor package |
| KR101078737B1 (en) | 2009-08-10 | 2011-11-02 | 주식회사 하이닉스반도체 | Stacked semiconductor package |
| EP2850654B1 (en) | 2012-05-17 | 2016-10-26 | Heptagon Micro Optics Pte. Ltd. | Assembly of wafer stacks |
| KR102315758B1 (en) * | 2014-09-09 | 2021-10-20 | 센주긴조쿠고교 가부시키가이샤 | Cu COLUMN, Cu NUCLEAR COLUMN, SOLDER JOINT, AND THROUGH-SILICON VIA |
-
1999
- 1999-03-05 JP JP05881999A patent/JP3697926B2/en not_active Expired - Fee Related
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| Publication number | Publication date |
|---|---|
| JP2000260933A (en) | 2000-09-22 |
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