JP3610979B2 - Liquid crystal display device and display system - Google Patents

Description

  The present invention relates to a liquid crystal display device, a driving method thereof, and a display system.

  An example of a conventional liquid crystal display device is disclosed in JP-A-6-222741. FIG. 2 is an example of a circuit diagram of a data driver of the liquid crystal display device. In general, there are an analog method and a digital method as a data driver method for writing an image signal to a liquid crystal display device. Among these, the analog method is not suitable for a display such as a portable computer because the power consumption of the circuit is large. On the other hand, although the digital method consumes less power, there is a problem that the number of external power supplies increases because the output voltage needs to be supplied from the outside. Although there is a system that incorporates a D / A converter and minimizes the number of external power supplies, in general, the output voltage of the D / A converter is linear and is different from the γ characteristics of liquid crystals, so it is suitable for gradation display Not. Therefore, a device is devised in which a voltage between input voltages is complemented and output, and a certain amount of γ correction is performed while reducing the number of external input power supplies.

  For example, in the example of FIG. 2, nine levels of voltage can be supplied from the outside, and a total of 64 levels of output voltage can be output. V1, V2. . . V9 is nine power supply voltages given from the outside. The upper 3-bit image signal 21 is converted into 8-level data by the decoder 23, and two adjacent power supplies are selected from the nine power supply voltages by the power supply selection circuits 24 and 25. The lower 3-bit image signal 22 is converted into 8-level data by the decoder 24, and one of the two selected voltage levels divided into eight by the resistance division type D / A converter 26 is selected and output. Let In this method, if the nine power supply voltages input from the outside are optimized according to the γ characteristics of the liquid crystal, a certain amount of γ correction is possible.

  However, the conventional TFT circuit has the following problems. That is, the voltage output after interpolation is different from the voltage that should be displayed, which will be described below with reference to the drawings. FIG. 3 is a diagram showing the relationship between the applied voltage and the transmittance of the liquid crystal display device. The transmittance dependency of the actual liquid crystal display device draws a curve like a broken line 31. In the data driver circuit of FIG. 2, nine input power supply voltages V1, V2,. . . Since the output voltage is interpolated using V9, the transmittance dependency of the broken line as shown in 32 is assumed. FIG. 4 is an enlarged view of a part of FIG. 3. For example, the output voltages Va, Vb, Vc, Vd, Ve, Vf, Vg are liquid crystal by dividing the two input voltages V1 and V2 into eight equal parts. When applied to the display device, the gray scale display corresponding to the display device is whitened like Ta, Tb, Tc, Td, Te, Tf, Tg.

  The liquid crystal display device, the driving method thereof, and the display system of the present invention solve such problems, and an object thereof is to realize a high-quality liquid crystal display device.

  The liquid crystal display device of the present invention includes a data conversion circuit for converting n-bit digital input video data to n + m bits and an n + m-bit digital data driver. Further, the driving method of the liquid crystal display device according to the present invention sequentially converts an n-bit digital input signal into n + m-bit digital data in accordance with the γ characteristics of the liquid crystal, and uses an n + m-bit digital data driver for n bits. It is characterized by performing gradation display.

  In the liquid crystal display device of the present invention, a data driver for driving a signal line includes a CMOS static shift register, a level shifter, and a D / A converter, and a scan driver for driving a scan line includes a CMOS static shift register, a level shifter, and a buffer. The shift register in the data driver, the shift register in the scan driver, and the input video signal input unit of the D / A converter are connected to a common power source, and the voltage of the common power source is the D / A converter and the buffer. It is characterized by being smaller than the power supply voltage of the circuit. Further, the driving method of the liquid crystal display device of the present invention includes a D / A converter in the data driver, and uses the same amplitude signal as the input video signal of the D / A converter and the timing signal of the shift register. The power supply level for the D / A converter is alternately switched for each field, and an AC voltage is applied to the liquid crystal. Alternatively, the data driver has a plurality of D / A converters, and the power level for the D / A converter is alternately switched every horizontal scanning period, an AC voltage is applied to the liquid crystal, and the adjacent signal lines are connected. Is characterized in that a video signal of reverse polarity is always applied. Alternatively, the data driver has a plurality of D / A converters, and the power level for the D / A converter is alternately switched every horizontal scanning period, an AC voltage is applied to the liquid crystal, and the adjacent signal lines are connected. Is characterized in that a video signal of reverse polarity is always applied. Alternatively, the power supply level for the D / A converter is alternately switched for each field, the potential of the common electrode is also alternately switched for each field, and an AC voltage is applied to the liquid crystal. Alternatively, the power supply level for the D / A converter is alternately switched every horizontal scanning period, the potential of the common electrode is also alternately switched every horizontal scanning period, and an AC voltage is applied to the liquid crystal. Alternatively, the power supply level for the D / A converter is alternately switched for each field, and the scanning signal is made up of a 4-level potential signal. Switching between the case where the potential is maintained and the case where the potential below the non-selection potential is maintained for each field, and an AC voltage is applied to the liquid crystal. Alternatively, the power supply level for the D / A converter is alternately switched every horizontal scanning period, and the scanning signal is composed of a 4-level potential signal. Switching between maintaining a potential higher than the potential and maintaining a potential lower than the non-selected potential is performed every horizontal scanning period, and an AC voltage is applied to the liquid crystal.

The liquid crystal display device of the present invention is a liquid crystal display device that performs image display using a plurality of pixels, and includes a data driver that supplies image signal data to each pixel through a signal line, and the data driver includes a shift register and The delay circuit includes a latch, a D / A converter, and a delay circuit, wherein the delay circuit delays the timing of the image signal data in accordance with a delay time in the shift register and in the latch.
The data driver may further include a data conversion circuit that converts n-bit digital input image data into n + m-bit digital image data in accordance with γ characteristics of the liquid crystal display device, and the data driver may be an n + m-bit driver. .
The delay circuit includes a delay time detection circuit that detects a delay time of the shift register and the latch, and a delay time compensation circuit that delays image signal data by a time detected by the delay time detection circuit. You may do it.
In addition, a pixel thin film transistor provided corresponding to an intersection of a scanning line and the signal line is provided, the data driver includes a data driver thin film transistor, and the scanning driver for supplying a selection signal through the scanning line is a scanning driver. The pixel thin film transistor, the data driver thin film transistor, and the scan driver thin film transistor may be a polysilicon thin film transistor formed on the same substrate.
The liquid crystal display device driving method of the present invention includes a step of inputting an image signal for image display, a step of delaying the image signal data, a clock signal input to a shift register, and a plurality of signal lines. Shifting the selection pulse for controlling the timing of supplying the image signal data; and latching the image signal data based on the selection pulse, and the delay time of the step of delaying the image signal includes: The time is determined according to the delay time from the clock signal to the output signal of the latch.
And a step of detecting a delay time from the clock signal to the output signal of the latch, and a step of compensating the delay time by feeding back the detected delay time to a circuit for delaying the image signal data. It may be.

A display system according to the present invention includes a data driver that supplies image signal data to each pixel through a signal line in a liquid crystal display device that displays an image using a plurality of pixels, and the data driver includes a shift register and a latch. And a D / A converter and a delay circuit, the delay circuit delays the timing of the image signal data according to the delay time in the shift register and in the latch, and further converts n-bit digital input image data. A liquid crystal display device having a data conversion circuit for converting into n + m bit digital image data in accordance with the γ characteristic of the liquid crystal display device, wherein the data driver is an n + m bit driver; LCD panel and A that converts analog image signal to n-bit digital data Comprising D and converter, and a timing controller for controlling the operation timing, and displaying an image corresponding to the input video signal.
The sum of the delay time of the A / D converter, the delay time of the data conversion circuit, and the delay time of the delay circuit may be equal to the sum of the delay times inside the shift register and the latch.

  Since the liquid crystal display device of the present invention includes a data conversion circuit for converting n-bit digital input video data into n + m bits and an n + m-bit digital data driver, it is possible to display an image in accordance with an arbitrary gradation display characteristic. is there. In addition, since a ROM in which a conversion table for correcting the γ characteristic of the liquid crystal is written in the data conversion circuit is used, γ correction can be performed for all points of the gradation display, so that an excellent gradation display performance is achieved. Can be obtained. In addition, since an n + m-bit D / A converter is incorporated, the number of external input power supplies is reduced, and the apparatus can be reduced in size, weight, and cost. In addition, since an active matrix liquid crystal display device using TFTs or nonlinear elements is used, a high contrast ratio can be obtained, and multi-gradation display and full color display can be achieved. Further, since the peripheral driver is integrally formed on the glass substrate using the polysilicon TFT circuit, the device can be further reduced in size and weight. Further, since a capacitively coupled D / A converter is used, power consumption can be reduced. In addition, since the D / A converters having the same capacitance are arranged in parallel, there is no variation in the capacitance ratio, and gradation display is possible with high accuracy. Further, since the constant current binary attenuation type D / A converter is used, a very large liquid crystal display device can be realized.

  The driving method of the liquid crystal display device of the present invention sequentially converts an n-bit digital input signal into n + m-bit digital data in accordance with the γ characteristics of the liquid crystal, so that accurate γ correction can be performed with a simple circuit, A high-quality display image can be obtained. In addition, after resetting all signal lines to the same potential within the blanking period of the horizontal scanning period, an n + m-bit D / A converted voltage is applied to each signal line. It can be eliminated and no afterimage is generated.

  In the liquid crystal display device of the present invention, the logic part is driven by a single low power supply voltage, and the voltage is lower than that of the D / A converter part or buffer part, so that it is difficult to generate noise on the display screen. Further, since the peripheral drive circuit is integrally formed using the polysilicon TFT, the power supply wiring can be made common and the resistance can be lowered, so that it is less likely to generate noise. In addition, since the capacitance-division type D / A converter is used, only the minimum necessary current flows, so that it becomes more difficult to generate noise. In addition, since the level shifter in which the input portion is connected to the two n-channel and p-channel transistors connected in parallel is used, the current flowing through the level shifter can be suppressed, and noise is less likely to be generated.

  In the method for driving the liquid crystal display device of the present invention, the power level of the D / A converter is alternately switched for each field, so that current consumption is small and noise is hardly generated. In addition, since non-inverted data is used in the capacitive division type D / A converter, an image signal inversion circuit is not required, current consumption is reduced, and noise can be reduced.

  The liquid crystal display device driving method of the present invention uses a plurality of series of D / A converters to alternately switch the power supply level for each field and applies a video signal having a reverse polarity to adjacent signal lines. Flicker and lateral crosstalk do not occur. In addition, since non-inverted data is used in the capacitive division type D / A converter, an image signal inversion circuit is not required, current consumption is reduced, and noise can be reduced.

  In the driving method of the liquid crystal display device of the present invention, the power level is alternately switched for each horizontal scanning period using a plurality of series D / A converters, and a video signal having a reverse polarity is applied to adjacent pixels in the vertical and horizontal directions. Low power consumption and no flicker or up / down / left / right crosstalk. In addition, since non-inverted data is used in the capacitive division type D / A converter, an image signal inversion circuit is not required, current consumption is reduced, and noise can be reduced.

  According to the liquid crystal display driving method of the present invention, the power supply level of the D / A converter is alternately switched for each field, and the common electrode potential is also alternately switched with the reverse polarity, so that the power supply voltage range for the D / A converter is reduced. Can do. In addition, since non-inverted data is used in the capacitive division type D / A converter, an image signal inversion circuit is not required, current consumption is reduced, and noise can be reduced.

  In the driving method of the liquid crystal display device of the present invention, the power supply level of the D / A converter is alternately switched every horizontal scanning period, and the common electrode potential is also alternately switched with the reverse polarity, so the power supply voltage range for the D / A converter is reduced. It is possible to prevent flicker and vertical crosstalk. In addition, since non-inverted data is used in the capacitive division type D / A converter, an image signal inversion circuit is not required, current consumption is reduced, and noise can be reduced.

  According to the driving method of the liquid crystal display device of the present invention, the power level of the D / A converter is alternately switched for each field, and the scanning line signal in the non-selection period is also alternately switched with the reverse polarity. The current consumption can be reduced and noise is hardly generated. In addition, since non-inverted data is used in the capacitive division type D / A converter, an image signal inversion circuit is not required, current consumption is reduced, and noise can be reduced.

  According to the liquid crystal display driving method of the present invention, the power level of the D / A converter is alternately switched every horizontal scanning period, and the scanning line signal in the non-selection period is also alternately switched with the reverse polarity. The voltage range can be reduced, current consumption is small, noise is less likely to occur, and vertical crosstalk is less likely to occur. In addition, since non-inverted data is used in the capacitive division type D / A converter, an image signal inversion circuit is not required, current consumption is reduced, and noise can be reduced.

  Since the liquid crystal display device of the present invention includes a circuit that delays the video signal in accordance with the delay time inside the driver, the display screen does not shift even if the drive voltage of the driver is lowered. In addition, since the delay time detection circuit and the delay time compensation circuit are provided inside the driver, the display screen does not shift even if there are variations in the manufacturing conditions of the driver or changes in the usage environment. Further, since the peripheral driver is integrally formed on the glass substrate using the polysilicon TFT circuit, the device can be reduced in size and weight.

  According to the driving method of the liquid crystal display device of the present invention, since the video signal is delayed by estimating the delay time inside the driver, the display screen does not shift even when driver circuits having various performances are used under various conditions. In addition, since the delay time inside the driver is detected and self-corrected by the delay time compensation circuit, the display screen will not shift even if there are variations in driver manufacturing conditions or changes in the usage environment. Even if the driver is configured with a large circuit, it can be driven with a simple external circuit.

  In the display system of the present invention, an analog video signal is D / A converted into an n-bit digital signal, converted into data by a γ correction circuit, and driven by an n + m bit D / A converter built-in driver, so that excellent gradation display is achieved. Reproducible and easy to make full color. For example, a multimedia-compatible high-quality display system can be easily realized. Further, since the signal amplitude of the logic unit is set to the same low voltage, the power consumption is low and the system can be used for a long time even with a small battery. Further, since the video signal is delayed in accordance with the delay time inside the driver, the screen does not shift even when driven at a low voltage. Therefore, the power consumption can be further reduced and the influence of noise is less likely. Further, since a peripheral driver integrated liquid crystal display device using a polysilicon TFT circuit is used, the size and weight of the system can be reduced.

  The liquid crystal display device of the present invention will be described below with reference to the drawings.

  FIG. 1 is an example of a circuit diagram of the liquid crystal display device of this embodiment. Here, a liquid crystal display device using a thin film transistor (hereinafter abbreviated as TFT) will be described. In the active matrix portion 1 that performs image display, signal lines 4 and scanning lines 5 are arranged in a matrix, and pixel TFTs 6, holding capacitors 7, and liquid crystal capacitors 8 are connected to the intersections. The scanning driver unit 3 that supplies a selection pulse to the scanning line 4 includes a shift register 9 and a level shifter 10. In many cases, the output section of the level shifter 10 is provided with a buffer circuit. The data driver unit 2 that supplies an image signal to the signal line 4 writes the data stored in the latch 12 and the latch 12 that simultaneously fetches data from the n + m-bit digital image signal 17 in accordance with the shift register 11 and its output timing. The latch 13 includes a D / A converter 14 that converts n + m-bit digital image data stored in the latch 13 into an analog signal. When the two-stage latch is provided in this way, the D / A converter can be operated with the data stored in the other latch 13 even during the period in which data is rewritten in the first-stage latch 12. A sufficient time can be secured for driving the signal line 4.

  The n-bit digital image signal data 16 is converted into n + m-bit digital image signal data by a data conversion circuit. Here, a γ correction ROM 15 is used as the data conversion circuit. If the γ characteristic of the liquid crystal is actually measured and the ROM address is converted into n + m bit data for converting the address of the input image signal into the desired γ characteristic for the output, the data can be easily and sequentially converted. For example, the ROM can be replaced even when using different liquid crystal materials. Of course, data conversion may be performed by another circuit, but preferably a ROM in which a γ correction table is written should be used.

  Although a digital data driver incorporating a D / A converter is used here, a full digital driver, a PWM output driver, or the like may be used. However, here, the γ correction is performed by converting the image data from n bits to n + m bits, so the output after the data conversion may be linear. If linear output is acceptable, a D / A converter built-in system that can accommodate various screen sizes with a relatively simple circuit configuration and a small number of input power supplies is desirable.

  Although an active matrix type liquid crystal display device has been described here, the present invention can be used for all liquid crystal display devices including a simple matrix. However, in the simple matrix method, the voltage ratio between the selection unit and the non-selection unit decreases as the number of scanning lines increases, so that it is difficult in principle to achieve multi-gradation display. Therefore, it is desirable to use an active matrix liquid crystal display device in order to realize high image quality by multi-gradation display.

  Next, how the present invention performs gamma correction will be described with reference to FIG. Here, it is assumed that 6-bit digital image signal data is converted into 8-bit digital image signal data based on the γ correction table. In the figure, the white circles indicate the voltage that can be output by the 8-bit D / A converter and the transmittance of the liquid crystal display device in that case, and the black circles indicate the 6-bit data output based on the γ correction table. 6-bit data selected from the bit data, the corresponding output voltage, and the transmittance of the liquid crystal display device are shown.

  In general, when 6-bit data is converted to 8-bit data, conversion data is selected at a ratio of 1 out of 4 pieces of all 8-bit data. Here, however, transmission with respect to the applied voltage of the liquid crystal display device is selected. The voltage difference selected according to the rate dependency is changed. For example, in a region where the transmittance dependency on the applied voltage of the liquid crystal display device is steep, one of three is selected at a ratio of one or two, and in a gentle region, a ratio of one is selected for five or more. Is done. As a result, the transmittance of gradation display is changed to Ta, Tb, Tc,. . . As shown by Tg, the intervals can be substantially equal. Of course, the transmittance can be set at an equal ratio interval, and an arbitrary γ characteristic can be obtained as required. For example, it is also possible to perform gradation display centering on a slightly brighter one with emphasis on the brightness of the screen. If a plurality of γ correction table ROMs are provided, the display can be switched to a different γ characteristic depending on the purpose of use.

  Here, γ correction is performed by adding 2 bits. However, if the number of bits to be added is increased to 3 bits and 4 bits, strict γ correction can be performed accordingly. However, if the number of bits is too large, the D / A converter circuit becomes complicated. Therefore, it is desirable to add 2 to 3 bits for practical use. A method such as frame rate control can also be used to increase the number of gradation display bits. For example, by adding a frame rate control for 2 bits to a driver with a built-in 6-bit D / A converter to enable gradation display with a linear voltage for a total of 8 bits, the γ correction table is set as described above. It is also possible to perform display for 6 bits.

In FIG. 1, the active matrix portion, the scan driver portion, and the data driver portion are shown separately, but this is usually used by mounting an external LSI chip on the active matrix liquid crystal panel for the driver circuit. Because.
In order to reduce the outer dimensions and reduce the cost of the device, it is desirable to integrally form these driver circuits on the active matrix substrate using TFTs. As an element that can realize this, there is a polysilicon TFT circuit formed on a glass substrate. A method for forming this polysilicon TFT circuit will be described below.

FIG. 16 is a cross-sectional view of a polysilicon TFT in each process when a driver part is formed by a CMOS self-aligned TFT circuit and an active matrix part is formed by an LDD type TFT circuit. First, as shown in FIG. 2A, after depositing an insulating film for preventing diffusion of impurities from the substrate on the glass substrate, a polysilicon thin film 72 is deposited. It is necessary to improve the crystallinity of the polysilicon thin film 72 in order to increase the field effect mobility. Therefore, the polysilicon thin film is recrystallized using laser annealing or solid phase growth, or the amorphous silicon thin film is crystallized into polysilicon. After this polysilicon thin film 72 is patterned into an island shape, a gate insulating film 73 is deposited. Next, as shown in FIG. 6B, after forming the gate electrode 74, the portion that becomes the N-channel TFT is covered with the mask material 75, and boron ions are doped at a high concentration to form the source / drain portions of the P-channel TFT. To do. Next, as shown in FIG. 2C, the mask material is removed and the entire surface is doped with phosphorus ions at a low concentration. Further, as shown in FIG. 4D, the portion to become the P-channel TFT and the LDD portion of the pixel TFT are covered again with a mask material, and phosphorus ions are doped at a high concentration. Thus, the TFT of the pixel portion is made of an N-type high-resistance polysilicon thin film (n ⁻ poly-Si) between the source / drain electrodes made of an N-type low-resistance polysilicon thin film (n ⁺ poly-Si) and the channel portion. An LDD region is formed. As a result, the off current of the pixel TFT can be suppressed sufficiently low, and the occurrence of crosstalk in the active matrix portion can be prevented. Finally, as shown in FIG. 5E, an interlayer insulating film 76 is formed, wiring is formed with a metal thin film 77, a pixel electrode is formed with a transparent conductive film 79, and a passivation film 78 is formed. A driver-integrated active matrix substrate is completed. A liquid crystal display device is completed by subjecting this substrate to orientation treatment, and facing the opposite substrate, which has been subjected to orientation treatment in the same way, with a gap of several μm and encapsulating liquid crystal in the active matrix portion.

  The configuration of the D / A converter will now be described with a specific example. FIG. 6 is an example of a circuit diagram of an 8-bit data driver using a capacitive division type D / A converter. From the shift register 61, a timing pulse for fetching data for one signal line into a latch is output for each stage. With this output, eight digital latches A1, A2, A3. . . A8 includes data lines D1, D2, D3. . . Data of 8 bits is simultaneously taken from D8. LP is the second stage latch B1, B2, B3. . . Latch pulse terminal for controlling B8. SET is a set terminal for controlling the timing of sending data to the D / A converter, and RESET is a reset terminal for resetting data of the D / A converter. V0 is a common power source for the D / A converter, and COM is a power source for resetting the potential of the signal line. C0 is an equivalent capacity for one signal line. Point P corresponds to a signal line.

  The 8-bit D / A converter has eight capacitors C1, C2, C3. . . C8 and eight reset transistors Ta1, Ta2, Ta3. . . Ta8 and eight setting transistors Tb1, Tb2, Tb3. . . Tb8. Tc is a transistor that resets the potential of the signal line. Here, C1, C2, C3. . . The size of the eight capacitors of C8 is 1: 2: 4: 8: 16: 32: 64: 128. When the same voltage is applied after resetting the charges of all the capacitors, the amount of charges stored in these capacitors becomes equal to this ratio. On the other hand, since the capacitance of the signal line is constant, if the switch of any of these eight capacitors is closed and connected to the signal line, 256 combinations of the selected combinations can be applied to the signal line.

  Although it is difficult to apply a non-linear gradation voltage with this method, as described above, γ correction is performed when converting n-bit data into n + m-bit data, so that data using this D / A converter is used. Excellent gradation display characteristics can be obtained with a driver.

  This method requires very little power consumption of the D / A converter, and the circuit is very simple, so it is most suitable for a portable display. In order to perform highly accurate D / A conversion with this method, the capacity ratio must be accurate. However, in general, when this capacitance is formed using semiconductor technology or thin film technology, even if the pattern dimensions are slightly shifted, the value of the largest capacitance will immediately cause an error corresponding to the size of the smallest capacitance. End up. Therefore, it is desirable that the same number of capacitance patterns be connected in parallel by the number of capacitance ratios. For example, the capacity of the same pattern is 1, 2, 4,. . . It is connected in parallel with 128 pieces. In this method, even if the pattern is shifted slightly larger or slightly smaller, the capacitance ratio is kept constant.

  Next, an example using another type of D / A converter will be described. FIG. 8 shows an example of a data driver using a constant current binary attenuation type 8-bit D / A converter. This is a combination of eight constant current power supplies and eight sets of R and 2R type resistor networks. Since a constant current IR flows in all the constant current circuits, a circuit can be configured using the same transistor. Since this D / A converter includes a current source, it is not so limited by the capacity of the signal line serving as a load. Therefore, it can cope with a relatively small screen to a large screen. However, if the current supply capability is increased too much, power consumption increases.

  Although two types of D / A converters have been described above, the present invention can be applied to a data driver using any D / A converter, and different types of D / A converters can be used in combination. . Although the above description has been made based on an n-bit image signal, it goes without saying that 3 × n-bit data is converted to 3 × (n + m) bits when signals of three primary colors are input simultaneously. Will be converted. In addition, when the screen is divided into p to reduce the operating frequency of the data driver and p × n-bit data is simultaneously input, the p × n-bit data is converted into p × (n + m) -bit data. That's fine. Thus, the liquid crystal display device of the present invention can perform good γ correction on various input digital signals.

In this embodiment, a driving method of a liquid crystal display device will be described. In FIG. 1, an n-bit image signal 16 is sequentially converted into an n + m-bit image signal 17 by a γ correction ROM 15 and input to the data driver unit 2. Here, how to create a γ correction table stored in the γ correction ROM will be described. First, the transmittance of the liquid crystal display device is measured, and a graph of the dependency of the transmittance on the input voltage is prepared with the transmittance on the vertical axis and the input voltage on the horizontal axis. Next, 2 ^{n + m} voltage values that can be output by the D + A converter of n + m bits are plotted on the horizontal axis of the input voltage. Further, the transmittance of the target n-bit gradation display is plotted on the vertical axis, a horizontal parallel line is drawn from the point to the transmittance curve on the graph, and a perpendicular line is drawn from the intersection. The n + m-bit point closest to the intersection of the perpendicular and the horizontal axis is the data to be converted. For example, the points indicated by black circles in FIG. 5 are also obtained by this method. In this way, if n-bit data is made to correspond to the ROM address and the data stored therein is made into n + m-bit data obtained by the above method, it can be easily and sequentially converted by one ROM.

  Next, a method for driving the liquid crystal display device using the image signal sequentially converted by the γ correction table in this way will be described. FIG. 7 is an example of a timing chart of the driving voltage of the 8-bit digital data driver as shown in FIG. One horizontal scanning period is divided into a horizontal scanning selection period in which video signal data is sent and a horizontal blanking period in which video signal data is not sent. In the horizontal scanning selection period, 8-bit image signal data D1, D2, D3. . . When D8 is sequentially sent, the outputs SR1, SR2,. . . Are selected one by one. As a result, 8-bit data is sequentially taken into the first-stage latch. After all data has been written to the first stage latch, the set signal SET goes low during the horizontal blanking period, the D / A converter input is reset, the reset signal RESET goes high, and all signal lines are the same. It becomes a potential. During this time, the data written in the first-stage latch is written into the second-stage latch by the latch pulse LP. Then, the reset signal is again set to the low level to open the signal line, and then the set signal is set to the high level to connect the output of the D / A converter to the signal line. The set and reset timings can be set freely within the horizontal scanning period, but preferably the n + m-bit D / A conversion is performed after resetting the potentials of all signal lines to the same potential during the horizontal blanking period. The applied voltage should be applied to each signal line. This is because the signal line can always be driven during the horizontal scanning selection period, and a sufficient signal can be applied to the liquid crystal.

  In this embodiment, a liquid crystal display device capable of improving image quality by reducing noise will be described. In general, a digital driver having a multi-bit D / A converter easily captures various noises when performing analog conversion.

  FIG. 9 is a circuit diagram and a timing chart of a typical shift register circuit used for a digital data driver. In this circuit, the selection pulse can be shifted by a half cycle of the clock signal by using the clock signal that is 180 degrees out of phase. This circuit can transfer pulses in either the left or right direction. If R is set to high level and L is set to low level, the circuit is transferred to the right. Conversely, if R is set to low level and L is set to high level, the circuit is transferred to left. Can be shifted. The rise and fall timings of the clock signal of the shift register are just the same timing as the switching of the digital video signal for each dot. In order to minimize the influence of the clock signal and the digital data signal on the D / A converter, it should be driven with a voltage as low as possible. However, since a signal of about ± 5 V usually has to be applied to the liquid crystal, the power supply voltage of the D / A converter cannot be made very low.

  Therefore, the liquid crystal display device of this embodiment has the following configuration. First, the data driver includes a CMOS static shift register, a level shifter, and a D / A converter, and the scan driver includes a CMOS static shift register, a level shifter, and a buffer. These shift registers and latch circuits are connected to a common power source. Therefore, the clock signal, input signal, and digital image signal data of the shift register are all logic signals of the same power source. The level shifter boosts the control signal of each D / A converter as much as necessary, and similarly boosts the input signal of the buffer that drives the scanning line. In general, a CMOS static shift register is suitable for a driver of a portable liquid crystal display device because it can operate at a very high speed even with a low voltage and consumes little current. According to the above configuration, since all logic is operated by the same low voltage power supply, the interface is simple and noise is not easily generated. Furthermore, since a common power supply can be used, it is possible to make the wiring to the inside of the driver very low impedance, and there is almost no possibility that the power supply voltage fluctuates even if there is a portion where a large amount of current flows locally.

  The above configuration can be realized by connecting the data driver LSI and the scan driver LSI to the liquid crystal panel while keeping the contact resistance and wiring resistance of the mounting part sufficiently low, but in order to further enhance the effect, they are integrated on the same glass substrate. It is desirable to form. That is, if the driver part is formed integrally with the active matrix part using a polysilicon thin film transistor as shown in FIG. 16, the power source can be easily shared, and noise can be reduced by surrounding each logic part with a wide wiring.

  In the liquid crystal display device of this embodiment, various D / A converters can be used, but a D / A converter using a current source is likely to generate noise. It is desirable to use a D / A converter that allows a current to flow as much as possible. For example, the capacity division type D / A converter of FIG. 6 generates less noise because only the current for charging and discharging the charge flows through the capacitor.

  Further, in the present embodiment, it is desirable to use a level shifter that can shift the level at high speed and stably and generates little noise. FIG. 10 shows an example of a circuit diagram and a timing chart of a level shifter circuit suitable for the liquid crystal display device of this embodiment. When a waveform as indicated by IN in FIG. 5B is input, a waveform as indicated by OUT is output. That is, the output voltage is level-shifted from the VCC level to the VDD level. In this level shifter circuit, an input section is connected to two n-channel and p-channel transistors connected in parallel as shown in FIG. By doing so, the through current flowing in the middle of the level shifter input and the output switching can be kept low, and the switching speed is improved and the operation is stable. Of course, the current consumption is kept low, so there is little noise.

  In this embodiment, a driving method for improving the image quality of a liquid crystal display device using a D / A converter will be described. FIG. 11 is a timing chart showing a driving method of the liquid crystal display device. Since the liquid crystal needs to be AC driven, the video signal Vid is AC inverted every field symmetrically about a certain potential Vc. The scanning signal Vg becomes the selection level only for a period T1 once per field. This T1 corresponds to one horizontal scanning period. Note that in the TFT type liquid crystal display device, the potential of the pixel electrode is lower than the potential of the signal line by the amount of the extra voltage generated when the pixel TFT is turned off. Therefore, the common electrode potential Vcom on the counter substrate is less than the video signal center Vid. It is necessary to set it lower by an amount corresponding to the penetration voltage. In the present embodiment, the following method is used in order to cause an AC inversion output of a video signal with little noise for each field by a D / A converter.

  First, a signal having the same amplitude is used as the digital video signal input to the D / A converter and the timing signal of the shift register. Then, the power level of the D / A converter is alternately switched for each field, and an AC voltage is applied to the liquid crystal. That is, in the driving method of this embodiment, the analog output voltage range of the D / A converter to be applied to the signal line within a certain field period is limited, and the minimum voltage necessary for outputting the range is set. That's why. For example, when driving a liquid crystal in a voltage range of 6V ± 5V, the output range is 10V at maximum, but what is actually required is a field where a positive polarity signal is applied, and a field where a negative polarity signal is applied, about 8V to 11V. It is about 1V-4V. In other words, if the power supply of the D / A converter is minimized as long as an analog output of about 3 V is possible in each field, the current consumed by the D / A converter can be reduced, and noise generation is reduced.

  Further, as a more preferable driving method, there is the following method, that is, a method using a capacitively coupled D / A converter as shown in FIG. 6 and using a digital input signal whose black and white level is not inverted. In the case of the capacitive coupling method, the power source V0 for writing data can be alternately set on the positive side and the negative side with respect to the COM for the potential COM to be reset. In this case, since the gray level voltage to be D / A converted is also AC-inverted between the white level and the black level, it is not necessary to invert the data in black and white with an external circuit. Since a circuit that inverts data at high speed is not required, generation of noise can be suppressed, and the external circuit is simplified. Of course, current consumption is also low.

  The method described above is a method in which the video signal having the same polarity is written on the entire screen, so that the noise added to the video signal is minimized. However, in this method, if a sufficient storage capacity is not ensured, flicker is likely to occur due to a difference in penetration voltage based on the dielectric anisotropy of the liquid crystal. Further, if the wiring resistance of the scanning line or the capacitor line is not sufficiently lowered, the luminance unevenness in the left and right direction and the crosstalk in the left and right direction are likely to occur due to delay. As a driving method for avoiding these problems, there is a method described below.

  First, the D / A converter is divided into a plurality of systems, and the power source is also connected separately. A signal having the same amplitude is used as the digital video signal input to the D / A converter and the timing signal of the shift register. The power supply level of the D / A converter is switched alternately for each field, and an AC voltage is applied to the liquid crystal. The power supply voltage of the D / A converter connected to the odd-numbered signal lines and the signal lines of the even-numbered columns are connected. The power supply voltage of the D / A converter is alternately switched by shifting the phase by 180 degrees. That is, in this driving method, a video signal having a reverse polarity is always applied to adjacent signal lines. Accordingly, since there are the same number of pixels written with the positive polarity and those written with the negative polarity, the flicker becomes inconspicuous. In addition, since the charge applied to the pixels through the scanning lines and the capacitance lines is compensated to some extent between adjacent pixels, luminance unevenness in the left-right direction and left-right crosstalk are less likely to occur. Of course, even with this method, the power supply for the D / A converter is set to the minimum power supply voltage that can cover the required analog output range with positive polarity and negative polarity, respectively, resulting in low power consumption of the D / A converter. There is little noise to do. In this method, if the D / A converter does not have a black and white inversion function, a plurality of data wirings must be provided to input a positive signal and a negative signal separately.

  Therefore, as a more preferable driving method, there is the following method. That is, a method using a capacitively coupled D / A converter as shown in FIG. 6 and using a digital input signal whose black and white level is not inverted is used. As described above, in this method, since the D / A converter itself has a black and white inversion function, it is not necessary to arrange a plurality of data lines. Of course, since a circuit that inverts data at high speed is not required, generation of noise can be suppressed, an external circuit is simplified, and current consumption is small.

  Further, a driving method capable of avoiding crosstalk in the signal line direction will be described. First, the D / A converter is divided into a plurality of systems, and the power source is also connected separately. A signal having the same amplitude is used as the digital video signal input to the D / A converter and the timing signal of the shift register. Then, the power level of the D / A converter is alternately switched every horizontal scanning period, and an AC voltage is applied to the liquid crystal, but the power voltage of the D / A converter connected to the odd-numbered signal lines and the signal lines of the even-numbered columns are applied. The power supply voltage of the connected D / A converter is alternately switched with a phase difference of 180 degrees. That is, in this driving method, a video signal having a reverse polarity is always applied to the adjacent signal line, and the polarity is inverted in every horizontal scanning period. A signal having the opposite polarity is written. As a result, the flicker becomes inconspicuous, and the charge applied to the pixel through the scanning line and the capacitance line is compensated to some extent between the adjacent pixels, so that the luminance unevenness in the horizontal direction and the crosstalk in the horizontal direction are less likely to occur. Since the average potential is substantially constant regardless of the video signal, uneven luminance in the vertical direction and crosstalk in the vertical direction are less likely to occur. That is, this is a driving method that improves the uniformity of brightness in both the upper, lower, left, and right directions and suppresses crosstalk. Of course, even with this method, the power supply for the D / A converter is set to the minimum power supply voltage that can cover the required analog output range with positive polarity and negative polarity, respectively, resulting in low power consumption of the D / A converter. There is little noise to do. In this method, if the D / A converter does not have a black and white inversion function, a plurality of data wirings must be provided to input a positive signal and a negative signal separately.

  Therefore, as a more preferable driving method, there is the following method. That is, a method using a capacitively coupled D / A converter as shown in FIG. 6 and using a digital input signal whose black and white level is not inverted is used. As described above, in this method, since the D / A converter itself has a black and white inversion function, it is not necessary to arrange a plurality of data lines. Of course, since a circuit that inverts data at high speed is not required, generation of noise can be suppressed, an external circuit is simplified, and current consumption is small.

  In this embodiment, a second driving method for improving the image quality of a liquid crystal display device using a D / A converter will be described. In the driving method shown in FIG. 11, it is necessary to alternately move the power supply voltage of the D / A converter with a large amplitude. Here, a method for reducing the amplitude of this voltage will be described. FIG. 12 is a timing chart showing a driving method of the liquid crystal display device. Since the liquid crystal needs to be AC driven, the video signal Vid is AC inverted every field symmetrically about a certain potential Vc, and this Vc is also AC driven in reverse phase for each field. As a result, the voltage range of the video signal Vid is considerably narrower than that in FIG. Synchronously with this Vc, the common electrode potential Vcom on the counter substrate is also AC driven. Note that in the TFT type liquid crystal display device, the potential of the pixel electrode is lower than the potential of the signal line by the amount of the extra voltage generated when the pixel TFT is turned off, so the common electrode potential Vcom on the counter substrate is less than this from the video signal center Vid. It is necessary to set it lower by the amount of voltage that passes through. When the storage capacitor is connected to the storage capacitor method, that is, a dedicated capacitor line, the capacitor line may be driven with the same waveform as Vcom, but the storage capacitor is connected to the additional capacitor method, that is, the preceding scanning line. In this case, as shown in FIG. 12, the non-selection potential is translated in synchronization with Vcom. Also in this embodiment, in order to cause a video signal with less noise to be AC-inverted and output for each field by the D / A converter, a digital video signal input to the D / A converter and a signal having the same amplitude are used as the timing signal of the shift register. . Then, the power level of the D / A converter is alternately switched for each field, and an AC voltage is applied to the liquid crystal. In this method, since the analog output voltage range of the D / A converter to be applied to the signal line is positive and negative and does not have a large potential difference, the power supply for the D / A converter does not require a large amplitude.

  Further, as a more preferable driving method, there is the following method, that is, a method using a capacitively coupled D / A converter as shown in FIG. 6 and using a digital input signal whose black and white level is not inverted. This eliminates the need for a circuit that inverts data at a high speed, thereby suppressing the generation of noise, simplifying the external circuit, and reducing current consumption.

  Next, a driving method capable of avoiding crosstalk in the signal line direction also in this embodiment will be described. First, since the liquid crystal needs to be AC driven, the video signal Vid is AC inverted every horizontal scanning period symmetrically about a certain potential Vc, and this Vc is also AC driven in reverse phase every horizontal scanning period. Synchronously with this Vc, the common electrode potential Vcom on the counter substrate is also AC driven every horizontal scanning period. Note that in the TFT type liquid crystal display device, the potential of the pixel electrode is lower than the potential of the signal line by the amount of the extra voltage generated when the pixel TFT is turned off, so the common electrode potential Vcom on the counter substrate is less than this from the video signal center Vid. It is necessary to set it lower by the amount of voltage that passes through. When the storage capacitor is connected to the storage capacitor method, that is, a dedicated capacitor line, the capacitor line may be driven with the same waveform as Vcom, but the storage capacitor is connected to the additional capacitor method, that is, the preceding scanning line. In this case, the non-selection potential is translated in synchronization with Vcom. In this method, since a signal having a reverse polarity is applied to the signal line every horizontal scanning period, flicker becomes inconspicuous, and luminance unevenness and crosstalk in the vertical direction become inconspicuous.

  Furthermore, as a more preferable driving method, there is the following method. That is, a method using a capacitively coupled D / A converter as shown in FIG. 6 and using a digital input signal whose black and white level is not inverted is used. This eliminates the need for a circuit that inverts data at high speed, thereby suppressing the generation of noise, simplifying the external circuit, and reducing current consumption.

  In this embodiment, a third driving method for improving the image quality of a liquid crystal display device using a D / A converter will be described. In FIG. 12, since the common electrode of the counter substrate is AC driven, the power consumption is slightly increased. In this embodiment, a driving method in which the power supply voltage range for the D / A converter is narrow and power consumption is relatively small will be described. Note that this embodiment can be applied to an additional capacitance method, that is, when a storage capacitor is connected to the preceding scanning line. FIG. 13 is a timing chart showing a driving method of the liquid crystal display device. The video signal Vid uses the same signal as in FIG. 12, but the common electrode potential Vcom on the counter substrate remains constant. On the other hand, the scanning signal is made up of a signal having a potential of 4 levels, and immediately after the selection period, before switching from the selection potential to the non-selection potential, when maintaining the potential higher than the non-selection potential for a certain period and when maintaining the potential lower than the non-selection potential. Is switched for each field. For example, in FIG. 13, after the selection period T1, a potential different from the non-selection potential is applied for two horizontal scanning periods as T2, for example. In this figure, after T2, the potential of the storage capacitor is increased by V1 in the first field, and the potential is decreased by V2 in the second field, so that an AC voltage can be applied to the liquid crystal as in the case where the common electrode potential is AC driven. . Also in this embodiment, in order to cause a video signal with little noise to be AC-inverted and output for each field by the D / A converter, a digital video signal input to the D / A converter and a signal having the same amplitude are used as the timing signal of the shift register. . Then, the power level of the D / A converter is alternately switched for each field, and an AC voltage is applied to the liquid crystal. In this method, since the analog output voltage range of the D / A converter to be applied to the signal line is positive and negative and does not have a large potential difference, the power supply for the D / A converter does not need a large amplitude. Moreover, since the common electrode potential is constant, the power consumption of the liquid crystal display device is also smaller than in the case of FIG.

  Further, as a more preferable driving method, there is the following method, that is, a method using a capacitively coupled D / A converter as shown in FIG. 6 and using a digital input signal whose black and white level is not inverted. This eliminates the need for a circuit that inverts data at a high speed, thereby suppressing the generation of noise, simplifying the external circuit, and reducing current consumption.

  Next, a driving method capable of avoiding crosstalk in the signal line direction also in this embodiment will be described. First, since the liquid crystal needs to be AC driven, the video signal Vid is AC inverted every horizontal scanning period symmetrically about a certain potential Vc, and this Vc is also AC driven in reverse phase every horizontal scanning period. However, the common electrode remains constant. Then, a waveform that maintains the potential below the non-selection signal immediately after the selection period as in the selection signal waveform of the first field in FIG. 13, and a waveform that maintains a potential above the non-selection signal immediately after the selection period as in the second field. Are alternately repeated every horizontal scanning period. As a result, a signal having a reverse polarity is applied to the signal line every horizontal scanning period, so that the flicker becomes inconspicuous, and luminance unevenness and crosstalk in the vertical direction become inconspicuous.

  Furthermore, as a more preferable driving method, there is the following method. That is, a method using a capacitively coupled D / A converter as shown in FIG. 6 and using a digital input signal whose black and white level is not inverted is used. This eliminates the need for a circuit that inverts data at high speed, thereby suppressing the generation of noise, simplifying the external circuit, and reducing current consumption.

  In this embodiment, paying attention to the delay time inside the driver circuit of the liquid crystal display device, means for improving the image quality will be described. In general, in a liquid crystal display device using a digital data driver, it is desirable to drive at a low voltage in order to minimize the influence of noise on the display screen. On the other hand, due to the demand for higher definition of the screen, the operating speed of the driver has rather increased. For this reason, the original image may be displayed with a deviation from the delay time inside the driver. Alternatively, there is a problem that the voltage cannot be lowered so much to avoid it. In the liquid crystal display device of this embodiment, as shown in FIG. 14, a delay circuit 59 is provided in a portion where an image signal 59 is input to the data driver. On the other hand, in the data driver, the shift register 42 shifts the selection pulse of the latch 52 step by step by the clock signal 58. Here, when the voltage inside the driver is lowered, the time taken for the image signal is delayed due to the delay time inside the shift register and the delay time of the latch circuit. If the internal delay time of the driver is estimated or actually measured in advance and the image signal 56 is delayed by the delay circuit 59 by the delay time, the data can be taken in at the original timing. The configuration of the delay circuit may be any circuit as long as digital data is delayed by a necessary time. It may be a flip-flop, or just a multi-stage connection of inverters or the like. According to this method, since there is no fear that the display image is shifted, the voltage of the logic unit can be lowered, and the noise of the display screen is reduced.

  Furthermore, it is ideal that the delay time can be compensated for each driver. Therefore, as shown in FIG. 15, a delay time detection circuit 66 and a delay time compensation circuit 69 are provided in the data driver. Here, the delay time detection circuit is formed by a circuit having the same circuit configuration as that of one stage of the shift register 51 and the latch 52 or an element having the same size, and a circuit having the same delay time. A pulse is generated delayed by the delay time. The image signal 56 may be input from the delay time compensation circuit 69 using this pulse as a trigger. In this method, the display screen does not shift even if the delay time differs for each driver due to variations in the process conditions of the driver. Alternatively, even if the same liquid crystal display device is operated at a low temperature or a high temperature, there is no problem even if the delay time inside the driver is shifted.

  The liquid crystal display device of this embodiment can exhibit the effect most when the driver circuit is integrally formed on the active matrix substrate. As shown in FIG. 16, in the case of a liquid crystal display device in which a peripheral driver circuit is integrally formed using a CMOS type polysilicon TFT formed on a glass substrate, the mobility of the polysilicon TFT is several times that of single crystal silicon. Therefore, the delay time inside the driver is large. In addition, since it is a non-single crystal, variation between drivers is large due to variation in process conditions. Therefore, by using the image signal delay circuit, delay time detection circuit, and delay time compensation circuit of this embodiment, a high-quality driver built-in type liquid crystal display device can be realized.

  Next, a driving method of the liquid crystal display device of this embodiment will also be described. First, the case where the image signal delay circuit of FIG. 14 is used will be described. In general, since a luminance signal and a timing signal are simultaneously sent to the video signal data of the liquid crystal display device, the clock signal 58 and the image signal 56 can be easily formed by an external synchronization circuit. Of course, these two signals are synchronized and there is no timing shift. When this clock signal is used, the delay time in the shift register 51 and the delay time of the latch 52 are accurately estimated by simulation or actual measurement. The image signal 56 is delayed by using the image signal delay circuit 59 by the estimated delay time. As a result, the delay time of the image signal taken into the latch is synchronized with the delay time required for the operation of the shift register and the latch circuit. That is, since the image signal data can be captured at an ideal timing, the screen is not shifted.

  Similarly, the case of using FIG. 15 will be described. Again, the clock signal 58 and the image signal 56 formed by the external synchronization circuit are used. Of course, these two signals are synchronized and there is no timing shift. The delay time detection circuit 66 detects the delay time inside the shift register 51 and the delay time of the latch 52 when this clock signal is used. The delay time compensation circuit 69 is used to delay the image signal 56 by the detected delay time. As a result, the delay time of the image signal taken into the latch is synchronized with the delay time required for the operation of the shift register and the latch circuit. In this method, since the delay time shift is self-compensated, the image signal data is always captured at an ideal timing regardless of the driving condition, so that the screen shift does not occur.

  In this embodiment, a display system using a liquid crystal display device with a built-in D / A converter will be described. In FIG. 17, analog R, G, B video signals generated from an analog video signal generator such as a computer are converted into n-bit × 3 digital signals by a D / A converter. When a video device or the like is used as a signal source, it is converted into analog R, G, B video signals and input to a D / A converter. Of course, when the signal source generates a digital video signal, this D / A converter is not necessary. Next, the digital video signal of n bits × 3 is sequentially converted into a digital video signal of (n + m) × 3 bits by the γ correction ROM. The converted video signal is sent to the data driver. On the other hand, the timing controller generates drive signals for the A / D converter, the data driver, and the scan driver in synchronization with the signal of the analog video signal generation circuit. The data driver sequentially captures (n + m) × 3-bit video signals into the latch in synchronization with the clock signal received from the timing controller, and the signal lines of the active matrix portion via the (n + m) × 3-bit D / A converter Drive. This video signal is written to the pixel for each scanning line selected by the scanning driver, and the screen of the active matrix portion is displayed. In this display system, since γ correction is performed using a table written in the ROM, a complicated power source is unnecessary, and correction can be applied to all gradation signals, so that excellent color reproduction display is possible.

  When this embodiment is used as a portable system, it is necessary to suppress current consumption as much as possible. Therefore, preferably, the output signal of the A / D converter, the input / output signal of the γ correction ROM, the output signal of the timing controller, and the input signals of the data driver and the scan driver are made the same in voltage amplitude and driven with as low a voltage as possible. The necessary part is boosted with a level shifter. Further, if the power source for the D / A converter is also used at two levels and a positive signal is applied and a negative signal is applied, power consumption can be further reduced.

  When an image signal is written at high speed using a logic of a low voltage power supply, the display screen is likely to be shifted. Therefore, the delay time in the display system is more preferably optimized. That is, in FIG. 17, the delay time of the D / A converter and the γ correction ROM is made equal to the delay time until the video signal data is latched from the clock signal inside the data driver. If the delay time inside the data driver is too long, a delay circuit is provided in the digital video signal input section of the data driver, and the sum of the delay time of the delay circuit and the delay time of the A / D converter and the γ correction ROM is provided. Should be equal to the delay time inside the data driver.

  Further, if pursuing portability, it is desirable to use an active matrix type liquid crystal display device in which peripheral drive circuits are integrally formed. That is, a driver circuit is formed around the active matrix portion using a polysilicon TFT circuit formed on a glass substrate as shown in FIG. This makes it possible to reduce the size and weight of the system.

The circuit diagram of a liquid crystal display device. The circuit diagram of the conventional data driver with a built-in D / A converter. The figure which shows the input voltage dependence of the transmittance | permeability of a 9 power supply type liquid crystal display device. FIG. 10 is a diagram illustrating a part of the input voltage dependency of the transmittance of a nine-power-source liquid crystal display device. The figure which shows a part made from the input voltage dependence of the transmittance | permeability of a liquid crystal display device. FIG. 3 is a circuit diagram of a data driver with a built-in capacity division D / A converter. The timing chart of the operating voltage of an 8-bit data driver. The circuit diagram of the data driver with a built-in constant current binary attenuation type D / A converter. The circuit diagram and timing chart of a bidirectional shift register. Level shifter circuit diagram and timing chart. 4 is a timing chart illustrating an operation method of a liquid crystal display device. 4 is a timing chart illustrating an operation method of a liquid crystal display device. 4 is a timing chart illustrating an operation method of a liquid crystal display device. The circuit diagram of the data input part of a liquid crystal display device. The circuit diagram of the data input part of a liquid crystal display device. Sectional drawing which shows the manufacturing process of polysilicon TFT. 1 is a block diagram of a display system using a liquid crystal display device.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Active matrix part 2, 42 Data driver part 3 Scan driver part 4 Signal line 5 Scan line 6 Pixel TFT
7 Holding capacity 8 Liquid crystal capacity 9, 11, 51, 61 Shift register 10 Level shifter 12, 13, 52 Latch 14 D / A converter 15 γ correction ROM
16 n-bit image signal 17 n + m-bit image signal 21 upper 3 bit image signal 22 lower 3 bit image signal 23, 24 decoder 25 power supply selection circuit 26 resistance division type D / A converter 31 actual transmittance dependency 32 9 in power supply type Dependence on transmittance 56 Image signal 58 Clock signal 59 Image signal delay circuit 66 Delay time detection circuit 69 Delay time compensation circuit 71 Glass substrate 72 poly-Si thin film 73 Gate insulating film 74 Gate electrode 75 Mask material 76 Interlayer insulating film 77 Metal thin film 78 Passivation film 79 Transparent conductive film

Claims (5)

In a liquid crystal display device that displays an image using a plurality of pixels,
a data conversion circuit for converting n-bit digital input image data into n + m-bit digital image data in accordance with the γ characteristic of the liquid crystal display device;
A data driver for supplying image signal data to each pixel through a signal line;
The data driver is an n + m-bit driver and includes a shift register, a latch, a D / A converter, and a delay circuit.
The liquid crystal display device, wherein the delay circuit delays the timing of the image signal data according to delay times inside the shift register and inside the latch. The liquid crystal display device according to claim 1.
The delay circuit includes a delay time detection circuit that detects a delay time of the shift register and the latch;
A liquid crystal display device comprising: a delay time compensation circuit that delays image signal data by a time detected by the delay time detection circuit. The liquid crystal display device according to claim 1,
A thin film transistor for a pixel provided corresponding to an intersection of a scanning line and the signal line;
The data driver includes a data driver thin film transistor,
A scan driver for supplying a selection signal through the scan line includes a scan driver thin film transistor;
A liquid crystal display device, wherein the pixel thin film transistor, the data driver thin film transistor, and the scan driver thin film transistor are polysilicon thin film transistors formed on the same substrate. A liquid crystal display device according to claim 1;
An active matrix liquid crystal display panel;
An A / D converter that converts an analog image signal into n-bit digital data;
A timing controller for controlling the operation timing,
A display system for displaying video corresponding to an input video signal. The display system according to claim 4,
A display system, wherein a sum of a delay time of the A / D converter, a delay time of the data conversion circuit, and a delay time of the delay circuit is equal to a sum of delay times in the shift register and in the latch.

Images