JP3612510B2 - Preamplifier circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a preamplifier circuit , and more particularly to a transimpedance type preamplifier circuit .
[0002]
[Prior art]
An example of this type of conventional transimpedance type preamplifier circuit is disclosed in Japanese Patent Laid-Open No. 9-008563, and its circuit configuration is shown in FIG. In FIG. 4, an inverting amplifier 1 that amplifies and outputs a preamplifier input signal input from the input terminal 8, a buffer circuit 2 that buffers the signal output from the inverting amplifier 1 and outputs the signal to the output terminal 9, Feedback resistors 3 and 4 are connected in parallel between the input of the inverting amplifier 1 and the output of the buffer circuit 2 to determine the gain of the inverting amplifier 1.
[0003]
Further, a phase compensation capacitor 7 connected between the input and output of the inverting amplifier 1 for performing phase compensation of the inverting amplifier 1, and a feedback resistor 4 according to a gain switching signal input from the gain switching input terminal 11. The FET switch element 5 that controls on / off of the connection state to the inverting amplifier 1 and the buffer circuit 2 and the FET switch element 10 that similarly controls the connection state of the phase compensation capacitor 7 to the inverting amplifier 1 according to the gain switching signal are provided. doing.
[0004]
In the preamplifier circuit configured in this way, when the input signal from the input terminal 8 is at a low level, the gain switching signal is fixed at a low level, and thus the FET switch elements 5 and 10 are turned off. As a result, the feedback resistor for controlling the gain of the inverting amplifier 1 is only the resistor 3, and at the same time, the phase compensation capacitor 7 is opened and discharged. As a result, it is largely controlled by the gain of the preamplifier, and the phase compensation of the inverting amplifier 1 by the phase compensation capacitor 7 is not performed.
[0005]
On the other hand, when the input signal from the input terminal 8 is at a high level, the gain switching signal is at a high level, thereby controlling the FET switch elements 5 and 10 to be on. Therefore, the feedback resistor for controlling the gain of the inverting amplifier 1 is a parallel resistance of the resistors 3 and 4, and the gain of the inverting amplifier 1 is reduced as compared with the case where the input signal is at a low level. The phase compensation of the inverting amplifier 1 is performed by charging with the input signal.
[0006]
[Problems to be solved by the invention]
In the conventional preamplifier circuit shown in FIG. 4, charging of the phase compensation capacitor 7 is started when the gain switching signal transits from a low level to a high level. FIG. 5 is an example of an operation timing chart for explaining the situation at this time.
[0007]
As shown in FIG. 5, at the timing when the input signal at the input terminal 8 changes from a signal having a level smaller than a predetermined threshold level to a signal having a large level, and the gain switching signal is switched from low level to high level, the phase compensation capacitor 7 starts charging (refer to the voltage waveform at the node 40), but if the input of the small level signal continues for a long time, the discharge amount of the phase compensation capacitor 7 increases, and then the input signal becomes a signal of a high level. Thus, when the gain switching signal is switched to the high level, a large current is drawn into the inverting amplifier 1. As a result, a large amount of noise is applied to the preamplifier output signal, which has the disadvantage of adversely affecting a circuit (not shown) and the like at the subsequent stage.
[0008]
In order to solve such drawbacks, a preamplifier proposed by the applicant of the present application is presented in Japanese Patent Application No. 2000-140140. FIG. 6 shows the proposed circuit configuration, and the same parts as those in FIG. 4 are denoted by the same reference numerals. In this example, a reset FET switch element 20 is added in series to the phase compensation capacitor 7, and the FET switch element 20 is on / off controlled by a reset signal input from a reset input terminal 21.
[0009]
More specifically, this reset signal is always temporarily at a high level immediately before the input signal is supplied to the input terminal 8, and the FET switch element 20 is temporarily turned on. As a result, even when the gain switching signal is fixed at a low level, the phase compensation capacitor 7 is charged each time the input signal is supplied, and the discharge amount of the phase compensation capacitor 7 is reduced. It prevents it from growing.
[0010]
In the circuit of FIG. 6, the generation of noise shown in FIG. 5 is prevented, but since a reset signal is required, a reset signal generation circuit is required, which is not suitable for a device having no reset signal. .
[0011]
An object of the present invention is to provide a preamplifier circuit capable of suppressing noise very easily without requiring an additional circuit such as a reset signal generation circuit.
[0012]
[Means for Solving the Problems]
According to the present invention, an inverting amplifier for amplifying an input signal, a buffer for buffering the output of the inverting amplifier, and a first and a second provided in parallel between the output of the buffer and the input of the inverting amplifier. A feedback compensation resistor, a phase compensation capacitor for phase compensation of the inverting amplifier, a first switch connected in series with the second resistor to operate as a switch for gain switching with a gain switching signal as an input, A preamplifier circuit including a second switch connected in series to the phase compensation capacitor to operate as a switch for phase compensation switching with the gain switching signal as an input, and turned on and off by the gain switching signal and wherein a third switch controlled, to include a charging resistor connected in series with said third switch and the phase compensation capacitor That the preamplifier circuit is obtained.
[0015]
The third switch is turned on when the first and second switches are turned off to charge the phase compensation capacitor, and the third switch, The second switch is a switch element that is complementarily controlled on and off.
[0017]
The operation of the present invention will be described. According to the present invention, in a transimpedance type preamplifier circuit that controls gain switching to a smaller value by a gain switching signal when a large signal is input, a phase compensation capacitor is not required without requiring an extra control signal such as a reset signal. A charging circuit is added to eliminate the noise caused by the discharge of the capacitor. That is, since the phase compensation capacitor is discharged during a period when the input signal is at a low level (a period when the gain is controlled to be larger), the capacitor is charged during this period. Therefore, a switch element that is turned on to charge the phase compensation capacitor and a charging resistor are added during the period when the gain switching signal controls the gain to a large extent (low level period). It is.
[0018]
DETAILED DESCRIPTION OF THE INVENTION
An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a diagram showing a circuit configuration of an embodiment of the present invention, and the same parts as those in FIG. 4 are denoted by the same reference numerals. Describing the difference from FIG. 1, a resistor 31 and an FET switch element 30 are connected in series with the phase compensation capacitor 7. A series circuit of the resistor 31 and the FET switch element 30 is provided in parallel with the FET switch element 10. The on / off control of the FET switch element 30 is performed by a gain switching signal applied to the gain switching input terminal 11.
[0019]
The FET switch element 30 is a complementary conductivity type FET with respect to the other FET switch elements 5 and 10, and in this example, since the FETs 5 and 10 are N-channel MOSFETs, the FET 30 is constituted by a P-channel MOSFET. The The resistor 31 is selected to have a gain margin and a phase margin when the feedback amplifier is configured by combining the capacitor 7 and the inverting amplifier 1.
[0020]
The other configuration is the same as that of FIG. 4 and its description is omitted.
[0021]
FIG. 2 is an example of a timing chart showing the operation of the circuit of FIG. When the input signal level at the input terminal 8 is equal to or lower than a predetermined threshold level, the voltage at the gain switching input terminal 11 (gain switching signal) is at a low level. When the level is higher than the threshold level, the level is high. Therefore, when a signal having a level equal to or lower than the threshold value is input to the input terminal 8, the FET switch elements 5 and 10 are turned off and the FET switch element 30 is turned on. Therefore, the transimpedance gain of the preamplifier circuit is determined only by the feedback resistor 3. In this case, since the phase compensation capacitor 7 is charged via the resistor 31, the state where the electric charge is charged continues (refer to the voltage at the node 40 in FIG. 2).
[0022]
Thereafter, when a signal having a level greater than the threshold value is input to the input terminal 8, the FET switch elements 5 and 10 are turned on and the FET switch element 30 is turned off. Therefore, the transimpedance gain is determined by the parallel resistance of the feedback resistors 3 and 4. That is, the gain of the preamplifier circuit is smaller than that in the case where the input signal is at a level equal to or lower than the threshold value. Therefore, the preamplifier circuit is maintained in linearity without being saturated.
[0023]
At this time, the phase compensation capacitor 7 is charged through the FET switch element 10. However, since the capacitor 7 is in a charged state and the voltage at the node 40 does not decrease, the gain switching input terminal 11 Even when the voltage becomes high level, no large current is drawn into the inverting amplifier 1, and no noise is applied to the output terminal 9.
[0024]
FIG. 3 is a diagram showing a circuit configuration of another embodiment of the present invention, and the same parts as those in FIG. 1 are denoted by the same reference numerals. In the circuit of FIG. 1, a MOSFET having a conductivity type (complementary type) different from that of the other FET switch elements 5 and 10 is used as the FET switch element 30, but in the embodiment of FIG. The same conductivity type (N-channel type in this example) as the other FET switch elements 5 and 10 is used, and an inverter 33 is provided between the gate and the gain switching input terminal 11 for on / off control of the switch element 32. Is provided.
[0025]
By doing so, it is obvious that the FET switch element 32 and the other FET switch elements 5 and 10 can be complementarily turned on and off by the same gain switching signal.
[0026]
【The invention's effect】
As described above, according to the present invention, a special signal such as a reset signal is used during the period in which the gain is largely controlled, by controlling so as to prevent the phase compensation capacitor from being discharged. Even without this, it is possible to maintain and control the charging of the capacitor using the gain switching signal, and it is possible to suppress the generation of noise with a very simple configuration.
[Brief description of the drawings]
FIG. 1 is a circuit diagram of an embodiment of the present invention.
FIG. 2 is a timing chart showing the operation of the circuit of FIG.
FIG. 3 is a circuit diagram of another embodiment of the present invention.
FIG. 4 is a diagram illustrating an example of a conventional transimpedance type preamplifier circuit;
FIG. 5 is a timing chart showing the operation of the circuit of FIG.
FIG. 6 is a diagram showing a transimpedance type preamplifier circuit proposed by the applicant of the present application.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Inverting amplifier 2 Buffer circuit 3, 4 Feedback resistance 5, 10, 30, 32 FET switch element 7 Capacitor for phase compensation 8 Input terminal 9 Output terminal 11 Gain switching input terminal 31 Resistance

Claims (3)

An inverting amplifier for amplifying an input signal; a buffer for buffering the output of the inverting amplifier; first and second feedback resistors provided in parallel between the output of the buffer and the input of the inverting amplifier; A phase compensation capacitor for phase compensation of an inverting amplifier; a first switch connected in series to the second resistor to operate as a switch for gain switching with the gain switching signal as an input; and the gain switching signal. A preamplifier circuit including a second switch connected in series with the phase compensation capacitor to operate as a switch for phase compensation switching as an input,
A third switch that is on / off controlled by the gain switching signal;
A preamplifier circuit comprising: a charging resistor connected in series to the third switch and the phase compensation capacitor. The third switch, the first and second preamplifier of claim 1 wherein the switch is characterized by charging the phase compensation capacitor is turned on in the case of off. 3. The preamplifier circuit according to claim 2, wherein the third switch and the first and second switches are switch elements that are ON / OFF controlled complementarily.

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