JP3614306B2 - LSI layout method and recording medium storing LSI layout program - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor integrated circuit (LSI) layout method and a recording medium storing an LSI layout program, and more particularly to a clock path mounting design method in an LSI and the recording medium.
[0002]
[Prior art]
The LSI includes a large number of flip-flop cells and buffer cells for driving them. In general, tens of thousands of flip-flops are driven by a single buffer cell via a clock signal line. In such a layout of circuit elements and clock signal lines in an LSI, it is required to shorten the clock wiring length in order to increase the density, shorten the signal propagation delay time, and alleviate the congestion of the wiring. In addition, an optimum circuit element arrangement for suppressing a time difference (referred to as clock skew) with respect to a circuit element that requires a clock signal is required.
[0003]
FIG. 27 is a flowchart for explaining a conventional LSI layout method. As shown in the figure, the LSI layout includes a logic design stage S27, a clock layout stage S28, and a normal net wiring stage S29 other than the clock signal lines.
The logic design stage S27 includes a logic synthesis step S271 and a clock tree generation step S272.
[0004]
In step S271 of logic synthesis, the hardware description language (HDL) described in the register transfer level (RTL) of the elements constituting the LSI is synthesized into logic that can be laid out, and configured as a module. A first netlist (1) is created. In the clock tree generation step S272, a clock tree before the introduction of the LSI buffer cells is created based on the first netlist (1).
[0005]
FIG. 28 is a diagram showing an example of a clock tree in the LSI module before introducing the buffer cell. In the figure, 281 is a module, 282 to 284 are small modules, 285 is a clock source which is a clock signal source, and 286 to 288 are flip-flop cells. At this stage, since the buffer cell has not been introduced yet, the clock source 285 is a circuit for directly driving the flip-flop cells 286 to 288.
[0006]
Next, buffering processing is performed on the first netlist (1) to introduce buffer cells into the clock tree, thereby creating the second netlist (2).
FIG. 29 is a diagram showing a clock tree in which buffer cells are introduced in an LSI module. As shown in the figure, buffer cells 291 to 296 are introduced into the clock tree of FIG. The number of buffer cells in each module is determined according to the number of flip-flop cells to be driven. In FIG. 29, since the number of flip-flop cells in the small modules 282 and 283 is small, the buffer cells are arranged so as to be driven by one buffer cell 292 and 293, respectively. Since the number of the pcells 288 is larger than the number of flip-flop cells in the other small modules, it is driven by the three buffer cells 295, 296, and 297 in a tree structure.
[0007]
Returning to FIG. 27, the contents of the second netlist (2) are transferred to the clock layout stage S28.
The clock layout stage S28 includes steps S281 to S287.
In step S281, a floor plan is acquired. The floor plan is layout information obtained from the LSI designer himself.
[0008]
In step S282, buffer cells and flip-flop cells are initially arranged as shown in FIG. 30 so that the clock wiring length is as short as possible based on the floor plan. FIG. 30 is a diagram showing an initial arrangement result of buffer cells and flip-flop cells in an LSI module. In the figure, the buffer cell 301 and the six flip-flop cells 310 to 315 driven by the buffer cell 301 are connected by a line to indicate that there is a connection relationship.
[0009]
In step S283, the clock buffer is bottom-up arranged. The bottom-up arrangement means that the flip-flop cells that are farthest from the clock source are arranged in order. This is because the buffer cells on the clock bus are bottomed up so that the distance between the buffer cell 301 and the flip-flop cells 310 to 315 driven thereby is as equal as possible based on the arrangement information of the flip-flop cells. It is processing to arrange in. The bottom-up technique includes a technique in which the buffer cell is arranged at the center of the arrangement range of the flip-flop cell driven by the buffer cell, and a technique in which the buffer cell is arranged at the center of gravity of the flip-flop cell driven by the buffer cell.
[0010]
FIG. 31 is a diagram showing an example in which the buffer cell 301 is arranged in the center of the arrangement range of the flip-flop cells 310 to 315 driven by the buffer cell 301 in the LSI module.
Next, in step S284, in order to limit the wiring length from the buffer to the flip-flop cell, a placement restriction region for the flip-flop cell is generated. This is a rhombus region centered on the buffer cell that drives the flip-flop cell. FIG. 32 is a diagram showing an example in which the placement restriction region 322 is set around the buffer cell 321. Next, rearrangement processing is performed in consideration of the arrangement restriction area 322. Here, the arrangement of the buffer cells 321 arranged bottom-up in step S283 is fixed, the arrangement restriction area 321 generated in step S284 is used as the arrangement restriction of flip-flop cells, and cells other than the clock buffer are rearranged. 33 and 34 are diagrams showing the result of rearranging the cells. As shown in the figure, the buffer cell 321 is arranged at the center of the arrangement restriction area 322, and the flip-flop cells 331 to 336 are arranged inside the arrangement restriction area 322.
[0011]
Next, in step S286, special routing of the clock tree final stage net is performed. Here, the three processes shown in FIGS. That is, FIG. 35 shows the setting of cluster bar information 351-357. FIG. 36 shows the wiring of the branch line 361 connecting each flip-flop cell and the cluster bar. FIG. 37 shows route wiring from the driving buffer cell 321 to the cluster bar.
[0012]
Next, special wiring of the inter-buffer net is performed. Here, as shown in FIG. 38, special wiring is provided in a star shape to the four buffer cells 382 to 385 driven by the buffer cell 381. After performing the processing from step S282 to step S287 described above, the clock tree is arranged and wired so as to suppress the signal propagation delay time value and the skew value from the clock source to the flip-flop cell, and then the normal net wiring Processing is in progress.
[0013]
[Problems to be solved by the invention]
The above-described conventional LSI layout method is a technique mainly used in ASIC (Application Specific Integrated Circuit) gate arrays and embedded arrays, and after logic design, the clock layout and LSI mounting are performed without changing the netlist. It is a method of designing. In this conventional method, the clock signal lines are laid out so as not to change the clock tree logic, but to comply with the restrictions imposed by the user's desired clock signal propagation delay time and skew value.
[0014]
However, in the logic design of step 271 and the clock tree generation stage of step 272, the logic design is performed without considering the arrangement position of the flip-flop cell and the wiring path of the clock signal line, so that the clock constraint condition is satisfied for the logic information. However, when the clock layout is performed, there is a problem that the wiring is congested and the clock wiring and the subsequent signal wiring cannot be performed.
[0015]
Details of the problem will be described below.
Since the clock tree generation in step 272 does not consider the floor plan and the arrangement of the flip-flops, as a result of arranging the buffer cells, the floor plan blocks 392 and 395 on the semiconductor chip 391 in FIG. In some cases, the buffer cell 396 or 397 drives a distant floor plan block such as 394, respectively. In this case, the length of the wirings 398 to 401 of the network (hereinafter referred to as the net) that drives the remote floor plan block becomes long, resulting in a problem that the clock signal propagation delay time becomes long and wiring congestion. There is a problem (first problem).
[0016]
In the rearrangement of the flip-flop cells in consideration of the arrangement restricted area in step S285 of FIG. 27, when the arrangement restricted areas 430 and 431 overlap as shown in FIG. 40, the result of the rearrangement of the flip-flop cells is as shown in FIG. In addition, there is a problem that flip-flop cells are concentrated in a common area of the two arrangement restriction areas 430 and 431, and as a result, wiring is congested (second problem). 40 and 41, 410 and 420 are buffer cells, 411 to 416 are flip-flops driven by the buffer cell 410, 421 to 426 are flip-flops driven by the buffer cell 420, and 430 and 431 are arrangement restriction regions. is there. FIG. 41 shows an example in which the flip-flop cells 411 to 416 are moved into the arrangement restriction area 430 and the flip-flop cells 421 to 426 are moved into the arrangement restriction area 431.
[0017]
In addition, by pulling the flip-flop cell from the initial arrangement position into the arrangement restriction region, the wiring length of the net other than the clock connected to the flip-flop cell is lengthened, and the wiring other than the clock is also congested. (Third problem). For example, the wiring becomes long like the wirings 441 to 445 in FIG.
[0018]
As shown in FIG. 38, the wiring between the buffer cells when a plurality of buffer cells are driven by a single buffer cell has a problem that the wiring from the buffer cell to the buffer cell is congested (first). Fourth problem). FIG. 38 shows a state in which the wiring between the buffer cell 381 and the buffer cells 382 and 383 is congested in a configuration in which a plurality of buffer cells 382 to 385 are driven by the buffer cell 381.
[0019]
As a problem other than wiring congestion, there is a problem of a skew value of signal propagation delay time (fifth problem). That is, in step S285 of FIG. 27, the rearrangement process is performed while limiting the arrangement of the flip-flop cells, the flip-flop cells are collected, and the skew value is suppressed. As in the flip-flop cell 371 shown in FIG. In some cases, the flip-flop cell is arranged away from the cluster. In this case, there is a problem that the signal propagation delay time to the cell becomes longer due to the longer wiring to the flip-flop cell, resulting in an increased skew.
[0020]
In the clock tree generation process in step S273 of FIG. 27, the buffer cells are arranged so as to satisfy the fan-out constraint of the buffer cells. As a result, the small module 282 or 283 and the large module 284 in FIG. There are portions where the number of buffer stages up to the flip-flop cell is different. In this case, there is a problem that the signal propagation delay differs between the two-stage and three-stage clock paths, and the skew variation becomes large (sixth problem).
[0021]
Further, in the initial arrangement of step S282 in FIG. 27, conventionally, as shown in FIG. 42, the flip-flop cells 421 to 424 are arranged without ignoring the clock paths 427 and 428 from the clock buffer cells 425 and 426. Therefore, there is also a problem that the wiring paths of the data paths 429 connecting the flip-flop cells intersect and are crowded. There is also a problem that the paths of the data path 429 and the clock paths 427 and 428 become long and cause a timing error (seventh problem).
[0022]
The first problem is that the layout information is not considered when generating the clock tree.
In addition, the second problem and the third problem are caused by the fact that the arrangement restriction areas overlap and that the driven cells are attracted and relocated in the overlapping arrangement restriction areas. .
[0023]
The fourth problem is that the wiring between the buffer cells from the driving buffer cell to each driven buffer is a simple star-shaped wiring.
The fifth problem is that the problem is that the flip-flop cell is simply rearranged in the arrangement restriction region.
[0024]
The sixth problem is that the path with different number of buffer stages has a large variation in clock skew.
The seventh problem is caused by the arrangement of flip-flop cells without ignoring the clock path during the initial arrangement.
In view of the above problems in the prior art, the object of the present invention is that the wiring length of the clock signal line and the other signal lines is short, the degree of wiring congestion is low, the signal propagation delay time is short, and the signal propagation delay An object of the present invention is to provide an LSI layout method for manufacturing an LSI with little variation in time and a recording medium storing an LSI layout program.
[0025]
[Means for Solving the Problems]
In order to achieve the above object, according to the method provided by the first aspect of the present invention, a floor plan is executed on a netlist after logically synthesizing an LSI design content described in RTL, Based on the obtained floor plan information, buffer cells that operate according to the clock signal are arranged, and the number of buffer stages is checked against the result of arranging the buffer cells once, and the number of buffer stages from the clock source to each flip-flop cell is equal. Adjustments are made so as to satisfy (Claim 1).
[0026]
As a result, the clock buffer cells are arranged in consideration of the floor plan information, so that it is not necessary to buffer the remote floor plan block, and as a result, the wiring length of the clock path can be suppressed. The clock signal propagation delay time can be suppressed. Further, since the number of buffer stages is adjusted, clock skew can be suppressed.
[0027]
According to the second aspect of the present invention, the initial placement step performs cell placement processing ignoring the net on the clock tree based on the net list and the floor plan information, and then connects to the clock tree. And determining the position of the flip-flop cell to be performed.
As a result, cells connected to other than the net of the clock signal line (referred to as clock net) and flip-flop cells are initially placed at optimal positions, and the clock net is reconfigured based on the placement results. It is possible to arrange cells that optimize the wiring efficiency of nets and other nets, and the subsequent wiring processing time is shortened. In addition, since the data bus path between the flip-flop cells is optimally arranged, the timing error after the cell layout can be suppressed.
[0028]
According to the third aspect of the present invention, after the step of adjusting the number of buffer stages, the final stage net of the clock tree is extracted from the initial arrangement of the flip-flop cells, the net range of the extracted final stage net is examined, Multiple nets with overlapping net ranges are merged, the merged nets are divided into nets with non-overlapping net ranges, and buffer cells are assigned to the divided nets so that the net ranges do not overlap (Step 3).
[0029]
As a result, the skew variation of the clock last stage net can be suppressed, and the wiring congestion can be reduced.
According to the fourth aspect of the present invention, the step of performing the clock layout includes the step of ignoring the net on the clock tree and the buffer cell on the clock tree based on the result of the placement of the flip-flop by the step of performing the cell placement process. Is determined bottom-up, and for each final stage buffer of the clock tree, cluster information of flip-flop cells is created from the arrangement information of the flip-flop cells driven by the buffers, and placement restriction area information is centered on each buffer cell. And then performing a rearrangement process on the cells other than the buffer cell using the rearrangement restricted area information and the cluster information as constraint values (claim 4).
[0030]
As a result, the flip-flop cells are arranged in the arrangement limited region and so that the flip-flop cells are clustered for each cluster group, so that the signal propagation delay time of the clock path can be shortened and the skew value can be suppressed. Therefore, it is possible to reduce the man-hours for timing adjustment after layout.
According to the fifth aspect of the present invention, after the step of performing the rearrangement process on the cells other than the buffer cell using the rearrangement restricted region information and the cluster information as constraint values, the placement position of the driven cell for each net of the clock tree Cluster information is created from each of the created clusters, cluster wiring is performed between the clustered driven cells, and wiring from the driving cell to each cluster is routed in a star shape. 5).
[0031]
Thereby, clock wiring with reduced clock skew is possible. It is also possible to reduce the wiring congestion degree of the net between the buffer cells.
According to the sixth aspect of the present invention, the step of reconfiguring the clock tree, comprising the step of reconfiguring the clock tree after the step of determining the placement processing of the buffer cells on the clock tree to be bottom-up, When the clock logic is changed, a logic change command is output to the netlist file, and the second netlist is changed based on the logic change command, thereby including a clock logic that matches the clock logic on the layout database. The method further comprises the step of creating a third netlist.
[0032]
As a result, the consistency between the logic on the layout database and the logic of the netlist can be maintained, so that formal verification or the like for guaranteeing the logic consistency after the logic change can be used.
According to a seventh aspect of the present invention, there is provided a recording medium storing a program for executing any one of the series of processes (claim 7).
[0033]
DETAILED DESCRIPTION OF THE INVENTION
Next, an embodiment of the present invention will be described.
FIG. 1 is a flowchart for explaining an outline of an embodiment of an LSI layout method according to the present invention. As in the conventional example shown in FIG. 27, in the embodiment of the present invention, the LSI layout includes a logic design stage S11, a clock layout stage S12, and a normal net wiring stage S13 other than the clock signal lines. .
[0034]
The logic design stage S11 includes a logic synthesis step S111, a step 112 using the floor plan introduced by the present invention, and a clock tree generation step S113.
In step S111 of logic synthesis, the hardware description language (HDL) described in the register transfer level (RTL) of the elements constituting the LSI is synthesized into logic that can be laid out in the same manner as in the past. A first netlist (1) having a plurality of modules each including a plurality of flip-flop cells is created.
[0035]
In the floor plan utilization step S112, the operator rearranges the modules on the first netlist (1) so as to shorten the wiring length according to the floor plan, and stores the result in the floor plan information file 10.
Next, in step S113, based on the floor plan information stored in the floor plan information file 10, the floor plan is considered and the buffer stage number from the cross source to the terminal flip-flop cell is adjusted to the maximum buffer stage number. Clock tree generation is performed to create the second netlist (2). The second netlist (2) includes modules (referred to as floor plan blocks) connected to the clock tree and buffer cells. The logic of the connection relation of the cells connected to the clock tree based on the second netlist (2) is stored in the database 267 (FIG. 26).
[0036]
Next, the second netlist (2) and the floor plan information are used in the clock layout step S12.
In the clock layout stage S12, first, in step S121, a clock path is extracted from the second netlist (2).
Next, in step S122, using the floor plan information and ignoring the clock path extracted in step S121, the initial arrangement of only the flip-flop cells connected to the data line is performed.
[0037]
Next, in step S123, bottom-up arrangement of buffer cells for inputting and outputting clock signals (hereinafter also referred to as clock buffer cells) is performed in the same manner as the conventional method shown in step S283 of FIG.
In step S124, a reconfiguration process of the clock tree final stage net, which will be described in detail later with reference to FIGS. 5 to 15, is performed.
[0038]
Next, in step S125, the clock buffer cells are arranged bottom-up once again, and in step S126, the arrangement restriction area of flip-flop cells (see FIG. 18) is generated from the arrangement of the buffer cells, and the generated arrangement restriction area is arranged. Output to the restricted area information file 12.
Next, in step S127, cluster information relating to the cluster of flip-flop cells is created (FIG. 19), and the created cluster information is output to the first cluster information file 14.
[0039]
In step S128, the previously created flip-flop placement restriction area information and cluster information are input to the computer and cells other than the buffer cells are rearranged (see FIG. 20).
Next, in step S129, based on the result of the rearrangement in step S128, cluster information is generated for the flip-flop cell and each buffer cell (see FIG. 21), and the generated cluster information is stored in the second cluster information file 16. Output.
[0040]
Next, in step S130, the contents of the second cluster information file are input to the computer, and clock net special wiring, that is, intra-cluster wiring (see FIG. 23) and route wiring (FIG. 24) are performed. By the processing so far, the arrangement processing of all the cells and the wiring of the clock path are completed.
Next, the remaining ordinary net is wired to complete the layout.
[0041]
Since the logic of the layout database has been changed by reconfiguring the clock tree last stage net in step S124, the second is determined based on the contents of the logic change command file 18 previously created in step S131. The third netlist (3) having a logic matching the logic on the database 267 is created by changing the contents of the netlist (2).
[0042]
FIG. 2 is a flowchart showing details of the processing content of step S113 in FIG.
In FIG. 2, the contents of the floor plan information file 10 are input to the computer in step S21, and buffering taking this floor plan information into consideration is performed on the first netlist (1) in step S22 (FIG. 3). reference).
[0043]
Next, in step S23, the maximum number of buffer stages among the number of buffer stages between the clock source and the terminal flip-flop in the largest module in the first netlist in which the buffer cells are arranged is checked. In step S24, the buffer cells are arranged so that the number of buffer cells on the clock path including the buffer stage number smaller than the maximum buffer stage number is equal to the maximum buffer stage number, and the buffer stage number adjustment processing is performed (see FIG. 4). . As a result, the signal propagation delay time from the clock source to all of the flip-flops at the end becomes equal, so that the skew can be suppressed.
[0044]
FIG. 3 shows a clock tree after buffering in consideration of floor plan information. 31 is a semiconductor chip, and 32-1 to 32-5 are modules driven by one buffer cell (floor). Each module includes a plurality of flip-flop cells (not shown in FIG. 3). Buffer cells 33-1 to 33-4 in each module are representative of buffer cells that drive flip-flop cells in the module. The approaching module is driven by a common clock buffer by buffering in step S22 in FIG. In FIG. 3, the buffer cell 34 is arranged so as to drive two approaching modules 32-1 and 32-2 in common, and the two approaching modules 33-3 and 33-4 are similarly connected. Buffer cells 35 are arranged to drive in common. As a result, the net 36 for driving the floor plan block is shortened as compared with the conventional example shown in FIG.
[0045]
FIG. 4 shows the adjustment result of the number of buffer stages in step S24 of FIG. 4, 41 is a large module, 42 to 44 are small modules, 45 is a clock source, 46 to 48 are flip-flop cells, and 49 to 55 are buffer cells. The buffer cell 50 is added by step S24. Thus, the number of buffer stages between the clock source 45 and the terminal flip-flop cell 46, the number of buffer stages between the clock source 45 and the terminal flip-flop cell 47, and the buffer between the clock source 45 and the terminal flip-flop cell 48 are obtained. The number of stages is equal, so the signal delay time between them is equal.
[0046]
FIG. 5 is a flowchart for explaining the details of step S124 in FIG. In FIG. 5, first, in step S51, the last net of the clock tree is extracted from the net list in which the clock buffer bottom-up arrangement is completed in step S123 in FIG. 1, and then the net of the net extracted in step S52. Examine the range. In step S53, a search is made for a net with overlapping net range areas. If there is no overlapping net, the process ends and the process proceeds to step S125 in FIG. If there are overlapping nets (see FIG. 6), the overlapping nets are merged in step S56 (see FIG. 8). In step S57, the merged net is divided so that the net ranges do not overlap (see FIG. 11). In step S58, a buffer cell is assigned to each of the divided nets (see FIG. 12). The buffer cells are temporarily arranged at the center of each net (see FIG. 14). This is called virtual placement of buffers. In step S60, the logic change information is output to the logic change command file 18 as a logic change command. Next, the process returns to the process of examining the net range in step S52 again, and the process is continued until there is no overlap of the net ranges.
[0047]
FIG. 6 is a diagram showing the net range of the final stage net when there are overlapping nets as determined in step S54 of FIG. In the figure, 61 indicates the range of the net driven by the buffer cell Buf1, and 62 indicates the range of the net driven by the buffer cell Buf2. The net ranges 61 and 62 have overlapping portions as shown in the figure. In the illustrated example, flip-flop cells 1 to 6 exist in the net range 61, and flip-flop cells 7 to 12 exist in the net range 62.
[0048]
FIG. 7 is a diagram showing the logic of the clock net in the net range shown in FIG. As shown in the figure, before reconfiguration of the clock tree, the flip-flop cells 1 to 6 are driven by the buffer cell Buf1, and the flip-flop cells 7 to 12 are driven by the buffer cell Buff2.
FIG. 8 is a diagram showing net merging in step S56 of FIG. As shown in the figure, the net ranges 61 and 62 shown in FIG. 6 are merged so that the flip-flop cells 1 to 12 and the buffer cells Buf 1 and Buf 2 are all contained in one net range 81.
[0049]
FIG. 9 is a diagram showing the logic of the clock net in the net range shown in FIG. As shown in the figure, after merging the net range, it is undefined which of the buffer cells driving the flip-flop cells 1 to 12 is Buf1 or Buf2.
10 and 11 are diagrams for explaining the net dividing process in step S57 of FIG. As shown in the figure, the merged net 81 in FIG. 8 is divided into nets 101 and 102 whose net ranges do not overlap. The net 101 includes flip-flops 1, 2, 3, 7, 8, and 9. The net 102 includes flip-flops 4, 5, 6, 10, 11, and 12. The net 101 is driven by the buffer cell Buf1. The net 102 is driven by the buffer cell Buf2.
[0050]
FIG. 12 is a diagram for explaining buffer allocation in step S58 of FIG. As shown, buffer cell Buf1 is assigned to drive net 101, and buffer cell Buf2 is assigned to drive net 102.
FIG. 13 is a diagram showing the logic of the clock net after allocating buffer cells as shown in FIG. As shown, the buffer cell Buf1 is connected to and drives the flip-flops 1, 2, 3, 7, 8, and 9 in the net 101, and the buffer cell Buf2 is flip-flops 4, 5, and 6 in the net 102. Connected to 10, 11, 12 to drive these. Note that a buffer cell that may change the logic of the clock tree in this way outputs a “0” in response to an input of “0” and a true system that outputs “1” in response to an input of “1”. Buffer cells.
FIG. 14 is a diagram showing a virtual arrangement of buffer cells in step S59 of FIG. As shown in the figure, the buffer cell Buf 1 is arranged at the center of the net 101 and the buffer cell Buf 2 is arranged at the center of the net 102.
[0051]
FIG. 15 is a diagram for explaining the arrangement restricted area generation in step S126 of FIG. As shown in the figure, a rhombic arrangement restriction region 151 in which as many flip-flop cells in the net 101 as possible are formed around the buffer cell Buf1 in the net 101 shown in FIG. 14, and similarly, the buffer cell Buf2 in the net 102 is formed. A rhombic arrangement restriction region 152 is formed in which as many flip-flop cells in the net 102 as possible enter. The size of the placement restriction area may be such that the distance from the center to the side is within the range of the route length defined in the design of the LSI to be designed. The information on the restricted area formed in this way is stored in the restricted area information file 12 (FIG. 1).
[0052]
FIG. 16 is a flowchart for explaining details of the rearrangement processing in step S128 of FIG. In FIG. 16, first, one final stage net of the clock tree is extracted in step S161.
Next, in step S162, the contents of the arrangement restricted area information file 12 (see FIG. 1) are read, and an arrangement restricted area (diamond area in FIG. 17) for the flip-flop cell is set.
[0053]
Next, in step S163, the first cluster information file 14 is read, and a virtual net is created between flip-flops grouped by cluster (see FIG. 18).
Next, in step S164, an inter-cell approach degree larger than the inter-cell approach degree in the normal net is set for the created virtual net information. In other words, the virtual net is confined within the arrangement restriction area.
[0054]
The processing from step S161 to step S164 is performed for all the last-stage nets of the clock tree, and when the processing for all the final-stage nets is completed, the rearrangement of the flip-flop cells is performed in step S167 with the arrangement restricted area and the inter-cell approach degree as constraints. The rearrangement process is terminated by executing the process.
FIG. 17 is a diagram showing the placement restriction area information of the flip-flop cell set in step S162 of FIG. In the figure, reference numeral 171 is a buffer cell, 172 is a number of flip-flop cells driven by the buffer cell 171, and 173 is an arrangement restriction area of the flip-flop cells. This arrangement restriction area is the same as that shown in FIG.
[0055]
FIG. 18 is a diagram showing the virtual net created in step S163 of FIG. As shown in the figure, the flip-flop cell 172 shown in FIG. 17 is grouped into a plurality of clusters CL1, CL2, CL3,... Based on the cluster information, and the virtual network is formed by virtually connecting the cells in each group. Is created.
FIG. 19 is a diagram showing the virtual net rearrangement process in step S167 of FIG. As illustrated, the clusters CL <b> 1 to CL <b> 6 are confined within the arrangement restriction region 173.
[0056]
FIG. 20 is a diagram showing second cluster information generated by further increasing the degree of proximity between cells in step S129 of FIG. 1 after the cluster rearrangement shown in FIG. As illustrated, the second cluster information is obtained by regenerating clusters CL1 to CL6 so that the wiring length between flip-flop cells in the rearranged clusters CL1 to CL6 shown in FIG. 19 is further shortened. It is done. This second cluster information is stored in the second cluster information file 16.
[0057]
FIG. 21 is a flowchart for explaining the details of the special wiring processing of the clock net in step S130 of FIG. In the figure, in step S211, one clock net is extracted, in step 212 the contents of the second cluster information file 16 are read, and in step 213, intra-cluster wiring is performed based on the input cluster information. In step 214, route wiring from the buffer cell to the cluster wiring is performed. In step 215, it is determined whether the processing has been completed for all the clock nets. If not completed, steps 211 to S214 are repeated for the next clock net in step 216. If all clock nets have been processed in step 215, the special wiring process is terminated.
[0058]
FIG. 22 is an explanatory diagram of the intra-cluster wiring process in step 213 of FIG. As shown in the figure, based on the second cluster information shown in FIG. 20, the clusters extending in the conventional lateral direction described in FIG. 35 inside each of the clusters CL1, CL2, CL3, CL4, CL5, and CL6. The wirings 221 to 226 are automatically provided without using a bar. At this stage, the buffer cell 227 is not wired.
[0059]
FIG. 23 is an explanatory diagram of the route wiring process in step S214 of FIG. As illustrated, the cluster wirings 221 to 226 and the buffer cell 227 in FIG. 22 are connected by route wirings 231 to 236, respectively.
In the above description, the connection method between the flip-flop cells and the buffer cells has been described. However, the same method is applied to the connection between the buffer cells.
[0060]
FIG. 24 is a diagram showing the results of cluster wiring and route wiring of the inter-buffer net. In the figure, CL1a, CL1b, and CL1c are clusters each including a plurality of buffer cells. The buffer cell 241 in the cluster CL1a, the buffer cells 242 and 243 in the cluster CL2a, and the buffer cell 244 in the cluster CL3a are buffer cells. The buffer cell is driven by H.245. The buffer cell 245 and each of the clusters CL1a, CL2a, and CL3a are connected by one route wiring 246, 247, and 248, respectively. As a result, even if there are a plurality of buffer cells to be driven by the buffer cell 245 in the cluster, the problem of wiring congestion due to a plurality of wirings as in the conventional example shown in FIG. 38 can be avoided.
[0061]
The wiring process from step S211 to step S214 is performed for all the clock nets to complete the clock net wiring process. By the processing up to step S130 in FIG. 1, all the cell arrangements and the wiring of the clock tree are completed, and finally the normal net wiring other than the clock net is performed to complete the layout. FIG. 25 is a diagram for explaining a case where the clock net is ignored in the initial arrangement of the flip-flop cells in step S122 of FIG. In the figure, 251 to 254 are flip-flops, 255 and 256 are clock buffer cells, 257 is a clock net that connects the clock buffer cells and the flip-flop cells, and 258 is a data path net that connects the flip-flop cells. In the initial arrangement of the flip-flops, according to the embodiment of the present invention, the clock net is ignored, and the flip-flop cells are arranged by focusing only on the data path net, thereby avoiding the problem in the prior art shown in FIG. The route of the data path net can be shortened and the wiring congestion level can be reduced. In this case, the clock net can reduce the degree of wiring congestion in the process of reconfiguring the clock tree in step S124 in FIG.
[0062]
FIG. 26 is a block diagram showing the configuration of a computer system for carrying out the method according to the present invention. In the figure, a central processing unit (CPU) 261, a CD-ROM drive 262, a keyboard 263, a display 264, a hard disk 265, a memory 266, and a database 267 are connected to a bus 260. The program of the LSI layout method according to the present invention including the flowchart shown in FIG. 1 is stored in the hard disk in advance, but the program including the flowchart shown in FIG. You may make it install in the hard disk 265 from the ROM drive 262. FIG. The memory 266 stores the floor plan information, the arrangement restricted area information, the first cluster information (1), the second cluster information (2), and the first to third netlists described in the flowchart of FIG. The
[0063]
The operator operates the keyboard 263 while looking at the screen on the display 264 to perform LSI layout according to the flowchart of FIG.
[0064]
【The invention's effect】
As described above, according to the present invention, the floor plan is performed from the logic design stage, and the clock tree is generated from the result, so that the clock wiring length between the floor plan blocks can be shortened, and the signal propagation delay Time can be shortened.
[0065]
Further, the skew can be suppressed by adjusting the number of clock buffer stages.
In addition, by ignoring the clock net in the initial placement and reconfiguring the clock net from the result of the flip-flop cell placement, the path other than the clock path is prevented from approaching forcefully, reducing wiring congestion. I can do it.
[0066]
In addition, by performing rearrangement processing by flip-flop cell placement restriction and cluster restriction, the skew of the clock tree final stage net can be suppressed.
In addition, it is possible to alleviate the wiring congestion by specially wiring the buffers between the buffers using clusters.
With the above effects, the overall wiring efficiency can be improved and the processing time can be shortened.
[0067]
Further, since the clock signal propagation delay time and the skew can be suppressed, the timing error after layout is reduced, and the processing time for the timing adjustment work is shortened.
Furthermore, since the wiring density can be afforded by suppressing the degree of wiring congestion, the chip size can be reduced by increasing the density of the margin.
[0068]
In addition, since a high-speed verification tool such as a formal verifier can be used for logic verification after layout, it is possible to shorten the LSI mounting design time.
[Brief description of the drawings]
FIG. 1 is a flowchart for explaining an outline of an embodiment of an LSI layout method according to the present invention;
FIG. 2 is a flowchart showing details of processing contents in step S113 in FIG.
FIG. 3 is a diagram illustrating a clock tree after performing buffering in consideration of floor plan information.
FIG. 4 is a diagram illustrating a result of adjusting the number of buffer stages in step S24 of FIG.
FIG. 5 is a flowchart illustrating details of step S124 in FIG. 1;
6 is a diagram showing a net range of a final stage net when there are overlapping nets in the determination in step S54 of FIG.
7 is a diagram showing the logic of a clock net in the net range shown in FIG. 6. FIG.
FIG. 8 is a diagram showing net merging in step S56 of FIG. 5;
9 is a diagram illustrating the logic of a clock net in the net range shown in FIG. 8. FIG.
FIG. 10 is a diagram for explaining the net dividing process in step S57 of FIG. 5;
FIG. 11 is a diagram for explaining the net dividing process in step S57 of FIG. 5;
12 is a diagram for explaining buffer allocation in step S58 of FIG. 4;
FIG. 13 is a diagram showing the logic of the clock net after allocating buffer cells as shown in FIG.
14 is a diagram showing a virtual arrangement of buffer cells in step S59 of FIG.
FIG. 15 is a diagram for explaining the arrangement restricted area generation in step S126 of FIG. 1;
FIG. 16 is a flowchart illustrating details of the rearrangement process in step S128 of FIG. 1;
FIG. 17 is a diagram showing arrangement restriction region information of flip-flop cells set in step S162 of FIG.
18 is a diagram showing the virtual net created in step S163 of FIG.
FIG. 19 is a diagram showing virtual net rearrangement processing in step S167 of FIG. 16;
20 is a diagram showing second cluster information generated by further increasing the degree of proximity between cells after step S129 of FIG. 1 after the rearrangement of the clusters shown in FIG. 19;
FIG. 21 is a flowchart for explaining the details of the special wiring process of the clock net in step S130 of FIG. 1;
FIG. 22 is an explanatory diagram of intra-cluster wiring processing in step 213 of FIG. 21;
FIG. 23 is an explanatory diagram of the route wiring process in step S214 of FIG.
FIG. 24 is a diagram illustrating a result of cluster wiring and route wiring of an inter-buffer net.
FIG. 25 is a diagram for explaining a case where the initial arrangement of the flip-flop cells in step S122 in FIG. 1 is performed ignoring the clock net.
FIG. 26 is a block diagram showing the configuration of a computer system for carrying out the method according to the present invention.
FIG. 27 is a flowchart illustrating a conventional LSI layout method.
FIG. 28 is a diagram illustrating an example of a clock tree before introducing buffer cells in an LSI module in a conventional method.
FIG. 29 is a diagram showing a clock tree in which buffer cells are introduced in an LSI module in a conventional method.
FIG. 30 is a diagram showing an initial arrangement result of buffer cells and flip-flop cells in an LSI module in a conventional method.
FIG. 31 is a diagram showing an example in which a buffer cell 301 is arranged at the center of an arrangement range of flip-flop cells 310 to 315 driven by the buffer cell 301 in an LSI module in a conventional method.
FIG. 32 is a diagram showing an example in which an arrangement restriction region 322 is set around a buffer cell 321 in the conventional method.
FIG. 33 is a diagram showing a result of rearranging cells in the conventional method.
FIG. 34 is a diagram showing a result of rearranging cells in the conventional method.
FIG. 35 is a diagram showing the setting of cluster bar information 351 to 357 in the conventional method.
FIG. 36 is a diagram showing a wiring of a branch line 361 connecting each flip-flop cell and a cluster bar in the conventional method.
FIG. 37 is a diagram showing route wiring from a driving buffer cell 321 to a cluster bar in a conventional method.
FIG. 38 is a diagram showing special wiring of a net between buffers in the conventional method.
FIG. 39 is a diagram showing a floor plan block and a clock tree in a conventional method.
FIG. 40 is a diagram showing the overlapping of the arrangement restriction regions in the conventional method.
FIG. 41 is a diagram for explaining wiring congestion in a conventional method;
FIG. 42 is a diagram illustrating an arrangement process in which a clock net is not ignored in a conventional method.
[Explanation of symbols]
10 ... Floor plan information file
12: Placement restricted area information
14 ... First cluster information file
16 ... Second cluster information file
18 ... Logical change command file
32-1-32-4 ... Floor plan block
33-1 to 33-4... Buffer cell
34, 35 ... buffer cells
36 ... clock path
41-44 ... Module
45 ... clock source
46-48 ... flip-flop cells
49-55 ... buffer cells
101, 102 ... divided nets
151, 152 ... Arrangement restricted area
171 ... Buffer cell
172 ... flip-flop cell
173 ... Placement restriction area
227: Buffer cell
221 to 226 ... Wiring in the cluster
231 to 236 ... Route wiring
245 ... Buffer cell
246 to 248: Cluster wiring between buffers
251 to 254 ... flip-flop cells
257 ... Clock net
258 ... Data path net
262 ... CD-ROM drive
Buf1, Buf2, ... buffer cells
CL1 to CL4 ... Cluster

Claims (7)

Generating a first netlist that defines a connection relationship between flip-flop cells constituting the LSI by logically synthesizing the LSI design contents described in RTL;
Generating a clock tree of the LSI by executing a floor plan using the first netlist; and
Creating a second netlist including buffer cells for driving the flip-flop cells based on the clock tree;
Based on floor plan information obtained by execution of the floor plan and the second netlist, the buffer cell, the flip-flop cell, and a clock signal line connecting the buffer cell and the flip-flop cell Performing clock layout of the LSI including initial placement;
Wiring the normal net other than the clock signal line after the clock layout,
The LSI layout method, wherein the initial arrangement step includes a step of adjusting the number of buffer stages so that the number of buffer cells from the clock source to each flip-flop cell is equal. The initial placement step performs cell placement processing ignoring nets on the clock tree based on the net list and the floor plan information, and then places flip-flop cells to be connected to the clock tree. The LSI layout method according to claim 1, further comprising a step of determining a position. After the step of adjusting the number of buffer stages, the final stage net of the clock tree is extracted from the initial arrangement of the flip-flop cells, the net range of the extracted final stage net is examined, and a plurality of nets where the net ranges overlap are extracted. Merging, dividing the merged net into nets that do not overlap with the net ranges, and reallocating the nets so that the net ranges do not overlap by assigning buffer cells to the divided nets. Item 4. The LSI layout method according to Item 1. In the clock layout step, the buffer cell placement position on the clock tree is bottomed up based on the result of the flip-flop placement in the cell placement process ignoring the net on the clock tree. For each final stage buffer of the clock tree, the cluster information of the flip-flop cells is created from the placement information of the flip-flop cells driven by the buffers, the placement restricted area information is created around each of the buffer cells, The LSI layout method according to claim 2, further comprising a step of performing a rearrangement process on the cells other than the buffer cell using the rearrangement restricted area information and the cluster information as constraint values. Next to the step of performing the rearrangement processing using the relocation restriction area information and the cluster information as constraint values for cells other than the buffer cell, for each net of the clock tree, create cluster information from the placement position of the driven cell, 5. The LSI layout method according to claim 4, further comprising the steps of: performing cluster wiring between the clustered driven cells for each created cluster; and routing the wiring from the driving cell to each cluster in a star shape. . A step of reconfiguring the clock tree after the step of determining the placement processing of the buffer cells on the clock tree from the bottom up is a step of reconfiguring the clock tree. Generating a third netlist including a clock logic that matches the clock logic on the layout database by changing the second netlist based on the logic change command. The LSI layout method according to claim 4 , further comprising: A recording medium storing an LSI layout program for executing the steps according to any one of claims 1 to 6.

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