JP3768284B2 - Inspection method of semiconductor memory device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor memory device inspection method, and more particularly to a semiconductor memory device capable of writing data and requiring a long time for writing, for example, an EPROM (erasable programmable read only memory) or an EEPROM. The present invention relates to an inspection method suitable for use in (electrically erasable programmable read only memory).
[0002]
In general, user programmable ROMs such as EPROM and EEPROM take longer to write than to read. Therefore, data is written to the chip, for example, test time for guaranteeing write characteristics and work time for incorporating software. There is a need for a very long and useful technique that can shorten the writing time as much as possible in order to make testing and work more efficient.
[0003]
[Prior art]
FIG. 7 is a test flowchart for guaranteeing the write characteristics. In this flow, first, the initial address of the chip to be tested is set (step 1), the value of the counter C is initially set (step 2), and then test data of a predetermined logic is applied to the initial address of the chip for a certain period of time. (Step 3). Here, the write time is T / n (n is an integer of 0 or more), where T is the upper limit write time of the test target chip.
[0004]
When T / n has elapsed, the data at the initial address is read (step 4), and the match between the logic of the read data and the logic of the test data is determined (step 5). In the case of coincidence, PASS (normal writing was possible at T / n with respect to the initial address), and in the case of non-coincidence, FAIL.
In the case of PASS, the address is changed (step 6), the above processing (steps 2 to 5) is repeated, and when the final address is reached (step 7), a non-defective product of the chip is determined.
[0005]
On the other hand, in the case of FAIL, since normal writing could not be performed at T / n, the value of the counter C is incremented (step 8), and T / n is written again for the same address. (Step 3). If FAIL continues even after repeating this rewriting n times, a defective product of the chip is determined (step 9).
[0006]
[Problems to be solved by the invention]
However, in the above processing flow, if the actual write time of the test target chip is within T / n, the write time is one time per address, so the minimum test time is obtained. For example, when T / n is 5 ms (for example, T = 20 ms, n = 4) and the actual writing time T ′ of the chip to be tested is 6 ms, the writing can be performed twice. 2 × (T / n)> T ′ and the test time per address 2 × (T / n) = 10 ms As a result, there is a problem that a wasteful writing time of 2 × (T / n) −T ′ = 4 ms is generated and the test efficiency is poor.
[0007]
If T / n is reduced, useless writing time is reduced, but on the other hand, an increase in test time accompanying an increase in the number of writings cannot be ignored, so that deterioration in test efficiency is unavoidable.
Accordingly, an object of the present invention is to set an optimal write time that matches the actual write characteristics of the chip to be tested, and to greatly reduce the test time or the user program installation time.
[0008]
[Means for Solving the Problems]
In order to achieve the above object, the present invention writes data to an arbitrary address of a semiconductor memory device to be inspected at a predetermined writing time, reads the data, evaluates its logic, and determines whether the writing to the arbitrary address is good or bad. In a semiconductor memory device inspection method for determination, a first step of measuring a write characteristic distribution of a population including a semiconductor memory device to be inspected, and a write time at which a write frequency is approximately 100% based on the write characteristic distribution And a second step of setting the write time as the predetermined write time.
[0009]
Alternatively, the writing time set based on the writing characteristic distribution is divided into two, and when writing by one writing time is not good, writing by the other writing time is executed.
In the present invention, since the optimum write time is set based on the write characteristics of the population including the semiconductor memory device to be tested, the useless write time is limited, and the test time or the user program installation time is greatly increased. Shortening is achieved. Alternatively, the writing time is divided into two, and writing is performed twice, so that it is not necessary to perform additional writing when the first pass, so that the time can be further shortened.
[0010]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings.
FIG. 1 is a schematic flow diagram of an embodiment of a semiconductor memory device inspection method according to the present invention.
This flow includes processing steps of a population selection step 10, a writing characteristic distribution measurement step 11, a test time estimation step 12, a writing time determination step 13 and a population measurement step 14.
“Population selection step 10”
In this step, focusing on the fact that the variation in the write characteristics of the semiconductor memory device shows a specific statistical tendency within the same population such as the same wafer process lot, the semiconductor memory to be tested is selected from several populations. Select the population that contains the chip of the device (hereinafter “chip”). Needless to say, when there is only one population, for example, one wafer process lot, and the chip to be tested shares the lot, that one population is selected.
[0011]
FIG. 2 is a diagram showing the write characteristic distribution of the three populations a, b, and c for convenience. The horizontal axis represents the time required for writing (corresponding to the above-mentioned write time T ′), and the vertical axis represents each write time. The number of normal writes (also referred to as frequency). The average (frequency peak) of the population a is indicated by x ₁ and the variance is indicated by σ ₁ . Similarly, the average of the population is x ₂ and the variance is σ ₂ , and the average of the population c is x ₃ and the variance is indicated by σ ₃ . In this example, the three populations a, b, and c are normal distributions that can be expressed by N (x ₁ , σ ₁ ), N (x ₂ , σ ₂ ), and N (x ₃ , σ ₃ ), respectively. is there. Note that the normal distribution may not be obtained, but in such a case, the frequency distribution may be used as it is.
[0012]
In FIG. 2, PASS is given until a certain writing time T, and FAIL after that. This time T is the upper limit writing time of the test target chip. In the case of FIG. 2, only the hatched portion of the population c is in the FAIL area.
FIG. 3 is a normal distribution diagram of one population. x is an average, and ± 1σ, ± 2σ, and ± 3σ are variances, respectively. 1σ = x + 0.2 ms, 2σ = x + 0.4 ms, 3σ = x + 0.6 ms, −1σ = x−0.2 ms, −2σ = x−0.4 ms, −3σ = x−0.6 ms, for example, x = 6.0 ms and each variance is represented by a value on the time axis, as shown in the figure, 1σ = 6.2 ms, 2σ = 6.4 ms, 3σ = 6.6 ms, −1σ = 5.8 ms, −2σ = 5.6 ms, −3σ = 5.4 ms.
"Write characteristic distribution measurement step 11"
In this step, the writing characteristic distribution of the population selected in step 10 is actually measured, and its average x and variance σ are specified. The measurement may be performed by taking out several chips in the population and writing the data and measuring the time required for the writing. For example, a statistical histogram can be used.
"Test time estimation step 12"
As a result of the measurement, if a normal distribution as shown in FIG. 3 is obtained, x is 6.0 ms and σ is 0.2 ms. The ratio of PASS for each writing time in such a normal distribution is summarized as a table in FIG. The writing time is 8 steps from x ± nσ (n is 1, 2, 3), that is, from the minimum x-3σ to the maximum x + 4σ. x ± 0 is the average. According to this table, for example, when the writing time is minimized (x-3σ), only 1.3% of the whole is PASS, and when it is maximized (x + 4σ), almost 100% of the whole is PASS, and the average (x When ± 0), only 50% of the total passes.
"Write time determination step 13"
In this step, based on the table estimated in the test time estimation step 12, an optimum writing time for the population is determined. In FIG. 4, the write time for which almost 100% of the PASS is PASS in one write is x + 4σ. Therefore, when x = 6.0 ms and σ = 0.2 ms, the optimum write time is 6.0 ms + 4 × 0. 2 ms = 6.8 ms.
"Population measurement step 14"
In this step, the optimal write time (6.8 ms) is used to perform a test for guaranteeing the write characteristics of the chips in the population. The test flow can use FIG. However, n is fixed to 1 when the test flow of FIG.
[0013]
The total test time in this embodiment is the product of the optimum write time (6.8 ms) and the address space size (for convenience, 16384; the same applies below), and the read time (for convenience, 0.1 ms; the same applies below). And the product of the address space size, specifically,
(6.8 ms × 16384) + (0.1 ms × 16384)
≒ 113sec
It becomes.
On the other hand, the total test time of the prior art is the product of the write time (5.0 ms), the size of the address space and the number of writes (2 times), the read time, the size of the address space, and the number of writes (2 ) Times the product, specifically,
(5.0 ms x 16384 x 2) + (0.1 ms x 16384 x 2)
≈ 167 sec
It becomes.
[0014]
Therefore, according to the present embodiment, it is possible to shorten the test time by about 30% from 167 sec to 113 sec.
In the above embodiment, writing is performed once with the optimum writing time (x + 4σ). However, in some cases, writing in two times can shorten the time.
[0015]
The following example is an improved example suitable for use in such a case.
FIG. 5 is a convenient table for explaining the improved embodiment. The point of this table is that the two write times are combined so that the frequency of the first write time and the frequency of the additional write time are almost 100%. For example, the additional write time A ₂ paired with the _first write time A ₁ corresponding to x-3σ is a time corresponding to 7σ, and the first write time B ₁ corresponding to x-2σ. The additional write time B ₂ paired with is a time corresponding to 6σ, and the additional write time C ₂ paired with the _first write time C ₁ corresponding to x−1σ corresponds to 5σ. It is time to do. These total times are indicated by ΣA, ΣB, ΣC,.
[0016]
As described in the above embodiment, the total test time when writing at one time with the optimum writing time (x + 4σ) was approximately 113 seconds. On the other hand, the total test time when writing twice in x and 4σ is approximately 107 seconds, and the test time can be further shortened. The calculation formula for writing in two steps is as follows.
[0017]
[16384 × (6.0 ms + 0.1 ms)] +
[16384 × (0.8 ms + 0.1 ms)] × 0.5
= 107.31 sec
By the way, the total test time when the first write time is x-3σ and the additional write time is 7σ is:
[16384 × (6.0 ms−0.6 ms + 0.1 ms)] +
(16384 × 1.4ms)
= 113.05 sec
Therefore, it is most efficient to divide into x and 4σ twice.
[0018]
FIG. 6 is a test flow chart for assuring the write characteristics of chips in the selected population in this improved embodiment, and corresponds to FIG. 7 of the conventional example.
In this flow, first, after setting the initial address of the test target chip (step 20), it is determined whether or not the first writing is performed (step 21). If it is the first time, the first writing time is set (step 22). Otherwise, the additional writing time is set (step 23). Then, test data having a predetermined logic is written to the initial address of the chip over the set time (step 24). When the set time elapses, the data of the initial address is read (step 25), and the logic of the read data is read. Is matched with the logic of the test data (step 26). PASS if there is a match, FAIL if there is no match.
[0019]
In the case of PASS, the address is changed (step 27), the above processing (steps 21 to 26) is repeated, and when the final address is reached (step 28), a non-defective product of the chip is determined.
On the other hand, in the case of FAIL, it is determined whether or not it is the second writing (step 29). In the case of YES, the chip is determined to be defective, and in the case of NO, step 21 and subsequent steps are performed to perform additional writing. Execute.
[0020]
According to this improved embodiment, the optimum writing time is divided into two and the second writing is performed only when the first writing is FAIL, so that the test time can be further shortened. it can.
In each of the above embodiments, the writing time is set with the variance σ of the normal distribution as one unit, but the present invention is not limited to this. The distribution σ may be subdivided into one unit, or when the distribution is not a normal distribution, the frequency distribution may be used as it is, and a variation value may be used instead of the dispersion σ.
[0021]
In the improved embodiment, the combination of the first writing time and the additional writing time is a combination that minimizes the total time, but the first writing time exceeds the upper limit writing time T in the standard. Must not.
Furthermore, in each of the above embodiments, the application to the test for guaranteeing the write characteristic of the chip has been shown. A user program can be incorporated with an optimum writing time without excess or deficiency, and is particularly advantageous when a large amount of user program ROM is manufactured.
[0022]
【The invention's effect】
According to the present invention, since the optimal write time is set based on the write characteristics of the population including the semiconductor memory device to be tested, the useless write time can be localized, and the test time or user program incorporation time can be greatly increased. Can be shortened. Alternatively, the writing time is divided into two, and writing is performed twice, so that when the first pass, there is no need to perform additional writing, so that the time can be further reduced.
[Brief description of the drawings]
FIG. 1 is a test flow diagram of one embodiment.
FIG. 2 is a write distribution characteristic diagram of three populations shown for convenience.
FIG. 3 is a detailed diagram of write distribution characteristics of one population.
FIG. 4 is a table showing the writing time and the number of times that data can be normally written in that time.
FIG. 5 is a table showing combinations when the writing time is divided into two.
FIG. 6 is a test flow diagram of an improved example.
FIG. 7 is a test flow diagram of a conventional example.
[Explanation of symbols]
11: Write characteristic distribution measurement step (first step)
13: Write time determination step (second step)

Claims (2)

In an inspection method for a semiconductor memory device, data is written to an arbitrary address of a semiconductor memory device to be inspected at a predetermined write time, the data is read out, the logic is evaluated, and the quality of writing to the arbitrary address is determined.
A first step of measuring a write characteristic distribution of a population including a semiconductor memory device to be inspected;
A second step of setting a write time at which the write frequency is approximately 100% based on the write characteristic distribution, and setting the write time as the predetermined write time. Method. 2. The writing time set based on the writing characteristic distribution is divided into two, and when writing by one writing time is not good, writing by the other writing time is executed. Inspection method of semiconductor memory device.

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