JP3788822B2 - Computer system and failure recovery method in the system - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a computer system and a failure recovery method thereof, and more particularly to an improved computer system and a failure recovery method thereof that can recover from a failure caused by a fixed failure of a main memory.
[0002]
[Prior art]
In general, in a computer system, a memory with parity is employed in order to increase the reliability against a memory failure. In a memory subsystem having a memory with parity, a checksum of the data is calculated when the data is read, and a memory error is detected by comparing the checksum with a parity bit. Thereby, the use of incorrect memory data can be prevented beforehand.
[0003]
However, error correction cannot be performed because it is impossible to specify which bit of memory data has an error only by using parity.
On the other hand, when a memory subsystem using a redundant code such as an SEC-DED code is used, 1-bit error correction and 2-bit error detection are possible. That is, even if one bit of data is permanently in error, this can be corrected automatically and processing can be continued. Therefore, in a computer system that requires high reliability, it is desirable to employ a memory subsystem using a redundant code such as a SEC-DED code rather than a memory with parity.
[0004]
However, when a memory subsystem using a redundant code such as a SEC-DED code is introduced into an existing computer system that employs a memory with parity, the existing memory with parity cannot be used as it is. It is necessary to newly reconstruct the main memory to correspond to the SEC-DED code. Therefore, a lot of cost is required for the introduction.
[0005]
On the other hand, the fault tolerant computer system employs a configuration in which all memory failures are masked by duplication of memory. According to this dual memory configuration, the same data is always held in the two memories, so that if a data error is detected, the processing is continued by using the data in the other memory. Can do.
[0006]
However, there are disadvantages such as a large amount of hardware because it is necessary to duplicate the memory, and a special structure is required for switching the access memory when an error is detected.
[0007]
Therefore, recently, a checkpoint using a log memory for storing update history information of the main memory is a method for realizing recovery from a general failure with additional hardware without duplicating the memory. A restart method has been proposed. In this checkpoint restart method, information necessary for process re-execution is stored in the main memory for each checkpoint, and the main memory is updated as the process is executed during the period from one checkpoint to the next. Each time the data is updated, the data before update is collected in the log memory as the update history information. When a failure occurs in the computer system, the main memory can be restored to the time of the checkpoint before the failure by using the contents of the log memory. Therefore, by adopting a checkpoint restart method using a log memory, the contents of the memory can be restored with a small amount of hardware without using a dual memory.
[0008]
However, in this method, when a failure occurs in which the contents of the memory are permanently rewritten, there is a case where it cannot be recovered even if the failure can be detected. In other words, if the value of the memory data has been rewritten before the previous checkpoint, the wrong memory data will be read again even if the process is resumed by returning to the previous checkpoint when a failure is detected. Will not be able to recover.
[0009]
[Problems to be solved by the invention]
As described above, when a memory subsystem using a redundant code such as a SEC-DED code is introduced into an existing computer system employing a memory with parity, the existing memory with parity cannot be used as it is. However, it is necessary to newly reconstruct a large-capacity main memory so as to correspond to the SEC-DED code, and there is a disadvantage that a lot of cost is required for its introduction.
[0010]
Checkpoint restart method using log memory to store update history information of main memory as a method to realize recovery from general failure with additional hardware without duplicating memory However, this method has a problem that it may not be possible to cope with a memory failure in which data is permanently rewritten.
[0011]
The present invention has been made in view of the above points, and makes it possible to construct a memory subsystem having an error correction function by using additional hardware while using resources such as an existing memory with parity as it is, and to improve reliability against a memory failure. An object of the present invention is to provide a computer system with high accuracy.
[0012]
In addition, the present invention enables processing to continue even when a memory failure occurs that cannot be recovered by the checkpoint restart method using a log memory, and sufficient hardware is sufficient without duplicating the memory. It is an object of the present invention to provide a computer system and a failure recovery method capable of realizing excellent fault tolerance performance.
[0013]
[Means for Solving the Problems]
The present invention is connected to one or more CPUs and the CPU via a bus, With parity to store data with added parity In a computer system having a main memory, A cache memory, a memory controller provided between the bus and the main memory and controlling the main memory; A plurality of storage areas are provided corresponding to each address serving as a unit of read / write access to the main memory, and each storage area corresponds to the storage area. Of the main memory Redundancy that can correct errors that occur in some of the data stored at the address code A redundant code memory, and the bus and the redundant code memory Between Control device for controlling the redundant code memory Because Monitor bus transactions issued on the bus; When a write back from the cache memory to the main memory is executed, A redundant code corresponding to the data is generated from the value of the data on the bus, and the redundant code is stored in the storage area of the redundant code memory corresponding to the unit data write address. When data error of the read data is detected by the controller and parity check by the memory controller when reading data from the main memory, the read data and the redundant code memory corresponding to the read data are stored. Error correction means for reconstructing correct data from the redundant code It is characterized by that.
[0014]
In this computer system, a redundant code memory and a control device for controlling the redundant code memory are provided. By monitoring a bus transaction issued on the bus, Write back from cache memory to main memory is executed When this is detected, a redundant code corresponding to the data is automatically generated from the value of the data on the bus in the control device and stored in the corresponding storage area of the redundant code memory. Further, when a data error of the read data is detected by the parity check by the memory controller when reading data from the main memory, correct data is reconstructed from the read data and the redundant code corresponding to the read data. in this way, When an error is detected in the data in the main memory, correct data can be reconstructed from that data and the corresponding redundant code, so error correction is possible simply by providing the redundant code memory and control device described above as additional hardware. A memory subsystem having functions can be constructed, and a computer system with high reliability against a memory failure can be realized.
[0015]
Further, the apparatus further comprises a log memory connected to the control means for storing update history information of the main memory, wherein the control means performs data writing before data writing to the main memory by the CPU is executed. Read the pre-update data of the main memory corresponding to the address to be executed and the redundant code corresponding to the pre-update data from the main memory and the redundant code memory, respectively, and use the pre-update data and redundant code as the update history information Stored in the log memory, When a failure that requires restoring the contents of the main memory to the state before the failure occurs, the pre-update data and redundant code constituting each update history information stored in the log memory are stored in the main memory and Each of the redundant code memories is written back to restore the main memory to the state before the failure, and the contents of the redundant code memory are restored to the state corresponding to the restored contents of the main memory. It is preferable to configure as described above.
[0016]
With this configuration, the content of the main memory can be restored to the state before the failure using the content of the log memory, and correct data can be reconstructed by using the redundant code even when a memory failure occurs. In this case, a memory failure that cannot be recovered only by the checkpoint restart method by reconstructing the correct data using the redundant code and restarting the processing from the checkpoint before the failure occurred. Will be able to continue processing.
[0017]
In addition to storing the pre-update data as well as the redundant code corresponding to the pre-update data in the log memory, a failure that requires restoring the contents of the main memory to the state before the failure occurred When writing the pre-update data and redundant code constituting each update history information stored in the log memory back to the main memory and redundant code memory, respectively, the main memory can be restored to the state before the failure occurred, and The contents of the redundant code memory can be returned to the state corresponding to the restored contents of the main memory.
[0018]
In addition, storage of update history information including pre-update data to the log memory must be performed before data write to the main memory is executed. However, in a system having a cache memory, the CPU writes data to the cache memory. Read the data before update of the main memory corresponding to the address where the data was written and the corresponding redundant code from the main memory and the redundant code memory, respectively, and update history of the data before update and the redundant code. By storing the information in the log memory as the information, the update history information can be easily stored before the data writing to the main memory is executed.
[0019]
Further, instead of the above-described redundant code memory, the main memory has a plurality of storage areas provided corresponding to each unit data block composed of a plurality of data strings that are continuously accessed. By using a vertical parity memory that holds vertical parity data for the same bit position of each of a plurality of data strings belonging to a unit data block corresponding to the storage area, a simple process called a parity process can be used. It is possible to reproduce correct block data.
[0020]
Furthermore, instead of the vertical parity memory, there are a plurality of storage areas provided corresponding to a plurality of data block groups each including a plurality of unit data blocks each having a plurality of data strings on the main memory. In each storage area, a block parity memory that holds block parity data composed of vertical parity data for the same bit position of each of a plurality of unit data blocks belonging to the data block group corresponding to the storage area is adopted. As a result, it is possible to reproduce correct block data even when a wide range of memory failures such as memory module units occur.
[0021]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings.
FIG. 1 conceptually shows the configuration of a computer system according to the first embodiment of the present invention. This computer system stores information necessary for failure recovery at each checkpoint in the main memory. When a failure occurs, the main memory update history information stored in the log memory is used to store the contents of the main memory before the failure occurs. Is a multiprocessor system that employs a failure recovery method of restoring at the time of a checkpoint, and as shown, a processor bus 10, CPUs 11-1 to 11-n, cache memories 12-1 to 12-n, main memory 14, a redundant code memory (CM) 16, and a before image buffer (BIB) 17.
[0022]
The cache memories 12-1 to 12-n are used as primary caches or secondary caches of the CPUs 11-1 to 11-n sharing the main memory 14, and at the time of checkpoint acquisition, the cache memory 12- For each of 1 to 12 -n, data not reflected in the main memory 14 is written into the main memory 14.
[0023]
The main memory 14 is a memory having an error detection function such as a memory with parity, and a parity bit for the data string of the word in units of words that is a data unit read / written by one memory access by the CPU. Is added.
[0024]
The redundant code memory (CM) 16 is provided to add an error correction function to the main memory 14 having an error detection function, and has entries for the number of words of the main memory 14. Each entry stores an error correction redundancy code of a corresponding word in the main memory 14. For example, the error correction redundant code for the word N of the main memory 14 is stored in the Nth entry of the redundant code memory 16.
[0025]
The writing of the error correcting redundant code to the redundant code memory (CM) 16 is executed in response to the bus transaction when a bus transaction for writing data to the main memory 14 is issued on the bus 10. In this case, an error correcting redundant code is generated from the data output on the bus 10, and the entry position of the redundant code memory (CM) 16 to which the error correcting redundant code is written is determined from the memory address output on the bus 10. Is done.
[0026]
The before image buffer (BIB) 17 is used as a log memory for holding update history information of the main memory 14 during a period from one check point to the next check point, and data writing to the main memory 14 is performed. Before each data write, the update history information includes the address indicating the data write address of the main memory 14, the pre-update data, and the error correction redundant code of the redundant code memory 16 corresponding to the pre-update data. Are stored in the before image buffer (BIB) 17 in a stack format. The error correction redundant code is stored together with the address and the pre-update data when the contents of the main memory 14 are restored using the update history information of the before image buffer (BIB) 17 and the redundant code is adjusted accordingly. This is because the contents of the memory (CM) 16 can be restored together.
[0027]
When the main memory 14 has only a 1-bit error detection capability based on parity, a 1-bit error correction code can be used as an error correction redundancy code stored in the redundancy code memory 16.
[0028]
Next, the data flow in the system of FIG. 1 will be described in detail with reference to FIGS.
First, with reference to FIG. 2, the error correction redundant code writing operation to the redundant code memory (CM) 16 will be specifically described.
[0029]
As shown in FIG. 2, a main memory controller (MM controller) 13 is provided between the bus 10 and the main memory 14, and read / write control of the main memory 14 is performed by the main memory controller (MM controller). ) 13 is executed. A BIB / CM controller 15 is commonly provided between the redundant code memory (CM) 16, the before image buffer (BIB) 17, and the bus 10, and the redundant code memory (CM) 16 and the before image are provided. The read / write control of each buffer (BIB) 17 is executed by the BIB / CM controller 15.
[0030]
Hereinafter, an operation performed when data from the CPU 11-1 is written to an address N of the main memory 14 will be described.
Transactions on the bus 10, that is, various commands, addresses and data on the bus 10 are monitored by the BIB / CM controller 15, and a transaction for writing data to the main memory 14 is issued on the bus 10 from the CPU 11-1. Then, the memory address (N) and data (Dold1) at that time are acquired by the BIB / CM controller 15. This bus transaction is actually performed when data is written back from the cache memory 12-1 to the main memory 14.
[0031]
On the other hand, the MM controller 13 writes data (Dold1) at the address of the word N specified by the address (N) in response to a transaction for writing data to the main memory 14. In this case, an error detection bit (P) corresponding to the value of the data (Dold1) is generated inside the MM controller 13, and the data (Dold1) is written to the main memory 14 with the error detection bit (P) added. It is.
[0032]
In the BIB / CM controller 15, a redundant code (Cold1) that can correct an error generated in a part of the value of the data (Dold1) is generated by an ECC operation or the like, and the redundant code (Cold1) is generated. It is written in the entry (N) of the redundant code memory (CM) 16 corresponding to the address (N).
[0033]
As described above, the redundant code memory (CM) 16 has the same number of entries as the number of words in the main memory 14, and each word in the main memory 14 and the entry in the redundant code memory (CM) 16 have a one-to-one relationship. It corresponds with. Therefore, when the data error is detected by the MM controller 13 when reading the data (Dold1) from the word N of the main memory 14, the error processing software or the like enters the entry (in the redundant code memory (CM) 16). By reconstructing correct data from the redundant code (Cold 1) of N) and the error detected data, the data (Dold 1) of the word N in the main memory 14 can be restored.
[0034]
Next, with reference to FIG. 3, an operation of writing update history information to the before image buffer (BIB) 17 will be described.
Here, a case where the CPU 11-1 updates the data written in the address of the word N designated by the address (N) of the main memory 14 from Dold1 to Dnew1 will be described as an example.
[0035]
In this case, when Dnew1 is written into the cache memory 12-1, the BIB / CM controller 15 reads the data (Dold1) and the corresponding redundant code (Cold1) from the main memory 14 and the redundant code memory 16, respectively. Then, update history information including an address (N), pre-update data (Dold1), and a redundant code (Cold1) is stored in the before image buffer (BIB) 17.
[0036]
Next, an operation for restoring the contents of the main memory 14 using the update history information stored in the before image buffer (BIB) 17 will be described with reference to FIG.
[0037]
When a failure that requires restoring the contents of the main memory 14 to the state before the failure occurs, update history information is sequentially read from the before image buffer (BIB) 17 under the control of error processing software or the like. Then, the process of writing the pre-update data and the redundant code back to the corresponding storage locations in the main memory 14 and the redundant code memory 16 is performed.
[0038]
For example, when four pieces of update history information as shown in the figure are stored in the before image buffer (BIB) 17, first, the fourth update history information (address N, pre-update data Dd, redundant code Cd) And the pre-update data Dd is written to the address N of the main memory 14 and the redundant code Cd is written to the entry N of the redundant code memory 16. Next, the third update history information (address 2, pre-update data Dc, redundant code Cc) is written back, the pre-update data Dc is written to address 2 of the main memory 14, and the redundant code memory Redundant code Cc is written in 16 entries 2. Thereafter, similarly, the second update history information and the first update history information are written back sequentially.
[0039]
In this way, the main memory 14 can be restored to the state before the failure, and the contents of the redundant code memory 16 are also restored to the state corresponding to the restored contents of the main memory 14.
[0040]
As described above, the case of memory access in units of words has been described. However, in the case where access to the main memory 14 is performed in units of cache blocks, it is possible to write error correction redundancy code and update history information in the same manner. it can. In other words, if the cache block is composed of n words, the above-described process may be repeated n times for one access.
[0041]
Next, a specific hardware configuration of the BIB / CM controller 15 will be described with reference to FIG.
The BIB / CM controller 15 includes a bus interface control unit 101, a bus transaction response control unit 102, a bus transaction issue control unit 103, a buffer access controller 104, a state storage control unit 105, and a code memory controller 106, as shown in the figure. Has been.
[0042]
The bus interface control unit 101 is connected to various signal lines defined on the bus 10, and exchanges addresses, data, and various statuses with the bus 10. On this bus 10, as shown in the figure, an address / data bus (address / data) used for data transfer on the bus 10, a command line, and a status line for cache control. (Shared, modified) and the like are defined. The shared line indicates a status (shared clean) in which a copy of the memory data requested in the memory read transaction is shared in a clean state. The modified line indicates a status (modified) that is shared while the copy of the memory data requested by the memory read transaction is changed.
[0043]
By monitoring the state of these various signal lines on the bus 10 through the bus interface control unit 101, the BIB / CM controller 15 snoops the cache status and the bus transaction.
[0044]
The bus transaction response control unit 102 operates in response to a predetermined bus transaction received via the bus interface control unit 101. For example, when a failure occurs, the bus transaction response control unit 102 is issued on the bus 10 by a certain CPU. In response to a word write transaction, the transaction is aborted.
[0045]
The bus transaction issue control unit 102 issues a transaction such as memory read / write on the bus 10. For example, the state of the signal line on the bus 10 received via the bus interface control unit 101 is transferred to the cache memory. Is detected, the transaction for reading the pre-update data from the main memory 14 is started.
[0046]
The state storage control unit 105 performs control of a pointer value for designating a position where update history information is stored in the before image buffer (BIB) 17, and stores the update history information in the before image buffer (BIB) 17. Each time, the pointer value is updated by +1. When the main memory 14 is restored using the update history information of the before image buffer (BIB) 17, the state storage control unit 105 changes the pointer value from the current value to −1 each time the update history information is read. Control such as updating each time.
[0047]
The buffer access controller 104 is provided with an address line (BIB address), a data line (BIB data), and a read / write control line (BIB RAS #, CAS #, WE #) provided with the before image buffer (BIB) 17. Used to control data writing and reading to the before image buffer (BIB) 17.
[0048]
The code memory controller 106 includes an address line (CM address), a data line (CM data), and a read / write control line (CM RAS #, CAS #, WE #) provided between the code memory controller 106 and the redundant code memory (CM) 16. Used to control data writing and reading to the redundant code memory (CM) 16. In the writing process, the code memory controller 106 generates a redundant code by calculation from data on the bus 10 received via the bus interface control unit 101, and writes it into the redundant code memory (CM) 16.
[0049]
Next, specific operations of the system of FIG. 5 will be described with reference to FIGS.
The timing chart of FIG. 6 shows a series of operations executed when data is written back from an arbitrary cache memory to the main memory 14.
[0050]
When data is written back from the cache memory to the main memory 14, a command (write-line) indicating a write back of the cache line is issued on the command line (COMMAND) by the cache memory or the CPU corresponding thereto, and The memory address (A) is output to the address bus (address bus), and the write data (Dnew) is output to the data bus (data bus). When the cache block is composed of 4 words, burst transfer is performed, and data Dnew1 to Dnew4 are continuously output on the data bus (data bus).
[0051]
In response to this bus transaction, the main memory controller 13 and the BIB / CM controller 15 operate.
The main memory controller 13 controls an address line (MM address), a data line (MM data), and a read / write control line (MM RAS #, CAS #, WE #) provided with the main memory 14, Data (Dnew1 to Dnew4) is written in four consecutive addresses starting from the address (A) in the main memory 14.
[0052]
On the other hand, in the BIB / CM controller 15, the code memory controller 106 operates, and first, redundant codes (Cnew1 to Cnew4) corresponding thereto are generated from the data (Dnew1 to Dnew4) on the bus 10 by calculation. The redundant codes (Cnew1 to Cnew4) are output on the data line (CM data), and the row address (Ar) and column address (Ac1 to Ac4) generated from the address (A) received from the bus 10 are also displayed. Is output to the address line (CM address), and redundant codes (Cnew1 to Cnew4) are written in the entries of the redundant code memory 16 corresponding to the address (A).
[0053]
As described above, the writing of the redundant code to the redundant code memory 16 is automatically executed by the code memory controller 106 in parallel with the write back process when data is written back from the cache memory to the main memory 14. .
[0054]
FIG. 7 shows a series of processing procedures executed when an arbitrary CPU writes to a shared cache line in the corresponding cache memory.
[0055]
When writing to the shared cache line is performed, an invalidate command (invalidate) is sent to the address bus on the command line (command) on the bus 10 in order to notify other cache memory that the shared data is changed. The address (A) of the shared data is issued on (address bus), and the invalidation protocol is executed. In this invalidation protocol, writing to the shared cache line is waited until another cache memory invalidates the copy of the shared data.
[0056]
When the bus transaction issuance control unit 103 of the BIB / CM controller 15 confirms the invalidate command, the pre-update data (D1 to D4) of the address (A) is obtained from the main memory 14 using the address (A) at that time. Start a memory read transaction for reading. At this time, the command issued on the command line (command) on the bus 10 is read non-snoop, and each cache memory does not perform the snoop operation for the read cycle.
[0057]
The main memory controller 13 controls the address line (MM address), the data line (MM data), and the read / write control line (MM RAS #, CAS #, WE #) in response to the memory read transaction. The data (D1 to D4) are read from the address (A) of 14 and output on the data bus (data bus) of the bus 10.
[0058]
On the other hand, in the BIB / CM controller 15, the address (A) is also passed to the buffer access controller 104 and the code memory controller 106. The code memory controller 106 outputs the row address (Ar) and the column addresses (Ac1 to Ac4) generated from the address (A) on the address bus (CM address), and before updating from the entry A of the redundant code memory 16 The redundant codes (C1 to C4) corresponding to the data (D1 to D4) are read out.
[0059]
Thereafter, the buffer access controller 104 reads the address (A), the data (D1 to D4) output on the data bus (data bus) of the bus 10, and the redundant code (C1) read by the code memory controller 106. ˜C4) are assembled into the data storage format of the update history information and written to the entry of the before image buffer (BIB) 17 designated by the pointer value (P).
[0060]
As described above, the update history information is written to the before image buffer (BIB) 17 when the data is written to the cache memory, that is, before the data is written back from the cache memory to the main memory 14. 103, automatically executed by the buffer access controller 104 and the code memory controller 106.
[0061]
FIG. 8 shows the flow of recovery processing when a data error in the read data is detected when data is read from the main memory 14.
Here, a case will be described in which the contents of the main memory 14 can be correctly restored to the original instruction without being restored to the time of the checkpoint before the error occurred.
[0062]
That is, when data (D) written in the main memory 14 at a certain point in time is subsequently read out from the main memory 14, if the data (D) is an incorrect data value (D ') due to a memory error or the like. In the case of the replacement, the occurrence of a memory data error is detected by checking the error detection code by the main memory controller 13. The occurrence of this memory data error is notified to a predetermined CPU by a hardware interrupt signal or the like, and an error interrupt routine is executed by the CPU.
[0063]
The CPU executing the error interrupt routine masks the error interrupt so that it does not occur again (step S10), and then reads the data (D ′) stored at the address where the error occurred in the main memory 14, and then The corresponding redundant code (C) is read from the redundant code memory 16 (steps S11 and S12). Thereafter, the CPU reconstructs the correct data (D) from the data (D ′) and the redundant code (C) (step S13), and sets the data (D) to the address where the error occurred in the main memory 14. Store (step S14).
[0064]
This procedure of the recovery process can be applied to a system that does not employ the checkpoint restart method using the before image buffer (BIB) 17 because the before image buffer (BIB) 17 is not used.
[0065]
FIG. 9 shows a second example of the recovery process in the case where a data error of the read data is detected when reading data from the main memory 14.
Here, when data (D) written in the main memory 14 before a certain checkpoint CP1 is read from the main memory 14 for the first time after the checkpoint CP1 is obtained, the data (D) is stored in the memory. A case is assumed in which it is detected that an incorrect data value (D ′) is replaced due to an error or the like.
[0066]
The occurrence of this memory error is detected by checking the error detection code of the data value (D ′) by the main memory controller 13 and notified to a predetermined CPU by a hardware interrupt signal or the like. Then, the recovery routine is executed by the CPU.
[0067]
The CPU that executes the recovery routine masks the error interrupt so as not to occur again (step S20), reads the data (D ′) stored in the address where the error occurred in the main memory 14, and then responds to it. The redundant code (C) to be read is read from the redundant code memory 16 (steps S21 and S22). Thereafter, the CPU reconstructs the correct data (D) from the data (D ′) and the redundant code (C) (step S23), and sets the data (D) to the address where the error occurred in the main memory 14. Store (step S24).
[0068]
Next, the CPU controls the BIB / CM controller 15 to write the pre-update data of the before image buffer (BIB) 17 back to the main memory 14 and write back the redundant code to the redundant code memory 16 (step S25, S26). Thereafter, the process state collected at the checkpoint CP1 is restored to each CPU, and the processing is resumed from the checkpoint CP1.
[0069]
Thus, by correcting the memory error and then restoring the contents of the main memory 14 to the time of the checkpoint before the failure occurs, it becomes possible to prevent the same failure from recurring due to erroneous reading of the memory data. Therefore, even when a memory failure occurs that cannot be recovered by the checkpoint restart method alone, the processing can be continued.
[0070]
FIG. 10 shows the configuration of a computer system according to the second embodiment of the present invention.
This computer system employs a vertical parity memory 21 in place of the redundant code memory 16 provided in the system of the first embodiment, and is a unit read / written by continuous access by the CPU such as burst transfer instead of word units. It is configured to manage vertical parity data used for error correction in units of data blocks (cache blocks).
[0071]
That is, the main memory 14 is a memory having an error detection function, such as a memory with parity, and is a word unit that is a data unit read / written by one memory access by the CPU with respect to a data string of the word. Parity bits are added.
[0072]
The vertical parity memory 21 is provided to add an error correction function to the main memory 14 having an error detection function, and has entries for the number of unit data blocks that can be stored in the main memory 14. Yes. In each entry, vertical parity data calculated from the bit arrangement at the same bit position of each data string among the data strings belonging to the corresponding unit data block of the main memory 14 is stored. For example, as shown in FIG. 11, the unit data block of the cache block N of the main memory 14 is composed of 4-byte data D0 to D3, and each of the data D0 to D3 has 4 horizontal parity bits P0 to P3. When P3 is added, the entry N of the vertical parity memory 21 has the same bit position of the 4-byte vertical parity Dp and the horizontal parity bits P0 to P3 calculated for each same bit position of the data D0 to D3. Vertical parity data including 4-bit vertical parity Pp calculated every time is stored.
[0073]
In this way, the unit data block is divided into data units that can be detected by the horizontal parity bit, and the vertical parity data calculated for these is stored in the vertical parity memory 21, whereby the data in which the occurrence of the error is detected. It is possible to determine from the vertical parity data which bit position is in error, and error correction becomes possible.
[0074]
The writing of the vertical parity data to the vertical parity memory 21 is executed in response to the bus transaction when a bus transaction for writing back a cache line having the cache memory to the main memory 14 is issued on the bus 10. . In this case, vertical parity data is generated from the unit data block for one cache line continuously output on the bus 10 and the vertical parity data is to be written from the unit block address output on the bus 10. 21 entry positions are determined.
[0075]
When only a part of data belonging to a unit data block in the main memory is updated by word unit writing, the unit data block to be updated is read from the main memory 14, and the unit data block and the data are written. New vertical parity data is obtained from the difference from the data and the vertical parity data of the vertical parity memory 21 corresponding to the read unit data block. Then, the vertical parity data is written to the entry of the vertical parity memory 21 corresponding to the unit data block to which the write data belongs.
[0076]
The before image buffer (BIB) 17 is used as a log memory for holding update history information of the main memory 14 during a period from a certain checkpoint to the next checkpoint, as in the first embodiment. Each time data is written to the main memory 14, before the data is written, the cache block address of the main memory 14 to which the address where the data is written belongs, the unit data block before update, and the unit data block before update are stored. Corresponding vertical parity data is stored in the before image buffer (BIB) 17 in a stack format as update history information.
[0077]
When an error is detected in the read data of the main memory 14, the bit position where the error has occurred is specified from the error detection result by the horizontal parity of the main memory 14 and the vertical parity data, and correct data is reconstructed. Then, it is written back to the main memory 14.
[0078]
In the second embodiment, generation of vertical parity data and read / write control of update history information for the before image buffer (BIB) 17 are realized by hardware similar to that of the first embodiment described with reference to FIG. That is, the operation is described by replacing the redundant code memory 16 in the system of FIG. 5 with the vertical parity memory 21. When writing the vertical parity data to the vertical parity memory 21, the data is written back from the cache memory to the main memory 14. In parallel with the write back processing, the code memory controller 106 automatically executes the processing. Also, the update history information is written to the before image buffer (BIB) 17 when the data is written to the cache memory, that is, before the data is written back from the cache memory to the main memory 14, the bus transaction issuance control unit 103, It is automatically executed by the buffer access controller 104 and the code memory controller 106.
[0079]
Also, the failure recovery processing in the second embodiment can be performed in the same procedure as in the first embodiment described with reference to FIGS. That is, when restoring the contents of the main memory 14 to the checkpoint state before the failure, the correct data is reconstructed using the vertical parity data, and then the update history information is received from the before image buffer (BIB) 17. A process of sequentially reading and writing back the pre-update unit data block and the vertical parity data to the corresponding storage positions in the main memory 14 and the vertical parity memory 21, respectively, is performed.
[0080]
The case where the data in the main memory has parity and can detect a 1-bit error has been described above, but the same configuration is possible when the SEC-DED code is used. In this case, when a 2-bit error is detected when reading data from the main memory, the correct data is reconstructed by the same method as described above, and the failure can be recovered.
[0081]
FIG. 12 shows the configuration of a computer system according to the third embodiment of the present invention.
This computer system employs a block parity memory 22 in place of the redundant code memory 16 provided in the system of the first embodiment, and is a unit read / written by continuous access by the CPU such as burst transfer instead of word units. It is configured to manage block parity data used for error correction in units of data block groups each including four data blocks (cache blocks).
[0082]
That is, the main memory 14 is a memory having an error detection function, such as a memory with parity, and is a word unit that is a data unit read / written by one memory access by the CPU with respect to a data string of the word. Parity bits are added.
[0083]
The block parity memory 22 is provided to add an error correction function to the main memory 14 having an error detection function, and has entries for the number of data block groups that can be stored in the main memory 14. Yes. Each entry stores vertical parity data calculated from the bit arrangement at the same bit position of each data block belonging to the corresponding data block group in the main memory 14.
[0084]
In this way, the occurrence of an error is detected by dividing the block data group into unit data blocks that can be read and written by one cache line operation and storing the calculated vertical parity data in the block parity memory 22. The unit data of the unit data block thus detected can be detected by the horizontal parity of the main memory 14, and which bit position is in error can be obtained from the block parity data, thereby enabling error correction.
[0085]
Writing block parity data to the block parity memory 22 is executed when it is detected that a bus transaction for writing back a cache line in the cache memory to the main memory 14 has been issued on the bus 10. In this case, the data block updated by the unit data block for one cache line continuously output on the bus 10 is read from the main memory 14, and the difference between the data block and the unit data block to be written (exclusive) New block parity data is generated from the block parity data of the block parity memory 22 corresponding to the data block group. Then, the block parity data is written to the entry of the block parity memory 22 corresponding to the data block group to which the unit data block to be written belongs.
[0086]
The before image buffer (BIB) 17 is used as a log memory for holding update history information of the main memory 14 during a period from a certain checkpoint to the next checkpoint, as in the first embodiment. Each time data is written into the main memory 14, the address of the block data group of the main memory 14 to which the address where the data is written belongs, the data block group before update, and the data block before update are written. Block parity data corresponding to the group is accumulated in the before image buffer (BIB) 17 in a stack format as update history information.
[0087]
In this case, the pre-update data block and the block parity data necessary for generating the new block parity data are read out as update history information for storage in the before image buffer (BIB). Can be used in combination, and each can be controlled so that only one access is required.
[0088]
When an error is detected in the read data of the main memory 14, the bit position where the error has occurred is specified from the error detection result by the horizontal parity of the main memory 14 and the block parity data, and correct data is reconstructed. Then, it is written back to the main memory 14. Specifically, all unit data blocks of the data block group to which the error detected data belongs are read from the main memory 14, and the correct block data group is reproduced from the corresponding block parity data.
[0089]
In the third embodiment, generation of block parity data and read / write control of update history information for the before image buffer (BIB) 17 are realized by hardware similar to that of the first embodiment described with reference to FIG. That is, the operation will be described by replacing the redundant code memory 16 in the system of FIG. 5 with the block parity memory 22. When block parity data is written to the block parity memory 22, data is written back from the cache memory to the main memory 14. In parallel with the write back processing, the code memory controller 106 automatically executes the processing. Also, the update history information is written to the before image buffer (BIB) 17 when the data is written to the cache memory, that is, before the data is written back from the cache memory to the main memory 14, the bus transaction issuance control unit 103, It is automatically executed by the buffer access controller 104 and the code memory controller 106.
[0090]
Also, the failure recovery process in the third embodiment can be performed in the same procedure as in the first embodiment described with reference to FIGS. That is, when restoring the contents of the main memory 14 to the checkpoint state before the failure occurs, the correct data is reconstructed using the block parity data, and then the update history information is received from the before image buffer (BIB) 17. A process of sequentially reading and writing back the pre-update data block group and the block parity data to the corresponding storage positions in the main memory 14 and the block parity memory 22 is performed.
[0091]
The case where the data in the main memory has parity and can detect a 1-bit error has been described above, but the same configuration is possible when the SEC-DED code is used. In this case, when a 2-bit error is detected when reading data from the main memory, the correct data is reconstructed by the same method as described above, and the failure can be recovered.
[0092]
In the above description, in any embodiment, the before-update data and the corresponding error correction redundant code (ECC, vertical parity, block parity) are simultaneously written in the before image buffer (BIB) 17. However, the redundant code may be performed when the redundant code memory 16, the vertical parity memory 21, or the block parity memory 22 for storing the redundant code is updated. In this case, a redundant code updated by writing a new redundant code is read from the redundant code memory 16, the vertical parity memory 21, or the block parity memory 22, and is written in the before image buffer (BIB) 17.
[0093]
【The invention's effect】
As described above, according to the present invention, a memory subsystem having an error correction function can be constructed with additional hardware while using resources such as an existing memory with parity as it is. A high computer system can be realized. In addition, processing can be continued even when a memory failure occurs that cannot be recovered by the checkpoint restart method using log memory, and sufficient fault-tolerant performance is achieved with less hardware without duplicating memory. Can be realized.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of a computer system according to a first embodiment of the present invention.
FIG. 2 is a view for explaining an error correction code writing operation to a redundant code memory in the system according to the first embodiment;
FIG. 3 is a view for explaining an update history information writing operation to a BIB memory in the system according to the first embodiment;
FIG. 4 is a view for explaining the restoration operation of the main memory and the redundant code memory in the system according to the first embodiment;
FIG. 5 is a block diagram showing a specific hardware configuration employed in the system of the first embodiment.
6 is a timing chart illustrating a series of operations executed in a write-back process from a cache to a main memory in the system of FIG.
7 is a timing chart for explaining a series of operations executed in a writing process for a shared line in a cache in the system of FIG.
FIG. 8 is a flowchart for explaining a first procedure of failure recovery processing executed in the system of FIG. 5;
FIG. 9 is a flowchart for explaining a second procedure of failure recovery processing executed in the system of FIG. 5;
FIG. 10 is a block diagram showing a configuration of a computer system according to a second embodiment of the present invention.
FIG. 11 is a view for explaining the generation principle of vertical parity data in the system of the second embodiment;
FIG. 12 is a block diagram showing a configuration of a computer system according to a third embodiment of the present invention.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 10 ... Processor bus, 11-1 to 11-n ... CPU, 12-1 to 12-n ... Cache memory, 13 ... Main memory controller, 14 ... Main memory, 15 ... BIB / CM controller, 16 ... Redundant code memory ( CM), 17 ... before image buffer (BIB), 21 ... vertical parity memory, 22 ... block parity memory, 101 ... bus interface control unit, 102 ... bus transaction response control unit, 103 ... bus transaction issue control unit, 104 ... buffer Access controller 105... State storage control unit 106.

Claims (7)

In a computer system having one or more CPUs and a main memory with parity that is connected to the CPUs via a bus and stores data with added parity ,
Cache memory,
A memory controller that is provided between the bus and the main memory and controls the main memory;
Data having a plurality of storage areas provided corresponding to each address serving as a unit of read / write access to the main memory , and stored in the address of the main memory corresponding to the storage area in each storage area a redundant code memory for holding a correctable redundancy code error occurring in a part of,
A control device that is provided between the bus and the redundant code memory and controls the redundant code memory, monitors a bus transaction issued on the bus, and writes data from the cache memory to the main memory When back-up is executed, a redundant code corresponding to the data is generated from the data value on the bus, and the redundant code is stored in the storage area of the redundant code memory corresponding to the unit data write address. A control device;
When a data error in the read data is detected by the memory controller when the data is read from the main memory, the read data and the redundant code stored in the redundant code memory corresponding to the read data are used. A computer system comprising: error correction means for reconstructing correct data . A log memory connected to the control means for storing update history information of the main memory;
The control means, before executing the data write to the main memory by the CPU, the pre-update data of the main memory corresponding to the address where the data write is executed and the redundant code corresponding to the pre-update data Means for respectively reading from the main memory and the redundant code memory, storing the pre-update data and the redundant code in the log memory as the update history information,
When a failure that requires restoring the contents of the main memory to the state before the failure occurs, the pre-update data and redundant code constituting each update history information stored in the log memory are stored in the main memory and Rewriting to the redundant code memory to restore the main memory to a state before the occurrence of a failure, and further to returning the contents of the redundant code memory to a state corresponding to the restored contents of the main memory The computer system according to claim 1. The control means includes
When data is written to the cache memory by the CPU, the pre-update data of the main memory corresponding to the address where the data is written and the redundant code corresponding to the data are updated from the main memory and the redundant code memory. 3. The computer system according to claim 2, wherein each of the data is read and the pre-update data and redundant code are stored in the log memory as the update history information. A computer system having one or more CPUs and a main memory with parity connected to the CPUs via a bus and storing parity-added data, and information necessary for failure recovery at each checkpoint In a computer system that stores in a main memory and restores the contents of the main memory to a checkpoint before the occurrence of a failure using update history information stored in the log memory when a failure occurs,
Cache memory,
A memory controller that is provided between the bus and the main memory and controls the main memory;
Corresponding to each address as a unit of read / write access to the main memory A redundancy having a plurality of storage areas provided and holding a redundancy code capable of correcting an error occurring in a part of the data stored in the address of the main memory corresponding to the storage area in each storage area Code memory,
A log memory for storing update history information of the main memory;
A controller connected to the bus, the redundant code memory, and the log memory to control the redundant code memory and the log memory, and monitors a bus transaction issued on the bus; When write back to the main memory is executed, a redundant code corresponding to the data is generated from the value of the data on the bus, and the redundant code is stored in the redundant code memory corresponding to the unit data write address. Means for storing in a storage area, and when data write to the cache memory by the CPU is executed, the pre-update data of the main memory corresponding to the address where the data write is executed, and a redundant code corresponding thereto Read from main memory and redundant code memory respectively , A control device and means for storing the log memory them pre-update data and the redundant code as the update history information,
If a data error in the read data is detected by the memory controller when reading data from the main memory, the read data and the redundant code stored in the redundant code memory corresponding to the read data are used. Error correcting means for reconstructing correct data and writing the reconstructed data into the main memory;
When a failure that requires restoring the contents of the main memory to the state before the failure occurs, the pre-update data and redundant code constituting each update history information stored in the log memory are stored in the main memory and Means for respectively writing back to the redundant code memory to restore the main memory to the state before the failure, and to return the contents of the redundant code memory to a state corresponding to the contents of the restored main memory. A computer system characterized by that. In a computer system having one or more CPUs and a main memory with parity connected to the CPUs via a bus and having an error detection function based on parity for each data string serving as a read / write access unit,
Cache memory,
A memory controller that is provided between the bus and the main memory and controls the main memory;
A unit data block corresponding to the storage area in each storage area, the storage area having a plurality of storage areas provided corresponding to each unit data block composed of a plurality of continuously accessed data strings in the main memory; A vertical parity memory that holds vertical parity data for the same bit position of each of a plurality of data strings belonging to
A control device that is provided between the bus and the vertical parity memory and controls the vertical parity memory, monitors a bus transaction issued on the bus, and unit data from the cache memory to the main memory When block write-back is executed, the vertical parity data corresponding to the unit data block is generated from the value of the unit data block on the bus, and the vertical parity data corresponding to the unit data block is generated. A controller for storing in a storage area of the parity memory;
When a data error in the read data is detected by the parity check by the memory controller at the time of reading data from the main memory, the unit data block to which the data in which the data error is detected belongs and the unit data block A computer system comprising means for reconstructing a correct unit data block from the vertical parity data of the vertical parity memory. One or more CPUs, one or more CPUs, a main memory with parity connected to the CPUs via a bus and storing parity-added data, a cache memory, and between the bus and the main memory And a memory controller for controlling the main memory and a unit of read / write access to the main memory It has a plurality of storage areas provided corresponding to each address, and can correct an error occurring in a part of the data stored in the address of the main memory corresponding to the storage area in each storage area Provided between the redundant code memory that holds the redundant code, the bus and the redundant code memory, monitors a bus transaction issued on the bus, and executes write-back from the cache memory to the main memory A controller that generates a redundant code corresponding to the data from a value of the data on the bus and stores the redundant code in a storage area of the redundant code memory corresponding to a write address of the unit data; A failure recovery method for a computer system comprising:
When a data error in the read data is detected by the memory controller when the data is read from the main memory, the read data and the redundant code stored in the redundant code memory corresponding to the read data are used. Rebuild the correct data,
A failure recovery method comprising writing the reconstructed data into the main memory. A log memory connected to the control means and storing update history information of the main memory is further provided, and the control means executes data writing before data writing to the main memory by the CPU is executed. The pre-update data of the main memory corresponding to the address and the redundant code corresponding to the pre-update data are read from the main memory and the redundant code memory, respectively, and the pre-update data and redundant code are read as the update history information in the log. Including means for storing in memory;
When a failure that requires restoring the contents of the main memory to the state before the failure occurs, the pre-update data and redundant code constituting each update history information stored in the log memory are stored in the main memory and Each of the redundant code memories is written back to restore the main memory to a state before the failure, and the contents of the redundant code memory are restored to a state corresponding to the restored contents of the main memory. The failure recovery method according to claim 6.

Images