JP3725046B2 - Semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor integrated circuit excellent in reliability and mass productivity and having a high degree of integration, and a manufacturing method thereof.
[0002]
[Prior art]
In recent years, a polycrystalline or substantially monocrystalline film of a semiconductor is further formed on a semiconductor circuit formed on a single crystal semiconductor substrate as in the past, and a semiconductor circuit is formed thereon. Semiconductor integrated circuits with increased integration levels have been developed. A typical example is a fully CMOS static RAM (SRAM) having two layers of MOS transistors (that is, a MOS transistor on a single crystal substrate and a thin film transistor thereon). Conventional full CMOS SRAM requires two sets of CMOS (ie, two NMOS and two PMOS) and two driver NMOSs per memory cell, and thus requires a large area. . Therefore, it is replaced by a so-called high resistance type SRAM in which high resistance polycrystalline silicon is used instead of PMOS, and this is three-dimensionally arranged with respect to the transistor to increase the degree of integration. It was. However, as higher integration progresses, the leak current is too large in the method using a load, which is a linear element, so that the conventional full CMOS type using a PMOS, which is a non-linear element, is adopted again. I went to. However, in terms of the degree of integration, the conventional planar method cannot be adopted, so that the PMOS is used as a thin film transistor and is three-dimensionally arranged as it is now.
[0003]
Further, such a three-dimensional arrangement not only increases the degree of integration, but also provides other advantages. One of them is that the elements can be easily separated, and the latch-up phenomenon which causes a problem in the conventional CMOS monolithic integrated circuit does not occur. That is, in such a three-dimensional arrangement, since the PMOS is completely separated from the substrate and the NMOS, there is no room for a parasitic transistor to be generated via the NMOS adjacent to the substrate. Up is never possible.
[0004]
[Problems to be solved by the invention]
For these reasons, an integrated circuit having a multilayer structure (hereinafter referred to as a three-dimensional integrated circuit or a three-dimensional IC) has been formed. However, since the conventional three-dimensional integrated circuit uses the same manufacturing process as that of an integrated circuit on a normal semiconductor substrate, the number of masks required for manufacturing increases. For example, to form a CMOS inverter circuit with a three-dimensional integrated circuit having three layers of polycrystalline silicon and one layer of aluminum wiring, a first-layer MOS transistor (a polycrystalline silicon gate using a first polysilicon layer is used). In addition, the following process was required. That is,
(1) Formation of first interlayer insulator
(2) Formation and etching of the second polycrystalline silicon layer (1)
(3) Formation of gate insulating film
(4) Formation of a hole for connecting to the gate wiring of the first MOS transistor in the interlayer insulator (2)
(5) Formation of gate electrode (third polycrystalline silicon layer) of second transistor (3)
(6) Impurity ion implantation
(7) Formation of second interlayer insulator
(8) Formation of holes for source and drain electrodes in the second interlayer insulator (4)
(9) Formation of holes for source and drain electrodes in the first interlayer insulator (5)
(10) Formation of source and drain electrode wirings (6)
(11) Formation of passivation film
[0005]
Here, the circled numbers represent the mask number / number. That is, at least six masks are required. In order to add more value, more masks are required. In particular, in the processes of (7) and (8), in the case of a CMOS inverter, since wiring must be performed separately on the ground side and the drain voltage supply side, for example, a CMOS transfer gate circuit can be used. In this case, both the NMOS and PMOS impurity regions are combined. Therefore, in such a case, the NMOS impurity region is usually formed so as to overlap the PMOS impurity region. Therefore, if only the NMOS impurity region and the PMOS impurity region are connected, the two steps are bothered. You may think that there is no need to divide. Certainly, it can be considered that if a hole is made with one mask through the source or drain of NMOS and PMOS, contact can be made with both.
[0006]
However, the thickness of the impurity region layer of the PMOS has been found to be better as the thickness is reduced in recent research. Usually, a very thin thickness of 100 nm or less, and in some cases, 20 nm may be used. Therefore, simply forming a hole penetrating between one impurity region is not sufficient. Typically, assuming that the hole radius is 2 μm and the thickness of the PMOS impurity region is 100 nm, the area of the electrode formed in the NMOS is about 12.6 μm.²On the other hand, the area of the “electrode” in the PMOS impurity region is one-tenth of 1.3 μm.²Only it is. Since it is a CMOS, although it consumes less power, it has a too small electrode area and cannot withstand normal operation.
[0007]
Therefore, although it is troublesome, a hole is purposely made in the second interlayer insulator to form a hole for forming an electrode in the impurity region of the PMOS, and then the second and first interlayer insulators are formed. It is necessary to form a hole for forming an electrode in the impurity region of the NMOS so that the area of the electrode portion is almost the same size.
[0008]
Further, when the thickness of the impurity region of the PMOS is very thin, such as 50 nm or less, sufficient attention is required for forming a hole in the second interlayer insulator. In general, the interlayer insulator is 200 nm or more in consideration of its insulating characteristics and parasitic capacitance between lower and upper wirings. Actually, the previously formed gate oxide film remains, and in the case of a thin film transistor, the gate oxide film is formed to a thickness of 50 to 200 nm. An oxide with a thickness of 250 to 400 nm or more is present.
[0009]
And, in order to make a hole in such an interlayer insulator, a plasma vapor phase etching method is adopted, but even if the etching selectivity between silicon oxide and silicon is sufficiently large, if plasma etching is not performed accurately, There is a risk that a hole penetrating through the silicon film may be formed by mistake. In particular, it is relatively easy to form a hole in a flat part, but in the formation to a curved surface, for example, the thickness of the interlayer insulator itself varies depending on the location. It is extremely difficult to finish with.
[0010]
Needless to say, it is essential to reduce the mask process in order to increase the manufacturing yield of semiconductor integrated circuits and to reduce costs. An object of the present invention is to improve the yield by further reducing the number of masks. Another object of the present invention is to cover the wiring with an insulating film having excellent pressure resistance, and thus prevent a short circuit with the upper wiring.
[0011]
[Means for solving the problems]
In the present invention, an upper-layer thin film transistor (also referred to as a second MOS transistor, which corresponds to a PMOS in the previous example, needless to say, may be an NMOS), which has been conventionally used. Is an aluminum gate electrode, and its surface is oxidized by an anodic oxidation method to form a high breakdown voltage oxide layer, which is used in place of an interlayer insulator to reduce the number of masks, and between wirings. Improve pressure resistance.
[0012]
That is, in the present invention, if the same CMOS inverter circuit as that of the previous example is to be configured, the following process is required after forming the NMOS on the semiconductor substrate. However, in this example of the present invention, since the gate electrode of the PMOS is aluminum, it becomes “two-layer polycrystalline silicon, two-layer aluminum wiring”.
(1a) Formation of interlayer insulator
(2a) Formation / etching of second polycrystalline silicon layer (1)
(3a) Formation of gate insulating film
(4a) Formation of an interlayer insulator for connection to the gate wiring of the first MOS transistor (2)
(5a) Formation of gate electrode (first aluminum layer) of second transistor (3)
(6a) Anodization of gate electrode / wiring surface
(7a) Impurity ion implantation
(8a) Removal of gate insulating film and exposure of impurity region of PMOS
(9a) Formation of holes for source and drain electrodes in the interlayer insulator (4)
(10a) Formation of source and drain electrode wirings using the second aluminum layer (5)
(11a) Formation of passivation film
[0013]
As described above, the number of steps was not changed, but the number of masks could be reduced by one. In particular, as described above, the reduced mask process is the most difficult process, and the yield is remarkably increased by omitting this process. Instead of the process (8) of the conventional example, in the present invention, there is a process (8a), which does not contain silicon and aluminum oxide and does not contain silicon oxide like hydrofluoric acid, for example. Etching may be performed with a solution that dissolves. In this step, a part of the interlayer insulator formed earlier is eroded, but if the interlayer insulator is formed thicker than the gate oxide film, the interlayer insulator is eroded by this step. Thus, the underlying semiconductor substrate and polycrystalline silicon are not exposed.
[0014]
In particular, in order to positively prevent the exposure of the first polycrystalline silicon layer (where the gate wiring / electrode of the first MOS transistor is formed), it overlaps the first polycrystalline silicon wiring / electrode. In this way, the wiring by the first aluminum layer (the gate wiring / electrode of the second MOS transistor is formed) may be formed. That is, since the aluminum wiring is anodized, the surface is replaced with insoluble aluminum oxide, and the underlying object is not easily eroded.
[0015]
Similarly, when a CMOS transfer gate circuit is to be configured with two-layer polycrystalline silicon and two-layer aluminum wiring, the following process is required after forming an NMOS on a semiconductor substrate.
(1b) Formation of interlayer insulator
(2b) Formation / etching of second polycrystalline silicon layer (1)
(3b) Formation of gate insulating film
(4b) Formation of gate electrode (first aluminum layer) of second transistor (2)
(5b) Anodization of gate electrode / wiring surface
(6b) Impurity ion implantation
(7b) Removal of gate insulating film and exposure of impurity region of PMOS
(8b) Formation of holes for source and drain electrodes in the interlayer insulator (3)
(9b) Formation of source and drain electrode wirings using the second aluminum layer (4)
(10b) Formation of passivation film
[0016]
That is, the step (4a) required in the CMOS inverter step is not required. In the CMOS transfer gate circuit, it is not necessary to connect the gates of the NMOS and PMOS, so this step is unnecessary. After all, it is completed with four masks. This is the same with the conventional method, and even in the manufacture of the conventional three-dimensional integrated circuit, the mask is manufactured with a total of five masks, which is one mask less than in the case of the inverter.
[0017]
In the present invention, a circuit with higher reliability can be formed even if the number of masks is the same as the conventional one. The process for producing the same inverter by the method is as follows.
(1c) Formation of first interlayer insulator
(2c) Formation / etching of second polycrystalline silicon layer (1)
(3c) Formation of gate insulating film
(4c) Formation of a hole for connection to the gate wiring of the first MOS transistor in the interlayer insulator (2)
(5c) Formation of gate electrode (first aluminum layer) of second transistor (3)
(6c) Anodization of gate electrode / wiring surface
(7c) Impurity ion implantation
(8c) Formation of second interlayer insulator
(9c) Formation of holes for source and drain electrodes in the second interlayer insulator (4)
(10c) Formation of holes for source and drain electrodes in the second interlayer insulator (5)
(11c) Formation of source and drain electrode wirings using the second aluminum layer (6)
(12c) Formation of passivation film
[0018]
As described above, the number of processes is increased, and the number of mask processes is not different from the conventional one. However, in the circuit formed in this way, the surface of the gate electrode / wiring of the second transistor is particularly an anodized film and an interlayer insulator. In particular, since the anodic oxide film is honey and excellent in pressure resistance, it is effective in preventing a short circuit when an unexpectedly high voltage is applied between the wirings.
[0019]
Conventionally, silicon oxide used as an interlayer insulator cannot completely cover the undulations of the wiring, and the thickness is thick or thin, especially on the side of the gate wiring that is the lower wiring. It became thin. On the other hand, a sufficiently thick film was formed on the upper surface of the lower wiring. This variation in thickness led to peeling of the interlayer insulator due to subsequent heat treatment or the like. When the upper wiring is formed in this state, a short circuit is likely to occur on the side surface of the lower wiring. However, according to the present invention, the anodic oxide insulating film having substantially the same thickness can be formed on the side surface and the upper surface of the lower wiring, and thus such a problem is solved.
[0020]
In the present invention, the gate electrode of the second MOS transistor is aluminum that contains almost no impurities or pure aluminum, but the strength is insufficient. For example, when the mechanical force such as electromigration is weak, aluminum A film is formed using an alloy or the like obtained by adding 1 to 10% of silicon. Titanium or tantalum may be used instead of aluminum. An oxide film of these metals can be formed by an anodic oxidation method (anodization method), and the oxide film is excellent in pressure resistance. However, it should be noted when selecting this metal that titanium oxide and tantalum oxide have a significantly higher relative dielectric constant than aluminum oxide. Therefore, when these materials having a high dielectric constant are used as the interlayer insulator, the dielectric loss may increase. In addition, tantalum and titanium have a higher resistivity than aluminum, which must be considered in selecting materials. Further, since titanium and tantalum have excellent heat resistance, these materials are preferably used when the temperature becomes high in a later manufacturing process.
[0021]
In particular, when aluminum is used when the second transistor is a PMOS, there is almost no off-state channel formation (ie, less leakage current) due to the relationship between the work function of aluminum, the work function of silicon, and the energy level. It becomes an extremely reliable MOS transistor.
[0022]
When titanium or tantalum is used instead of aluminum, the adhesion between these materials and the underlying oxide film must also be considered. In general, the adhesion between these materials and silicon oxide is not good. Therefore, it is necessary to make a gate insulating film as a multilayer film to eliminate the discontinuity of adhesion, but this is not desirable because it complicates the process.
[0023]
As an anodic oxidation method, there are a solution method and a plasma method. The solution method is a method in which an entire substrate is immersed in an electrolytic solution, a gate wiring is connected to a power source, anodization is performed through direct current or alternating current, and an oxide film is formed on the surface of the gate wiring, gate electrode, or the like. . A film of aluminum oxide is formed when aluminum is used as a material for the gate wiring or the like, a film of titanium oxide is formed when titanium is used, and a tantalum oxide film is formed when tantalum is used. These oxide films are not purely made of metal and oxygen, but contain elements constituting the electrolyte inside or become hydrates, so that their physical properties change. For example, when an organic acid is used as the electrolyte, carbon is contained in the oxide film, and when sulfuric acid is used, sulfur is contained. The use of materials containing alkali metal ions in the electrolyte should be avoided. This is because alkali metal ions (sodium and potassium), when entering the semiconductor region, cause significant damage to the conductive properties of the semiconductor.
[0024]
In addition, for example, when only a specific gate wiring is connected to the power supply and the other gate wiring is not connected, an oxide film is formed only on the gate wiring connected to the power supply. An oxide film is not substantially formed other than the natural oxide film. Or you may change the time, electric current, voltage, etc. which energize each. In this way, the thickness of the oxide film to be formed can be changed. For example, when it is used as an interlayer insulator, it is desirable that the film thickness is large in order to reduce the capacitance between the wirings, while on the other hand, when it is used as an insulator of a capacitor, it is desirable that the film is thin. When there is a difference in such purposes, it is effective to use the above method.
[0025]
In this way, when the wiring or the like is covered with the oxide film, the substrate is taken out of the solution and dried well. If necessary, the oxide film may be modified by exposure to hot water or high-temperature steam. That is, in the anodic oxidation method, the obtained film is a porous film under the condition for obtaining a particularly thick oxide film. Although such a film is thick, there may be a problem with the withstand voltage, and a current may be short-circuited through a hole in a later process. In such a case, the pores may be closed by reacting the oxide film with high-temperature water to form a hydrate and expanding the volume. In this way, a dense and good insulating film can be obtained. In any case, it is necessary to sufficiently wash and dry the electrolyte so that it does not remain on the coating. In this way, FIG. 1C is obtained.
[0026]
Further, as a method for anodization, a method in plasma may be adopted in addition to a method in a normal acid solution. The solution-based method is inexpensive and can be processed in large quantities at a time. However, for example, mobile ions such as sodium can easily enter. Especially in submicron and quarter micron devices, such ions can Existence is fatal. On the other hand, the plasma anodic oxidation method is an extremely clean method compared to the method using a solution. However, it has the disadvantages that it lacks mass productivity and it is difficult to form a thick oxide film.
[0027]
The thickness of the anodic oxide film must be determined according to its purpose. Usually, since it is expected to function as an interlayer insulator, the thickness is 0.1 to 0.6 μm, preferably 0.2 to 0.5 μm.
[0028]
The effects brought about by the present invention are not limited to those described above. For example, in a typical three-dimensional integrated circuit, it has hardly been provided with a low concentration drain (LDD) region in a thin film transistor. This is not only because the process is complicated, but when an LDD region is formed by a conventional method, a side wall that is important in determining the width of the LDD region is formed by directional etching of a thick insulating film. Whereas the thin film transistors exist in the three-dimensional integrated circuit, the area of the thin film transistors is particularly undulating, and the same size is obtained regardless of the location. This is because the side wall could not be obtained.
[0029]
Therefore, the conventional thin film transistor usually has a typical MOS transistor structure as shown in FIG. This was formed as follows. First, a gate insulating film 801 is formed on the surface of a thin semiconductor region, a gate electrode 802 is formed thereon, and an impurity region 803 is formed in a self-aligned manner by ion implantation using the gate electrode as a mask. After that, an interlayer insulator 804 was formed. In the thin film transistor formed in this manner, as shown in FIG. 8B, impurities inevitably enter the lower part of the gate electrode due to secondary scattering of ions during ion implantation. Only in the region of length L, a portion where the gate electrode and the impurity region overlap was formed. Such an overlap becomes a parasitic capacitance and causes the operation of the MOS transistor to be dull.
[0030]
On the other hand, if this invention is utilized, such a problem will be solved. FIG. 3 shows a method for manufacturing a thin film transistor using the present invention. That is, as shown in FIG. 3A, a gate insulating film 301 is formed over a thin-film semiconductor region, a gate electrode 302 is further formed, and an impurity region 303 is formed in a self-aligning manner. The impurity region 303 usually goes under the gate electrode. So far, it is the same as the conventional example. However, according to the present invention, the situation is different when the surface of the gate electrode is then anodized. By anodic oxidation, an oxide film 304 is formed as shown in FIG. 3B, but the surface of the gate electrode is retreated by this oxidation. Considering secondary scattering of ions by ion implantation and receding of the gate electrode surface due to anodic oxidation, a state in which the impurity region and the gate electrode hardly overlap is realized as shown in FIG. Since the degree of secondary ion scattering and anodization can be calculated fairly accurately by simulation and experience, it is possible to realize a substantially non-overlapping state. It is also possible to overlap by an arbitrary width or to separate by an arbitrary width.
[0031]
FIG. 4 is another example. First, as shown in FIG. 4A, a gate insulating film 401 and a gate electrode 402 are formed over a thin semiconductor region 403. Then, as shown in FIG. 4B, anodization is first performed to form an oxide 404 around the gate electrode. Then, as shown in FIG. 4C, ion implantation is performed to form an impurity region 405. At this time, the impurity region and the gate electrode do not overlap each other and are in a separated state (offset state). In particular, in a thin film transistor, off-state current (leakage current) via a grain boundary may be a problem, but the off-state current can be significantly reduced by setting the offset state in this way. In addition, when a reverse voltage was applied to the gate electrode, in the thin film transistor, a phenomenon in which a current often flows (reverse leakage) was observed, but it has become clear that this can also be suppressed. Since the offset length L is suitably 0.2 to 0.5 μm, the ion implantation energy and the thickness of the anodic oxide film may be determined so as to realize such conditions. At this time, the value of L can be changed to an arbitrary value by changing these parameters.
[0032]
FIG. 5 shows an example of forming an LDD region according to the present invention. First, an impurity region 503 is formed as shown in FIG. Here, the impurity concentration of this impurity region is 1 × 10 5.¹⁷~ 5x10¹⁸cm^-3, Preferably 5 × 10¹⁷~ 2x10¹⁸cm^-3To be. Next, as shown in FIG. 5B, the gate electrode is anodized to form an oxide 504. Finally, as shown in FIG. 5C, ion implantation is performed again to form impurity regions. The impurity concentration of this impurity region is 1 × 10¹⁹~ 5x10^{twenty two}cm^-3, Preferably 5 × 10²⁰~ 2x10^{twenty one}cm^-3And Then, a low concentration impurity region 503 and a high concentration impurity region 505 are formed. In the present invention, since the anodic oxidation method is employed, the thickness of the oxide (which functions as a sidewall) is almost constant regardless of the inclination of the semiconductor region, and an LDD region can be obtained with extremely good reproducibility.
[0033]
FIG. 6 shows an example in which the laser annealing method is combined with the present invention. First, as shown in FIG. 6A, an impurity region 603 is formed by a conventional method. Then, the gate electrode is anodized to obtain an oxide 604. At this time, the impurity region is in an amorphous state or a microcrystalline state by ion implantation. Then, as shown in FIG. 6 (C), when laser light or a powerful electromagnetic wave equivalent thereto is irradiated from the upper surface, such amorphous or microcrystals are recrystallized, but the gate electrode and its surrounding oxides. The portion existing under the oxide 604 cannot be recrystallized. That is, a structure of N-type (P-type) region-amorphous N-type (P-type) region-I-type channel formation region-amorphous N-type (P-type) region-N-type (P-type) region is obtained. It has been confirmed by the present inventors that this structure can obtain an effect equivalent to that of providing an LDD region. Details thereof are the inventions of the present inventors and the like, and are described in detail in “Insulated Gate Type Semiconductor Device and Manufacturing Method thereof” filed on August 26, 1991 by Semiconductor Energy Laboratory Co., Ltd. .
[0034]
FIG. 7 is a combination of the offset region obtained by the present invention and the above amorphous region. That is, as shown in FIG. 7A, a gate insulating film 702 and a gate electrode 703 are formed over a semiconductor region 701, and the gate electrode is anodized to obtain an oxide 704. Next, as shown in FIG. 7B, an impurity region 705 is formed by ion implantation. Finally, laser annealing is performed as in FIG. Through the above steps, N-type (P-type) region-amorphous N-type (P-type) region-I-type offset region-I-type channel formation region-I-type offset region-amorphous N-type (P-type) region-N-type ( A structure called “P-type” region is obtained. The effect of the thin film transistor having this structure is a combination of FIG. 4 and FIG.
As described above, a thin film transistor having a very versatile structure is formed by the present invention. In order to form these various types of thin film transistors, almost no special technique or complicated process is required, and the base technology of the present invention, which is the anodic oxidation of the gate electrode, is based It will be easy to understand.
[0035]
The following examples illustrate the present invention in more detail and clarify its effects.
[0036]
【Example】
FIG. 1 shows this embodiment. In FIG. 1A, a first MOS transistor is already formed on a single crystal silicon wafer. That is, an N-type impurity region 101 having an LDD region is formed on a single crystal silicon surface exposed between element isolation regions (so-called LOCOS) 107, and a gate electrode 102 with a sidewall is formed thereon. . A gate wiring 108 extending from the gate electrode runs on the element isolation region 107. An interlayer insulator 103 is formed so as to enclose these electrodes and wirings. Then, there is a polycrystalline silicon film 104 selectively formed to form a second MOS transistor and a gate oxide film 105 formed by thermal oxidation thereon, and an interlayer insulator on the gate wiring 108 includes A hole 106 for connecting the gate wiring is formed.
[0037]
Next, as shown in FIG. 1B, the gate electrode 109 of the aluminum second transistor and the gate wiring 110 connected thereto are formed so as to overlap with the gate electrode wiring of the first transistor. The gate wiring 108 of the first transistor and the gate wiring 110 of the second transistor are connected through the hole 106.
[0038]
Then, the gate electrode of the second transistor is anodized. Anodization was performed by the following procedure. Here, it should be noted that the numerical values used in the following description are merely examples, and optimum values are determined depending on the size of the element to be manufactured. That is, the numerical values used in the following description are not absolute. First, an ethylene glycol solution of tartaric acid having a sufficiently low alkali ion concentration was prepared. The concentration of tartaric acid was 0.1 to 10%, for example, 3%, and 1 to 20%, for example, 10% ammonia water was added thereto to adjust the pH to 7 ± 0.5.
[0039]
A platinum electrode was provided as a cathode in the solution, and the silicon wafer was immersed in the solution. Then, the gate wiring / electrode on the wafer was connected to the positive electrode of the DC power supply. At first, the current was made constant at 2 mA. The voltage between the anode and the cathode (platinum electrode) varies with time depending on the concentration of the solution and the thickness of the oxide film formed on the gate electrode / wiring. Generally, as the thickness of the oxide film increases , High voltage is required. In this way, the current was continuously supplied, and when the voltage reached 150 V, the voltage was kept constant and the current was continuously supplied until the current reached 0.1 mA. The constant current state lasted for about 50 minutes and the constant voltage state lasted for about 2 hours. In this manner, an aluminum oxide film 111 having a thickness of 0.3 to 0.5 μm could be formed on the surface of the gate electrode / wiring. The aluminum oxide film thus formed was sufficiently dense by itself, but was kept in hot water for 10 minutes in order to further increase the insulating properties. By this process, a high withstand voltage film of 6 to 12 MV / cm could be formed.
[0040]
Thereafter, boron ions or boron compound ions (for example, BF) are used by a known ion implantation method using the gate electrode 109 as a mask.₂ ⁺). Thus, the P-type impurity region 112 is formed. Further, the wafer is thermally annealed to recrystallize the impurity region.
[0041]
Thereafter, the substrate is immersed in a hydrofluoric acid solution, for example, 1/10 hydrofluoric acid, and the gate oxide film (silicon oxide) 105 is etched to expose the surface of the semiconductor region 112. At this time, since the aluminum oxide is insoluble in hydrofluoric acid, the silicon oxide film under the gate electrode / wiring is not removed and remains as it is. However, care must be taken because the silicon oxide film under the gate electrode / wiring is dissolved if left in hydrofluoric acid for a long time.
[0042]
Finally, a hole 113 is formed in the impurity region 101 of the first transistor through the impurity region 112 of the second transistor, and an electrode / wiring 114 is formed in the transistor by using a metal material such as aluminum or chromium. To do.
[0043]
FIG. 2 shows a top view of the three-dimensional CMOS circuit obtained by the process of FIG. FIG. 2A shows a state in which the first transistor is formed, and FIG. 2B shows a state in which the second transistor is formed thereon and the connection between the transistors is completed.
[0044]
As described above, in the present invention, it is possible to form the upper wiring directly without forming an interlayer insulator on the second transistor. That is, the lower wiring is already covered with the oxide film. Therefore, one mask can be reduced at this stage as compared with the conventional method.
[0045]
However, such a method can be substantially problematic. In the example of FIG. 1, the interlayer insulator is only the oxide film of the lower wiring, but in that case, there is a problem in terms of thickness, and since such an oxide has a large dielectric constant, This causes an increase in inter-wiring capacitance. Therefore, an anodic oxide film is used, and an interlayer insulator is formed thereon as in the prior art. Good. That is, since the oxide formed by anodization is honey and has high pressure resistance, it is suitable for insulating separation between layers. Conventionally, since there is only one interlayer insulating layer, there is a problem with its pressure resistance. In particular, since there is a step at the wiring intersection, the interlayer insulator cannot cover this step, and cracks are generated. In many cases, a short circuit with the upper wiring is caused. However, in the present invention, there is no need to consider such a defect due to a step, which contributes to an improvement in yield. In adopting such a method, since the number of masks necessary for manufacturing the device is the same as the conventional one, it is not appropriate when the impurity region of the second transistor is extremely thin, but it is not less than 50 nm. In this case, mass production can be achieved without reducing the yield in the electrode forming step. Such a circuit is particularly suitable for high pressure applications.
[0046]
【The invention's effect】
According to the present invention, a three-dimensional integrated circuit can be manufactured with a smaller number of masks than before. Further, according to the present invention, a three-dimensional integrated circuit with higher reliability can be manufactured although the number of masks is not different from the conventional one. In particular, an object of the present invention is to improve the yield of a three-dimensional integrated circuit. In particular, in the three-dimensional integrated circuit, the formation of the source and drain electrodes of the thin film transistor is an advanced operation requiring accuracy of a width of 1 μm or less and a thickness of 10 nm or less, and defects caused by this process occur in other processes. It was significantly more than what it did. According to the present invention, since it is not necessary to make a hole in the thin film transistor, the yield is remarkably improved.
[0047]
On the other hand, particularly in a multilayer wiring integrated circuit, the occurrence of a defect due to a short circuit between a gate wiring and a signal line (source and drain wiring) is a serious problem. This is a defect caused directly by a handling problem, but indirectly, it is considered to be a defect of an interlayer insulator. In other words, silicon oxide used as an interlayer insulator cannot completely cover the undulations of the wiring, resulting in thick or thin portions of the thickness, especially on the side of the gate wiring that is the lower wiring. It became thin. On the other hand, a sufficiently thick film was formed on the upper surface of the lower wiring. When the upper wiring is formed in this state, a short circuit is likely to occur on the side surface of the lower wiring. However, according to the present invention, the anodic oxide insulating film having substantially the same thickness can be formed on the side surface and the upper surface of the lower wiring, and thus such a problem is solved. If an interlayer insulating film is formed as in the prior art after forming this anodized insulating film, the insulating effect can be further enhanced.
[0048]
The three-dimensional integrated circuit targeted by the present invention is not limited to CMOS. It will be apparent that an integrated circuit consisting only of NMOS or only PMOS can obtain the same effect if the present invention is used. Further, in the present invention, for ease of explanation, the example in which the first transistor is NMOS and the second transistor is PMOS is frequently used. However, even if the case is reversed, the basis of the present invention is denied. It will be clear that it is not.
[Brief description of the drawings]
FIG. 1 shows an example of a manufacturing process of a three-dimensional integrated circuit according to the present invention.
FIG. 2 shows an example of a three-dimensional integrated circuit manufactured according to the present invention.
FIG. 3 shows a thin film transistor according to the present invention and an example of a manufacturing process thereof.
FIG. 4 shows a thin film transistor according to the present invention and an example of a manufacturing process thereof.
FIG. 5 shows a thin film transistor according to the present invention and an example of a manufacturing process thereof.
FIG. 6 shows a thin film transistor according to the present invention and an example of a manufacturing process thereof.
FIG. 7 shows a thin film transistor according to the present invention and an example of a manufacturing process thereof.
FIG. 8 illustrates a thin film transistor by a conventional method and an example of a manufacturing process thereof.
[Explanation of symbols]
101 Impurity region of first MOS transistor
102 Gate electrode of first MOS transistor
103 Interlayer insulator
104 Semiconductor (silicon) coating
105 Gate oxide film of second MOS transistor
106 Hole for connecting gate electrode
107 Element isolation region (LOCOS)
108 Gate wiring of the first MOS transistor
109 Gate electrode of second MOS transistor
110 Gate wiring of second MOS transistor
111 Anodized film
112 Impurity region of second MOS transistor
113 Electrode forming hole in impurity region of first MOS transistor
114 Metal wiring

Claims (5)

An insulated gate field effect transistor formed on a semiconductor substrate;
An interlayer insulating film formed on the insulating gate type field effect transistor;
A thin film transistor formed on the interlayer insulating film;
The insulated gate field effect transistor has a gate electrode, a gate oxide film, and an impurity region, and the thin film transistor has a gate electrode , a gate oxide film formed under the gate electrode, and an impurity region,
The impurity region of the insulated gate field effect transistor is a semiconductor device connected to the impurity region of the thin film transistor through a wiring,
A gate wiring connected to the gate electrode of the thin film transistor;
The gate electrode and the gate wiring of the thin film transistor are each made of aluminum, titanium, or tantalum, and the upper surface and the side surface of each are covered with an oxide film that oxidizes the gate electrode of the thin film transistor and the gate wiring, respectively.
The wiring is connected to the inner side surface of the hole formed in the impurity region of the thin film transistor and the upper surface of the impurity region of the thin film transistor, and to the upper surface of the impurity region of the insulated gate field effect transistor, and on the gate wiring, the wiring A semiconductor device characterized by being disposed through an oxide film. An insulated gate field effect transistor formed on a semiconductor substrate;
An interlayer insulating film formed on the insulating gate type field effect transistor;
A thin film transistor formed on the interlayer insulating film;
The insulated gate field effect transistor has a gate electrode, a gate oxide film, and an impurity region, and the thin film transistor has a gate electrode , a gate oxide film formed under the gate electrode, and an impurity region,
The impurity region of the insulated gate field effect transistor is a semiconductor device connected to the impurity region of the thin film transistor through a wiring,
A gate wiring connected to the gate electrode of the thin film transistor;
The gate electrode and the gate wiring of the thin film transistor are each made of aluminum, titanium, or tantalum, and the upper surface and the side surface of each are covered with an oxide film that oxidizes the gate electrode of the thin film transistor and the gate wiring, respectively.
The wiring is connected to the inner side surface of the hole formed in the impurity region of the thin film transistor and the upper surface of the impurity region of the thin film transistor, and to the upper surface of the impurity region of the insulated gate field effect transistor, and on the gate wiring, the wiring Through the oxide film,
An impurity region of the thin film transistor is formed at a position where it does not overlap with a gate electrode of the thin film transistor. 3. The semiconductor device according to claim 1, wherein an LDD region is formed in the impurity region of the thin film transistor. The semiconductor device according to any one of claims 1 to 3, characterized in that the LDD region is formed in the impurity region of the insulated gate field effect transistor. The insulated gate field effect transistor and the thin film transistor semiconductor device according it to any one of claims 1 to 4, characterized in that a CMOS inverter circuit or a CMOS transfer gate circuits.

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