JP3725016B2 - Transmitter using non-linear distortion compensation circuit by negative feedback system - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a transmitter, and more particularly, to a negative feedback circuit that performs nonlinear distortion compensation and a phase control method thereof used in the transmitter.
[0002]
[Prior art]
In wireless systems using linear digital modulation methods such as 16QAM (Quadrature Amplitude Modulation) and π / 4 shift QPSK (Quadrature Phase Shift Keying), nonlinear distortion compensation of power amplifiers is essential, and various nonlinear distortion compensation methods (linearizers) ) Is used. Among them, the Cartesian loop negative feedback type linearizer has been used for a long time. A conventional linear feedback amplifier will be described with reference to FIG. FIG. 2 is a block diagram showing a configuration of a transmission unit of a digital radio using a Cartesian negative feedback linearizer system.
[0003]
The baseband signal generator 1 outputs an in-phase component (hereinafter referred to as I component) and a quadrature component (hereinafter referred to as Q component) of the baseband signal. Then, the I component is added to the feedback signal by the adder 2-1 to be output and input to the loop filter 3-1. Similarly, the Q component is added to the feedback signal by the adder 2-2 and output and input to the loop filter 3-2. The loop filters 3-1 and 3-2 band-limit the input I component and Q component, respectively, and input them to the quadrature modulator 4.
[0004]
The reference signal generator 11 generates a reference frequency signal and inputs the reference signal to the PLL frequency synthesizer 12 and the PLL frequency synthesizer 13. The PLL frequency synthesizer 12 generates a first local oscillation signal (hereinafter referred to as LO signal) based on the reference signal, and supplies the first LO signal to the quadrature modulator 4 and the phase shifter 18. Further, the PLL frequency synthesizer 13 generates a second LO signal based on the reference signal and supplies the second LO signal to the mixer 6 and the mixer 15. The phase shifter 18 controls the phase by a control signal input from the phase controller 19 to the first LO signal, and supplies the phase-controlled first LO signal to the quadrature demodulator 16.
[0005]
The quadrature modulator 4 modulates an input baseband signal I component I ′ and Q component Q ′ into a signal in an intermediate frequency band (hereinafter referred to as IF frequency band) by the first LO signal. The modulated modulated wave signal is supplied to a band pass filter (BPF) 5 and a signal obtained by removing unnecessary components from the inputted modulated wave signal is supplied to the mixer 6. The mixer 6 converts the input modulated wave signal into a desired frequency by the second LO signal output from the PLL frequency synthesizer 13, and supplies the frequency to the bandpass filter (BPF) 7. The band-pass filter 7 removes unnecessary spurious components from the input signal and supplies them to the power amplifier (PA) 8. The power amplifier 8 amplifies the input signal to a specified output level and transmits it through the antenna 9.
[0006]
Since this negative feedback amplifier has a configuration of a negative feedback linearizer based on a Cartesian loop, a part of the output signal of the power amplifier 8 is fed back to the attenuator (ATT) 14 by the directional coupler 10. The attenuator 14 adjusts the power level of the input signal to an appropriate value and supplies it to the mixer 15. The mixer 15 frequency-converts the signal input from the attenuator 14 to the IF frequency using the second LO signal, and provides the signal to the quadrature demodulator 16.
[0007]
The quadrature demodulator 16 outputs baseband signals q and i of I component and Q component by the first LO signal input from the phase shifter 18. The I component i is input as the I component of the feedback signal to the subtraction input side of the adder 2-1 via the switch 20-1, and the Q component q is input to the subtraction input side of the adder 2-2 via the switch 20-2. Is input as the Q component of the feedback signal. At this time, the output sides of the switches 20-1 and 20-2 are connected to the adders 2-1 and 2-2, respectively.
[0008]
In such negative feedback, in order to stabilize the system, the phases of the input signals I and Q and the feedback signals i and q are in phase (phase difference 0) on the input side of the adders 2-1 and 2-2. It is necessary to become. That is, when a phase difference occurs between the input signal and the feedback signal, the adders 2-1 and 2-2 need to control the phase shifted by a maximum of π radians to eliminate the phase difference.
[0009]
Next, a phase control method will be described. First, the output side of the switches 20-1 and 20-2 in FIG. 2 is switched and connected to the phase controller 19 side, and the feedback loop is brought into an open loop state. A predetermined DC voltage for phase adjustment is given only to the I component from the baseband signal generator 1, and the Q component is set to 0 (Q = 0), and is subjected to quadrature modulation according to the above-described operation and output from the antenna 9 To do. The output waveform of the power amplifier 8 at this time is an unmodulated carrier. When the output of the power amplifier 8 is partially fed back by the directional coupler 10 and the output of the feedback signal of the quadrature demodulator 16 is observed according to the above-described operation, if the phase is matched, the DC is only applied to the I component side. Voltage appears and no signal (DC) is output to the Q component side. However, when the phases are not matched, a DC voltage corresponding to the phase shift appears at the output of the Q component side. Therefore, the phase rotation angle can be obtained from the DC voltages of the I component and the Q component. The phase controller 19 controls the phase shifter 18 to rotate the phase corresponding to the calculated rotation angle, and adjusts the phase of the first LO signal to thereby adjust the feedback signal of the quadrature demodulator 16. The negative feedback is stabilized by combining the outputs. When the phase of the input signal and the feedback signal match, the output on the Q component side becomes 0. At that time, switches 20-1 and 20-2 are switched to the adders 2-1 and 2-2, and operate in a closed loop. Let
[0010]
[Problems to be solved by the invention]
In the above-described prior art, it is necessary to open and close the feedback loop every time the phase adjustment is performed. Therefore, since the loop is open during the phase adjustment, the phase cannot be adjusted for the phase change of the closed loop during continuous operation. In addition, the switching means is used to open and close the loop, and the phase is controlled by the DC voltage of the feedback signal on the input side of the switching means, so the voltage effect at the switching means is different between the open loop and the closed loop. Furthermore, when the compensation setting of the offset voltage of the system set in the closed loop state becomes an open loop, it becomes incompatible and accurate phase control cannot be performed. Furthermore, for example, even when the phase changes due to a change in phase characteristics due to temperature fluctuation or gain fluctuation, it is impossible to detect how much the phase change amount has occurred.
[0011]
If the operation is performed with the phase shifted, the phase margin of the entire system is lost, and an oscillation phenomenon may occur in the worst case. In the process, spurious is generated and the output operation characteristics are deteriorated.
For this reason, the transmission operation must be stopped and readjusted.
An object of the present invention is to provide a negative feedback amplifier that eliminates these drawbacks and does not deteriorate the output operation characteristics.
[0012]
[Means for Solving the Problems]
In order to achieve the above object, the present invention compares and compares the phase of the input baseband signal before adding the feedback signal and the phase of the signal before adding the feedback signal and before quadrature modulation. By controlling the phase of the second LO signal input to the quadrature demodulator that demodulates the feedback signal based on the information, phase control is always performed using the input signal during normal operation. As a result, a negative feedback amplifier has been realized in which the output operation characteristics are stably operated during normal transmission operation without using an open loop and always in a closed loop and without using a test signal for determining a phase state. Is.
[0013]
DETAILED DESCRIPTION OF THE INVENTION
An embodiment of the present invention will be described with reference to FIG. FIG. 1 is a block diagram showing a configuration of a negative feedback circuit of a quadrature modulation type transmitter using the present invention.
The baseband signal generator 1 outputs an I component and a Q component of the baseband signal. Then, the I component is added to the feedback signal by the adder 2-1 to be output and input to the loop filter 3-1. Similarly, the Q component is added to the feedback signal by the adder 2-2 and output and input to the loop filter 3-2. The loop filters 3-1 and 3-2 band-limit the input I component and Q component, respectively, and input them to the quadrature modulator 4.
[0014]
The reference signal generator 11 generates a reference frequency signal and inputs the reference signal to the PLL frequency synthesizer 12 and the PLL frequency synthesizer 13. The PLL frequency synthesizer 12 generates a first LO signal based on the reference signal and supplies the first LO signal to the quadrature modulator 4 and the phase shifter 18 '. Further, the PLL frequency synthesizer 13 generates a second LO signal based on the reference signal and supplies the second LO signal to the mixer 6 and the mixer 15. The phase shifter 18 'determines the phase of the first LO signal input from the PLL frequency synthesizer 12 according to the control signal (phase difference information and phase delay / lead information) input from the phase controller 17 as the first LO signal. To provide a quadrature demodulator 16 with the phase-controlled first LO signal.
[0015]
The quadrature modulator 4 modulates the first LO signal (carrier wave signal) into an IF frequency band signal using the I component I ′ and the Q component Q ′ of the input baseband signal. The modulated modulated wave signal is supplied to the bandpass filter 5. The band-pass filter 5 removes unnecessary components from the input modulated wave signal and supplies the signal to the mixer 6. The mixer 6 converts the input modulated wave signal into a desired frequency by the second LO signal output from the PLL frequency synthesizer 13, and supplies the frequency to the bandpass filter 7. The band-pass filter 7 removes unnecessary spurious components from the input signal and supplies them to the power amplifier 8. The power amplifier 8 amplifies the input signal to a specified output level and transmits it through the antenna 9.
[0016]
Since this negative feedback amplifier has a negative feedback linearizer configuration using a Cartesian loop, a part of the output signal of the power amplifier 8 is fed back to the attenuator 14 by the directional coupler 10. The attenuator 14 adjusts the power level of the input signal to an appropriate value and supplies it to the mixer 15. The mixer 15 frequency-converts the signal input from the attenuator 14 to the IF frequency using the second LO signal, and provides the signal to the quadrature demodulator 16.
[0017]
The quadrature demodulator 16 outputs baseband signals q and i of I component and Q component by the first LO signal input from the phase shifter 18, and the I component i is fed back to the subtraction input side of the adder 2-1. The I component of the signal is input, and the Q component q is input to the subtracting input side of the adder 2-2 as the Q component of the feedback signal, and negative feedback is applied to each of I and Q.
[0018]
Next, a phase error detection method will be described with reference to FIGS. 1, 3, 4 and 5. FIG. FIG. 3 is a time chart for explaining the operation of one embodiment of the phase control method of the present invention. FIG. 4 is a diagram for explaining an embodiment of the exclusive OR operation of the phase controller 17 (FIG. 1) of the present invention. FIG. 5 is a detailed block diagram of the phase controller 17 of FIG.
First, when the Q component which is the output of the baseband signal generator 1 in FIG. 1 is a signal as shown in FIG. 3A, when this signal and the reference voltage are input to the comparator 26 (FIG. 5), FIG. The signal of b) is obtained.
[0019]
Next, looking at the Q component input Q ′ of the quadrature modulator 4, when the phase is delayed, it becomes as shown in FIG. When this signal Q 'and the reference voltage are input to the comparator 21 (FIG. 5), the signal shown in FIG. 3 (d) is obtained. The exclusive OR gate 23 (FIG. 5) takes the exclusive OR of FIG. 3 (b) and FIG. 3 (d) to obtain the signal of FIG. 3 (e).
[0020]
Next, when the phase advances on the input side of the quadrature modulator 4, the result is as shown in FIG. When this signal and the reference voltage are input to the comparator 21, the signal shown in FIG. 3 (g) is obtained. When the exclusive OR of FIG. 3 (b) and FIG. 3 (g) is taken, the signal of FIG. 3 (h) is obtained.
Here, when the signals in FIG. 3 (e) and FIG. 3 (h) are viewed, it can be seen that data for the delay time (or advance time) is obtained. By counting the pulse width representing the time difference with the clock fclk (fclk = 2 MHz) by the counter 24, the delay amount can be measured and the phase deviation can be corrected.
[0021]
For example, in the case of a 4 kHz sine wave, if the 4 kHz sine wave is shifted by 1 degree (π / 180 radians), the output of the exclusive OR is “H” (high) level as shown in FIG. 694
Obtained as a pulse of nsec width.
The clock that can count 694 nsec is 1.44 MHz (≒ 1 / 0.000000694). Therefore, the clock is 2 MHz. When counting 250 μsec (4 kHz ≒ 1 / 0.000250) at 2 MHz, it is necessary to count 500 times (= 2000000/4000). Furthermore, counting 2 694 nsec at 2 MHz requires 2.8 counts. Accordingly, if the “H” level of the exclusive OR is 2.8 counts or more at 500 counts, the phase is changed by, for example, 1 degree (π / 180 radians).
[0022]
Next, the determination of the phase control direction will be described with reference to FIGS.
The direction for controlling the phase needs to be determined depending on whether the signal phase is clockwise or counterclockwise on the IQ coordinate. FIG. 6 shows a case where the signal phase is counterclockwise, and FIG. 7 shows a case where the signal phase is clockwise. Here, for example, when the Q component signal changes from − to +, if the I component signal is +, the phase rotation is clockwise, and if the I component is −, the phase rotation is counterclockwise. The phase control direction is determined by determining whether the I component is positive or negative at the zero cross point of the component signal.
[0023]
FIG. 6 shows a baseband phase transition of a specific pattern of the π / 4 shift QPSK modulation method. As shown in FIG. 6 (d), the constellation when the signal locus changes by + π / 4 radians is shown. Show. 6A shows the time waveform of the Q component signal, FIG. 6B shows the time waveform of the Q component at the loop filter output when the phase of the loop is delayed, and FIG. 6C shows the loop. The time waveform of the Q component at the output of the loop filter when the phase inside is advanced is shown. Similarly, FIG. 7 shows a constellation when the signal trajectory changes by −π / 4 radians as shown in FIG. 7D. 7 (a) shows the time waveform of the Q component signal, FIG. 7 (b) shows the time waveform of the Q component at the loop filter output when the phase of the loop is delayed, and FIG. 7 (c) shows the loop. The time waveform of the Q component at the output of the loop filter when the phase inside is advanced is shown.
[0024]
When the signal phase is counterclockwise as shown in FIG. 6, the peak point ta at the reference time t0 as shown in FIG. 6 (a) is changed in the loop as shown in FIG. 6 (b). When the phase is delayed from the reference time t0 like the peak point tb, the signal phase is counterclockwise, so the loop filter output is delayed in phase. As shown in FIG. 6C, when the phase in the loop advances from the reference time t0 as indicated by the peak point tc, the loop filter output is advanced in phase.
[0025]
Contrary to the case of FIG. 6, since the signal phase is clockwise in FIG. 7, the peak point ta at the reference time t0 as shown in FIG. 7 (a) is shown in FIG. 7 (b). As described above, when the phase in the loop advances from the reference time t0 as indicated by the peak point tb ′, the output of the loop filter is delayed in phase. Further, as shown in FIG. 7 (c), when the phase in the loop is delayed from the reference time t0 as indicated by the peak point tc ', the loop filter output is advanced in phase.
[0026]
This will be described with reference to FIG. FIG. 5 is a block diagram showing an embodiment of the phase controller 17 of the present invention. Reference numerals 31-1, 31-2, and 31-3 are input terminals, 32 is a reference voltage input terminal, and 21, 22 and 26 are comparators using a zero cross point input from the reference voltage input terminal 32 as a reference voltage. The comparator 21 inputs the Q component signal (Q ′) output from the loop filter 3-2 from the input terminal 31-1, and the comparator 22 inputs the I component signal (I) output from the baseband signal generator 1 to the input terminal 31. The comparator 26 inputs the Q component signal (Q) output from the baseband signal generator 1 from the input terminal 31-3, and outputs each result. 23 is an exclusive OR circuit, 24 is a counter, 25 is an up / down counter, 27 and 28 are flip-flops, 29 is an inverter, 30 is a switch, 33 is a control unit, 34 is an output terminal, 35 is a clock input terminal It is.
[0027]
First, the operation for obtaining the phase difference will be described.
In FIG. 5, the output of the comparator 21 is input to one input terminal of the exclusive OR circuit 23. The output from the comparator 26 is input to the flip-flop 28 and the other input terminal of the exclusive OR circuit 23. The output of the exclusive OR circuit 23 outputs a logical result as in the operation example described with reference to FIG. 3, and gives a pulse signal as shown in FIG. The counter 24 counts an “H” level pulse by a clock signal fclk (fclk = 2 MHz) that is separately input, and sends the count number to the control unit 33 as a phase difference count. In this way, the absolute value of the phase difference is not measured here, but the presence or absence of a phase shift from the reference value is detected. When the number of counters exceeds a certain value, it is determined that the phase is shifted, and the control unit 33 outputs a control signal for shifting the phase angle of the carrier signal by 1 degree (π / 180 radians). The amount of phase shift (phase adjustment amount) per time is not limited to 1 degree (π / 180 radians), but may be determined according to the required response characteristics of the system.
[0028]
Next, an operation for determining the direction in which the phase is shifted will be described.
In FIG. 5, the output of the comparator 26 is input to the flip-flop 27 and the up / down counter 25 in addition to being input to the flip-flop 28 and the exclusive OR circuit 23. The output of the comparator 21 is input to the flip-flop 28 in addition to being input to the exclusive OR circuit 23. Further, the output of the comparator 22 is input to the flip-flop 28. In the direction of shifting the phase, the flip-flop 27 latches the output of the comparator 21 with the output signal of the comparator 26, and determines the phase advance or phase delay according to the state of the I component signal at that time. Information on determination of phase advance or phase delay is output from the inverter 29 and the switch 30. The switch 30 is switched by the flip-flop 28 latching the output of the comparator 22 with the output signal of the comparator 26 to determine whether the I component is positive or negative when the Q component is zero-crossed, and the switch 30 is switched. The output of the switch 30 is input to the up / down counter 25. If the input signal is positive (+), it is determined to be delayed, and if the signal is negative (−), it is determined to be advanced and sent to the control unit 33. The control unit 33 generates a control signal for controlling the phase shift of the phase shifter 18 ′ from the input “phase difference” and “phase delay or advance”, and outputs two DC voltages from the output terminal 34. To do.
[0029]
Next, the phase shifter 18 ′ will be described with reference to FIGS.
FIG. 10 is a block diagram showing the configuration of an embodiment of the phase shifter 18 ′. Two DC voltages supplied from the phase controller 17 are supplied to the mixers 40-1 and 40-2 via the input terminals 17-1 and 17-2, respectively. Further, the first LO signal that is an output from the PLL frequency synthesizer 12 is supplied to the mixer 40-2 and the 90 ° phase shifter. The 90 ° phase shifter 42 shifts the phase of the first LO signal by 90 ° (π / 2 radians) and provides it to the mixer 40-1. The outputs of the mixer 40-1 and the mixer 40-2 are respectively supplied to the adder 41, added to the signal, and supplied to the quadrature demodulator 16.
[0030]
FIG. 11 is a diagram for explaining the operating principle of the phase shifter 18 ′. The horizontal axis represents the I component, and the vertical axis represents the Q component. In the operation of FIG. 10, as shown in FIG. 11, a DC voltage is applied to the I component and the Q component to perform quadrature modulation, and a signal equivalent to an unmodulated carrier signal is output. At this time, the initial phase angle θ can be varied by the voltages of the I component and the Q component, and an unmodulated carrier can be output with an arbitrary initial phase. That is, the phase shifter 18 'can be replaced with a general quadrature modulator.
[0031]
In the above-described embodiment, the comparison of the phase difference between the input signal and the feedback signal is performed for the Q component signal. However, it is obvious that it may be performed for the I component signal.
The phase controller 17 of FIG. 5 can be realized by combining a logic gate circuit, a counter and a memory, but can also be implemented in software using a DSP or a microcomputer (not shown).
FIGS. 8 and 9 are flowcharts in the case where the operations of the parts other than the comparators 20, 22, and 26 in FIG. 5 are performed by software. Hereinafter, this flowchart will be described.
[0032]
In step 101, the count value K of the counter 24, the initial value φ of the phase angle on the IQ coordinate, and the flag value M indicating whether or not the baseband Q component has changed from the low level to the high level, respectively. Set to zero. Next, in step 101, the I component baseband input signal, the comparator 22 output, the Q component baseband input signal, the comparator 26 output, the Q component baseband addition signal Q ′, and the comparator 21 output are captured.
[0033]
Next, in step 102, the value of the exclusive OR X of the outputs of the comparators 21 and 26 is calculated. In step 103, it is determined whether X is 1. If X is 1, the process proceeds to step 104. If X is not 1, the process returns to step 101. In step 104, the value K of the phase difference counter (corresponding to the counter 24) is incremented by one. In step 105, it is determined whether or not the count value K exceeds a set reference value L of the phase difference counter. When the count value K exceeds the reference value L, the process proceeds to step 106, and when it does not exceed, the process returns to step 101.
[0034]
In step 106, the DC voltage values of the I component and Q component corresponding to the phase shift set value φ determined in steps 110 to 126 described later are read from a memory (not shown) and output as analog signals (control unit). Equivalent to 33 operations). That is, for example, in a memory such as a ROM, values of an I component voltage and a Q component voltage corresponding to a phase value for each range of 1 to 360 ° of the φ value are stored. Then, the phase shifter 18 'is controlled by the voltage value determined in step 106, and the phase shift is reset in step 107.
[0035]
On the other hand, the detection flow of the advance and delay of the phase shift will be further described.
In step 110, it is determined whether or not the flag value M is at a high level (1). If the flag M is at a high level (indicating that the previous Q component is at a low level), it is next determined at step 111 whether the Q component baseband input signal Q is at a high level. If the Q value is at a high level, the flag M is reset to 0 in step 112. If the flag M is low level (indicating that the previous Q component is high level) in step 110, then in step 113, it is determined whether or not the Q value is low level. If the Q value is low level, the flag M is set to 1 in step 114. If the Q value is not low level, the process returns to step 101 and the above steps are repeated. The operation so far corresponds to the clock operation of the flip-flops 27 and 28.
[0036]
Next, in step 115, it is determined whether or not the value of the I component baseband input signal I is high. If the I value is high, it is determined in step 116 whether the Q component baseband addition signal Q ′ is high. If it is determined in step 115 that the I value is not high, it is determined in step 117 whether or not the Q component baseband addition signal Q ′ is high. Steps 110 to 117 correspond to the operations of the flip-flops 27 and 28, the inverter 29, and the switch 30.
[0037]
Next, in step 120, it is determined whether the count value N is greater than zero. If the count value N is larger than 0, it is a phase shift delay, and therefore, in step 121, a predetermined phase shift amount Δ (delta) is added to the current phase shift set value φ. If the count value N is not greater than 0, the phase is advanced, and therefore a predetermined phase shift amount Δ is subtracted from the current phase setting value φ in step 122.
[0038]
Next, in step 123, it is determined whether or not the updated phase shift set value φ is 360 ° or more. If φ is 360 ° or more, in step 124, φ−360 is calculated and the result is set as a new φ. If it is determined in step 123 that φ is not 360 ° or more, it is determined in step 125 whether φ is smaller than 0. If φ is smaller than 0, φ−360 is calculated in step 126, and the result is set as a new φ. The determined φ value is used in step 106.
[0039]
In the above-described embodiment, the phase difference is compared using the Q component Q of the input signal and the Q component Q ′ of the feedback signal, and the I component I and Q component Q of the input signal and the Q component Q ′ of the feedback signal are calculated. The rotation direction was obtained using the I component I ′ of the feedback signal instead of the Q component Q ′ of the feedback signal for phase difference comparison, and at that time, in order to obtain the rotation direction. It is obvious that the I component I and Q component Q of the input signal and the I component I ′ of the feedback signal may be used.
[0040]
【The invention's effect】
As described above, according to the present invention, phase control can be performed by observing the Q component and the I component of the baseband signal. Further, since phase control can be automatically performed during normal operation, no special test signal is required for phase adjustment. Furthermore, accurate phase control can be performed by eliminating the need for switching means between open loop and closed loop. Therefore, since the Cartesian loop is not an open loop and can follow the phase change even when the phase in the loop changes due to temperature fluctuations, changes over time, etc., the phase characteristics can be operated stably, and the output operation characteristics can be stabilized. It is possible to prevent deterioration of spurious characteristics.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of an embodiment of a negative feedback circuit of a transmitter of the present invention.
FIG. 2 is a block diagram showing a configuration of a conventional negative feedback circuit.
FIG. 3 is a time chart for explaining the operation of an embodiment of the phase control method of the present invention.
FIG. 4 is a diagram for explaining an embodiment of the exclusive OR operation of the phase controller of the present invention.
FIG. 5 is a block diagram showing an embodiment of the phase controller of the present invention.
FIG. 6 is an operation explanatory diagram of a phase controller according to an embodiment of the present invention.
FIG. 7 is an operation explanatory diagram of a phase controller according to an embodiment of the present invention.
FIG. 8 is a part of a flowchart in the case where the phase controller of the present invention is software-based.
FIG. 9 is a part of a flowchart for the case where the phase controller of the present invention is software-based.
10 is a block diagram showing a configuration of a specific example of the phase shifter of FIG. 1;
11 is an IQ coordinate diagram for explaining the operation of the phase shifter of FIG. 10;
[Explanation of symbols]
1: baseband signal generator, 2: adder, 3: loop filter, 4: quadrature modulator, 5, 7: bandpass filter, 6, 15: mixer, 8: power amplifier, 9: antenna, 10: direction Sex coupler, 11: reference signal generator, 12, 13: PLL frequency synthesizer, 14: attenuator, 16: quadrature demodulator, 17, 19: phase controller, 18, 18 ': phase shifter, 20, 30: Switch, 21, 22, 26: Comparator, 23: Exclusive OR circuit, 24: Counter, 25: Up / down counter, 27, 28: Flip-flop, 29: Inverter, 30: Switch, 31-1, 31-2 , 31-3: Input terminal, 32: Reference voltage input terminal, 33: Control unit, 34: Output terminal, 35: Clock input terminal.

Claims (2)

Inputs the input phase component and input the quadrature component of the baseband signal, at the transmitter to which the baseband signal to quadrature modulation by the local oscillator signal frequency, and transmits the amplifying the quadrature modulated signal to a predetermined power level,
Branching means for branching a part of the output signal of the transmitter;
A quadrature demodulating means for quadrature demodulating a feedback in-phase component and a feedback quadrature component according to the local oscillation signal frequency for a part of the output signal branched by the branching means;
By providing the feedback in-phase component and the input in-phase component and the adding means for adding the feedback quadrature component and the input quadrature component, respectively.
A non-linear distortion compensation circuit according to the negative feedback system to compensate for non-linear distortion of the transmitter,
Phase shifting means for shifting the phase of the local oscillation signal frequency input to the quadrature demodulation means ;
Comparing the input quadrature component or in-phase component with the quadrature component or in-phase component added by the adder, and phase control means for outputting phase control information for the phase shift means to shift the phase,
The phase control means includes
A first means for comparing the input in-phase component with a predetermined reference level, or comparing the input quadrature component with a predetermined reference level to generate a binary signal of 1, 0;
A second means for comparing one of the input signal of the input in-phase component and the addition signal of the input quadrature component with a predetermined reference level to generate a binary signal of 1, 0;
Third means for outputting an exclusive OR signal of the binary signal generated by the first means and the binary signal generated by the second means;
Counter means for counting feedback of the output signal of the third means at a predetermined clock;
A fourth means for generating the phase control information when a count value of the counter means exceeds a predetermined value;
The in- phase component by the first means and the second means, or means for determining the advance or delay of the phase by determining the positive or negative of the quadrature component or the in-phase component when the quadrature component is zero-crossing,
The phase shift means changes the phase of the carrier wave by a predetermined amount according to the phase control information from the phase shift control means , and the phase difference between the input in-phase component and the feedback in-phase component, and the input quadrature component And a phase difference between the feedback quadrature component and a transmitter. 2. The transmitter according to claim 1 , wherein the phase control means and the phase shift means are performed in a closed loop.

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