JP3800910B2 - SEMICONDUCTOR DEVICE, ITS MANUFACTURING METHOD, AND ELECTRONIC DEVICE - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device, manufacturing method thereof and electronic equipment, wherein semiconductor chips can be electrically connected to an external device or the like without using another auxiliary means such as an interposer and the stacked chips can electrically be connected regardless of their sizes. SOLUTION: Electrode pads 12a, 12b and 12c of stacked semiconductor chips 10a, 10b and 10c are formed on a side surface as exposed. A wiring pattern 18 is formed by electroless plating on a side surface of the chips 10a, 10b and 10c to be connected to a wiring substrate 30. Contacts 16 passing through the chips 10a, 10b and 10c and insulating resin 20a and 20b are provided so that a semiconductor chip 10d is connected to the substrate 30 through the contacts 16. With this arrangement, the chips 10a, 10b, 10c and 10d can be connected through the board 30.

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device, a method for manufacturing the same, and an electronic device, and more particularly to a device suitable for stacking and using a plurality of semiconductor chips.
[0002]
[Prior art]
In the field of semiconductor devices, in recent years, for the purpose of reducing the size and weight of semiconductor devices, many semiconductor chips are provided in a single package, in particular, each semiconductor chip is provided in a stacked state. Such a semiconductor device is called a multichip package (MCP) or a multichip module (MCM). A specific example of such an apparatus is the invention of Japanese Utility Model Laid-Open No. 62-158840. That is, a plurality of chips are stacked in a single ceramic package, and the electrodes of each chip are connected by wires. As another example, as in the invention of JP-A-11-135711, a semiconductor chip is mounted on a wiring board called an interposer, the interposers are connected to each other, and stacked to form a single semiconductor device. Is.
[0003]
[Problems to be solved by the invention]
However, when the semiconductor chips to be stacked are substantially the same size, in the invention of Japanese Utility Model Publication No. 62-158840, the semiconductor chip other than the semiconductor chip located at the uppermost part is a semiconductor chip whose electrode is located at the upper level. Since it is in a hidden state, bonding becomes difficult. In the invention of Japanese Patent Application Laid-Open No. 11-135711, it is easy to stack semiconductor chips of substantially the same size to form a single semiconductor device. However, each semiconductor chip is mounted on an interposer, and further, the interposer In order to secure the electrical connection between them, a more complicated manufacturing process is required than the invention of Japanese Utility Model Laid-Open No. 62-158840.
[0004]
Accordingly, the present invention has been made to solve the above-described drawbacks of the prior art, and it is possible to electrically connect a semiconductor chip to an external device or the like without using other auxiliary means such as an interposer. A semiconductor device that can electrically connect stacked semiconductor chips regardless of their size, a manufacturing method thereof, and an electronic apparatus.
[0005]
[Means for Solving the Problems]
In order to achieve the above object, the present invention provides a method of manufacturing a semiconductor device in which a plurality of semiconductor chips each having an electrode pad exposed on a side surface are stacked, and the semiconductor chips are stacked and integrated. 1 step, a second step of attaching catalyst nuclei to the wiring pattern formation region on the side surface of the semiconductor chip, and electroless plating on the wiring pattern formation region to form a wiring pattern in the wiring pattern formation region And at least a third step.
[0006]
In the present invention configured as described above, the stacked semiconductor chips are electrically connected by the wiring pattern formed by electroless plating, so that wiring is performed as in the case of using a wiring means such as a wire or an interposer. It is not necessary to secure a space for arranging the means, and the semiconductor device can be easily downsized.
[0007]
Further, in the method of manufacturing a semiconductor device, in which a plurality of semiconductor chips are stacked, and an electrode pad formed on the semiconductor chip and a terminal connected to the electrode pad are exposed to the side surface side, the semiconductor chip A first step of laminating and integrally forming, a second step of attaching catalyst nuclei to the wiring pattern formation region on the side surface of the semiconductor chip, and electroless plating on the wiring pattern formation region, And at least a third step of forming a wiring pattern in the pattern formation region.
[0008]
In the present invention configured as described above, since the stacked semiconductor chips are electrically connected by the wiring pattern formed by electroless plating, it is not necessary to secure a space for arranging the wiring means, and the semiconductor device Can be easily reduced in size.
[0009]
In the method of manufacturing a semiconductor device, a step of forming a photoresist film in a portion other than the wiring pattern formation region of the semiconductor chip between the first step and the second step; And a step of peeling the photoresist film between the step 2 and the third step.
[0010]
In the present invention configured as described above, since areas other than the wiring pattern formation area are masked, catalyst nuclei do not adhere to the areas. Further, since the photoresist film is peeled before the electroless plating, the metal in the plating solution does not deposit on the photoresist film.
[0011]
In the method of manufacturing a semiconductor device, in the second step, a solution containing at least one of colloidal gold particles, silver particles, platinum particles, or palladium particles is discharged from an inkjet head, and the wiring pattern The solution is adhered to the formation region.
[0012]
In the present invention configured as described above, catalyst nuclei can be quickly attached to the wiring pattern formation region.
[0013]
In the method for manufacturing a semiconductor device, in the second step, an adhesive is applied to the wiring pattern formation region, palladium powder is discharged from a spray nozzle, and the palladium powder is applied to the wiring pattern formation region. It was characterized by adhering.
[0014]
In the present invention configured as described above, catalyst nuclei can be quickly attached to the wiring pattern formation region. In addition, since the adhesive is provided in the wiring pattern forming region, the palladium powder can be reliably attached to the region and does not adhere to the region other than the region.
[0015]
In the method of manufacturing a semiconductor device, the step of forming a through hole penetrating the active element forming surface of the semiconductor chip and the back surface of the active element forming surface before the first step; And a step of attaching catalyst nuclei to the inner surface of the through hole.
[0016]
In the present invention configured as described above, it is possible to easily provide a contact penetrating the stacked semiconductor chips.
[0017]
Further, in the method for manufacturing a semiconductor device, in the step of attaching the catalyst nucleus to the inner surface of the through hole, a solution containing at least one of colloidal gold particles, silver particles, platinum particles, or palladium particles from the inkjet head And the solution is injected into the through hole.
[0018]
In the present invention configured as described above, the catalyst nucleus can be easily attached to the inside of the through hole.
[0019]
And in the semiconductor device, it was manufactured by the manufacturing method of the semiconductor device in any one.
[0020]
In the present invention configured as described above, the side surfaces of the stacked semiconductor chips can be used for electrical connection, and a contact penetrating the inside of the semiconductor chip is provided, so that semiconductor chips of substantially the same size are stacked. In addition, an auxiliary means for connecting semiconductor chips such as an interposer in a stacked state becomes unnecessary.
[0021]
Furthermore, an electronic apparatus includes the semiconductor device described above.
[0022]
In the present invention configured as described above, a semiconductor device that can be made smaller than the semiconductor device according to the prior art is used, and thus it is easy to reduce the size of the electronic device itself.
[0023]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, preferred embodiments of a semiconductor device, a manufacturing method thereof, an electronic device, a circuit board, and an electronic device according to the present invention will be described in detail with reference to the accompanying drawings.
[0024]
FIG. 1 is a cross-sectional view schematically showing a semiconductor device according to an embodiment of the present invention. FIG. 2 is a side view schematically showing the semiconductor device according to the embodiment of the present invention. FIG. 3 is an explanatory view (1) showing a wiring pattern forming step of the semiconductor device according to the embodiment of the present invention. FIG. 4 is an explanatory diagram (2) showing a wiring pattern forming step of the semiconductor device according to the embodiment of the present invention. Further, FIG. 5 is an explanatory view showing a contact forming process of the semiconductor device according to the embodiment of the present invention.
[0025]
As shown in FIG. 1, a semiconductor device 100 according to an embodiment of the present invention has a configuration as a multichip module in which semiconductor chips 10a, 10b, 10c, and 10d are stacked, and is connected to a wiring board 30. . The semiconductor chips 10a, 10b, and 10c have the same size, and are bonded via insulating resins 20a and 20b with their active element formation surfaces facing upward. The semiconductor chip 10d is smaller than the semiconductor chips 10a, 10b, and 10c, and is bonded to the semiconductor chip 10c by the anisotropic conductive adhesive 40 with the active element formation surface facing downward.
[0026]
Further, the semiconductor chips 10a, 10b, and 10c are provided so that the respective electrode pads 12a, 12b, and 12c are exposed to the side surface side. Further, bumps 14a, 14b, and 14c are provided on the electrode pads 12a, 12b, and 12c, respectively, and these are also provided so as to be exposed on the side surface side. In addition, a wiring pattern 18 in close contact with the side surfaces is formed on the side surfaces of the semiconductor chips 10a, 10b, and 10c. As shown in FIG. 2, the wiring pattern 18 is formed so as to cover the electrode pads 12a, 12b, 12c and the bumps 14a, 14b, 14c, and is connected thereto. In addition, the lower end portion of the wiring pattern 18 is electrically connected to the wiring pattern 32 provided on the wiring substrate 30 via the bumps 34.
[0027]
Therefore, the semiconductor chips 10a, 10b, and 10c are electrically connected to the wiring board 30. Further, since the insulating resins 20a and 20b are interposed between the bumps 14a and 14b and the semiconductor chips 10b and 10c located above the bumps 14a and 14b, the insulating state is maintained. The semiconductor chip 10a located at the bottom and the wiring board 30 are bonded by an anisotropic conductive adhesive 40. The material of the wiring pattern 18 is nickel (Ni) and is formed by a method described later.
[0028]
Furthermore, the semiconductor chips 10a, 10b, 10c and the insulating resins 20a, 20b are provided with contacts 16 penetrating them. The upper end portion of the contact 16 is connected to the electrode pad 12d of the semiconductor chip 10d through the bump 22. The lower end portion of the contact 16 is connected to a wiring pattern 32 provided on the wiring substrate 30 via bumps 34. Therefore, the semiconductor chip 10d is electrically connected to the wiring board 30. The material of the contact 16 is nickel as in the wiring pattern.
[0029]
According to the above configuration, the semiconductor chips 10a, 10b, and 10c are provided so that the electrode pads 12a, 12b, and 12c are exposed to the side surface, so that these semiconductor chips 10a, 10b, and 10c can be stacked even if they are stacked. Electrical connection is possible from the side. In addition, since the wiring pattern 18 is formed on the side surfaces of the semiconductor chips 10a, 10b, and 10c and connected to the electrode pads 12a, 12b, and 12c and the wiring pattern 32 of the wiring board 30, the stacked semiconductor chips 10a, 10b, 10c can be easily electrically connected to the wiring board 30. Further, since the semiconductor chip 10d having a size different from that of the semiconductor chips 10a, 10b, and 10c is bonded onto the semiconductor chip 10c and electrically connected to the wiring substrate 30 through the contact 16, the stacked semiconductor chips having different sizes are used. The chip can be easily connected electrically.
[0030]
Further, bumps 14a, 14b, 14c are provided on the electrode pads 12a, 12b, 12c, and the bumps 14a, 14b, 14c are also connected to the wiring pattern 18, so that the electrode pads 12a, 12b, 12c and the wiring pattern are connected. The reliability of the electrical connection with 18 can be increased. In addition, since the semiconductor chip 10 a and the wiring substrate 30 are bonded by the anisotropic conductive adhesive 40, the electrical connection between the bumps 34 and the wiring pattern 32 can be reliably ensured.
[0031]
In addition, since the insulating resins 20a and 20b are provided between the semiconductor chips 10a, 10b, and 10c, for example, a short circuit occurs between the bumps 14a and 14b and the semiconductor chips 10b and 10c located above the bumps 14a and 14b. Can be prevented. Further, since the semiconductor chip 10d is bonded to the semiconductor chip 10c by the anisotropic conductive film 40, a short circuit occurs between the electrode pad 12c and / or the bump 14c and the electrode pad 12d and / or the bump 22. There is nothing.
[0032]
The number of semiconductor chips stacked in the semiconductor device 100 is not limited to four, and may be any number as long as the above configuration can be adopted. The insulating resin is preferably an epoxy resin, but other resins may be used as long as they have good adhesion to the semiconductor chip. Further, the bumps 14a, 14b, and 14c may be omitted as long as the electrical connection between the electrode pads 12a, 12b, and 12c and the wiring pattern 18 can be reliably ensured. Furthermore, it is preferable to use tin or a tin alloy for each of the bumps 14a, 14b, 14c, 22, and 34, but other metals such as gold, copper, or a composite material thereof may be used. In addition, a conductive organic material such as conductive rubber may be used. Further, the material of the substrate portion of the wiring substrate 30 may be either an organic material or an inorganic material. Examples of the organic material include polyimide, polyester, and polysulfone resin, and examples of the inorganic material include silicon, glass, and metal. In the wiring board according to the present invention, any organic or inorganic material may be used, or a combination of both may be used.
[0033]
Furthermore, the wiring pattern 18 and the contact 16 are not limited to a single layer of nickel. For example, nickel and gold (Ni—Au), nickel and copper (Ni—Cu), or nickel and gold and copper (Ni—Au—). It may be formed by laminating a plurality of metal layers such as Cu) and may be another metal having good conductivity such as gold (Au), silver (Ag), copper (Cu), tin (Sn). . Moreover, when not using the formation method mentioned later, it is good also as what uses a conductive resin. Furthermore, the wiring pattern 18 and the contact 16 may be made of different materials. In addition, an adhesive having no conductivity may be used instead of the anisotropic conductive adhesive 40. In this case, although it is slightly inferior to the anisotropic conductive adhesive in ensuring the conductivity, it is advantageous in terms of cost because the price is low.
[0034]
Next, a method for forming the wiring pattern 18 of the semiconductor device 100 will be described. 3A and 3B show side surfaces of the stacked semiconductor chips 10a, 10b, and 10c, and FIG. 3C shows a cross section of the stacked semiconductor chips 10a, 10b, and 10c. Is shown. 4A and 4B show the same parts of the semiconductor chips 10a, 10b, and 10c as those shown in FIGS. 3A and 3B.
[0035]
First, as shown in FIG. 3A, the semiconductor chips 10a, 10b, and 10c are laminated and integrated through the insulating resins 20a and 20b.
[0036]
Next, as shown in FIG. 3B, a photoresist film 50 is provided in a portion other than a region where a wiring pattern is to be formed. When the pitch of the electrode pads 12a, 12b, and 12c of the semiconductor chips 10a, 10b, and 10c is relatively gradual, and the width of the wiring pattern may be slightly wider than the width of the electrode pads 12a, 12b, and 12c. This step may be omitted.
[0037]
Next, as shown in FIG. 3C, the catalyst solution 24 containing the catalyst nuclei 26 is ejected by the ink jet head 52 and adhered to the formation area of the wiring pattern. The catalyst core 26 is palladium colloid particles. Note that other metal colloidal particles having catalytic action such as gold, silver, or platinum may be used as long as electroless plating described later is possible. Further, instead of the process shown in FIG. 3C, first, an adhesive is applied to the wiring pattern forming region, and then palladium powder is sprayed onto the adhesive-coated region by a jet nozzle, The attached palladium powder may be used as the catalyst core.
[0038]
Next, as shown in FIG. 4A, the catalyst solution 24 attached to the wiring pattern formation region is dried, and the palladium colloid particles 26 are attached to the wiring pattern formation region. The catalyst solution 24 may be naturally dried or heated and dried.
[0039]
Next, as shown in FIG. 4B, the photoresist film 50 is removed, and then electroless plating of nickel is performed to deposit nickel in the wiring pattern formation region. Note that when the process shown in FIG. 3B is omitted, it is not necessary to remove the photoresist film 50. Further, as described above, a metal other than nickel may be plated.
[0040]
Through the above steps, the wiring pattern 18 as shown in FIG. 2 can be formed.
[0041]
Further, a method for forming the contact 16 of the semiconductor device 100 will be described.
[0042]
First, as shown in FIG. 5A, a laser beam 54 is irradiated to a portion where contacts of the stacked semiconductor chips 10a, 10b, and 10c and the insulating resins 20a and 20b are provided, thereby forming a through hole 28. Note that the through hole 28 may be formed in advance before stacking the semiconductor chips, or may be formed by using a wet-type etching together as in the related art.
[0043]
Next, as shown in FIG. 5B, the catalyst solution 24 is injected into the through hole 28 by the ink jet head 52 to fill the catalyst core 26 inside the through hole 28.
[0044]
Next, as shown in FIG. 5C, the catalyst solution 24 in the through hole 28 is dried to leave the palladium colloid particles 26 on the inner surface of the through hole 28. Subsequently, electroless plating of nickel is performed to deposit nickel on the inner surface of the through hole 28 and fill the through hole 28 with nickel.
[0045]
Through the above steps, the nickel contact 16 as shown in FIG. 1 can be formed. The through hole 28 may not be completely filled with nickel as long as electrical conduction between the upper and lower ends of the contact 16 can be ensured. Moreover, you may deposit metals other than nickel as mentioned above.
[0046]
According to the method for forming the wiring pattern 18 and the contact 16 described above, it is possible to easily form the wiring pattern 18 and the contact 16 in a minute region and a through hole.
[0047]
With the above configuration, the semiconductor chips 10a, 10b, 10c, and 10d can be easily connected to an external device or the like via the wiring substrate 30. Further, in the semiconductor device 100, it is not necessary to secure a space (volume) or an area for providing auxiliary means such as an interposer, so that the mounting area of the semiconductor device can be reduced. Further, if the semiconductor device 100 is used in an electronic device such as a mobile phone or a notebook personal computer, it is possible to easily downsize these electronic devices.
[0048]
【The invention's effect】
As described above, according to the present invention, in a method of manufacturing a semiconductor device in which a plurality of semiconductor chips each having an electrode pad exposed on the side surface are stacked, the semiconductor chips are stacked and integrated. 1 step, a second step of attaching catalyst nuclei to the wiring pattern formation region on the side surface of the semiconductor chip, and electroless plating on the wiring pattern formation region to form a wiring pattern in the wiring pattern formation region Therefore, the stacked semiconductor chips can be electrically connected to an external device or the like without using an interposer, which contributes to downsizing of the semiconductor device. It also contributes to the cost reduction of semiconductor device manufacturing.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view schematically showing a semiconductor device according to an embodiment of the present invention.
FIG. 2 is a side view schematically showing a semiconductor device according to an embodiment of the present invention.
FIG. 3 is an explanatory view (1) showing a step of forming a wiring pattern of the semiconductor device according to the embodiment of the present invention.
FIG. 4 is an explanatory view (2) showing a step of forming a wiring pattern of the semiconductor device according to the embodiment of the present invention.
FIG. 5 is an explanatory diagram showing a contact forming process of the semiconductor device according to the embodiment of the invention.
[Explanation of symbols]
10a ... Semiconductor chip 10b ... Semiconductor chip 10c ... Semiconductor chip 10d ... Semiconductor chip 12a ... Electrode pad 12b ... Electrode pad 12c ... Electrode pad 12d ... Electrode pad 14a ... ... Bump 14b ...... Bump 14c ......... Bump 16 ......... Contact 18 ......... Wiring pattern 20a ...... Insulating resin 20b ......... Insulating resin 22 ......... Bump 24 ...... Catalyst solution 26 ... ... catalyst core 28 ......... through hole 30 ......... wiring substrate 32 ......... wiring pattern 34 ......... bump 50 ......... photoresist film 52 ......... inkjet head 54 ......... laser beam 90a ......... opening Width 90b ......... Opening width 90c ......... Opening width 100 ......... Semiconductor device

Claims (9)

In a method of manufacturing a semiconductor device in which a plurality of semiconductor chips each having an electrode pad exposed on the side surface are stacked,
A first step of stacking and integrating the semiconductor chips;
A second step of attaching catalyst nuclei to the wiring pattern forming region on the side surface of the semiconductor chip;
A third step of electroless plating the wiring pattern formation region to form a wiring pattern in the wiring pattern formation region;
A method for manufacturing a semiconductor device, comprising: In a method for manufacturing a semiconductor device, in which a plurality of semiconductor chips are stacked and an electrode pad formed on the semiconductor chip and a terminal connected to the electrode pad are exposed on the side surface side,
A first step of stacking and integrating the semiconductor chips;
A second step of attaching catalyst nuclei to the wiring pattern forming region on the side surface of the semiconductor chip;
A third step of electroless plating the wiring pattern formation region to form a wiring pattern in the wiring pattern formation region;
A method for manufacturing a semiconductor device, comprising: Forming a photoresist film in a portion other than the wiring pattern formation region of the semiconductor chip between the first step and the second step;
Peeling the photoresist film between the second step and the third step;
The method of manufacturing a semiconductor device according to claim 1, wherein: In the second step,
2. A solution containing at least one of colloidal gold particles, silver particles, platinum particles, and palladium particles is ejected from an inkjet head, and the solution is adhered to the wiring pattern formation region. Item 4. A method for manufacturing a semiconductor device according to Item 3. In the second step,
4. The adhesive according to claim 1, wherein an adhesive is applied to the wiring pattern formation region, palladium powder is discharged from a spray nozzle, and the palladium powder is adhered to the wiring pattern formation region. The manufacturing method of the semiconductor device as described in 2. Before the first step,
Forming a through hole penetrating an active element forming surface of the semiconductor chip and a back surface of the active element forming surface;
Attaching catalyst nuclei to the inner surface of the through hole;
6. The method of manufacturing a semiconductor device according to claim 1, wherein: In the step of attaching catalyst nuclei to the inner surface of the through hole,
7. The solution according to claim 6, wherein a solution containing at least one of colloidal gold particles, silver particles, platinum particles, and palladium particles is discharged from an inkjet head, and the solution is injected into the through hole. A method for manufacturing a semiconductor device.   A semiconductor device manufactured by the method for manufacturing a semiconductor device according to claim 1.   An electronic apparatus comprising the semiconductor device according to claim 8.

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