JP3950419B2 - Frame signal processing method - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a frame signal processing method used when high-speed data is transmitted using a predetermined frame.
[0002]
[Prior art]
Non-Patent Document 1 and Non-Patent Document 2 disclose conventional techniques related to high-speed Ethernet (registered trademark: hereinafter referred to as a standard network).
As shown in Non-Patent Document 1, in a standard network that transmits high-speed data of 10 gigabits / second, four communication channels are used simultaneously, and data signals are respectively sent to four lanes corresponding to each channel. Allocating and processing four signals in parallel. Therefore, the bit rate of data per lane is reduced to ¼.
[0003]
In a circuit that processes a high-speed signal, an increase in power consumption of the circuit is inevitable. Therefore, in order to reduce the power consumption of the circuit in a relay device or the like, it is desirable to reduce the bit rate of data handled in the circuit.
By increasing the number of lanes used, the data rate per lane can be further reduced. For example, if the data sequence is converted and a 4-lane signal is converted to 8-lane, the data bit rate per lane is further reduced to 1/2.
[0004]
In order to reduce the data rate per lane, in the example of FIG. 11, the parallel signal assigned to the M lanes is input and the parallel signal assigned to the K lanes is output (M <K). Assumed. By such conversion, the bit rate of the signal per lane can be lowered.
When data is processed, since it is normally processed for each byte, the data is shown divided into bytes in the figure. Each column in the vertical direction across the lanes is called a column.
[0005]
The actually transmitted signal constitutes a predetermined data frame, and an inter frame gap (IFG) is arranged between two adjacent data frames. The inter frame gap is configured by a predetermined idle byte (I).
In addition, a predetermined signal (S) is arranged at the head position of the data frame, and a predetermined signal (T) is arranged at the end of the data frame. Each data representing the main body of the data frame is represented by (d).
[0006]
The minimum number of bytes is defined for the length of the interframe gap, that is, the number of consecutive idle bytes (I).
For example, the XGMII signal of the 10 gigabit standard network is a 4 parallel signal (M = 4) using 4 lanes, and the bit rate is 312.5 Mb / s. When this 4 parallel signal is converted into an 8 parallel signal (K = 8) using 8 lanes, the bit rate after conversion is as follows.
[0007]
312.5 (Mb / s) × 4/8 = 156.25 (Mb / s)
That is, the bit rate can be reduced to ½ by this conversion. If the bit rate of the original signal is Br, the converted bit rate Bout is generally expressed by the following equation.
Bout = Br × M / K
Thus, if the parallel number of signals to be handled is converted so as to increase from M to K, the bit rate of the signal decreases, so that the power consumption of the circuit that processes the signal can be suppressed. In addition, since the circuit can be configured by using an inexpensive device due to the low speed, the cost of the transmission apparatus can be reduced.
[0008]
In the example of FIG. 11, data are arranged in the order of lane (0), lane (1), lane (2),..., Lane (K-1). Lane (0) is the first lane, that is, the reference lane.
[Non-Patent Document 1]
“10 Gigabit Ethernet Textbook”, P169, Osamu Ishida, supervised by Koichiro Seto (IDG Japan), published on April 20, 2002.
[Non-Patent Document 2]
"Http://www.ieee802.3.org/3/ae/public/ju100/frazier_1_0700.pdf"
[0009]
[Problems to be solved by the invention]
As a specific example, a case is assumed in which an XGMII signal defined by a standard network of 10 gigabits / second is handled. In this signal, the length of the interframe gap, that is, the number of consecutive idle bytes (I) is defined so that the minimum value is 12. However, this minimum value is allowed to fluctuate within a range of 12 ± 3 instantaneously depending on the situation. Even after conversion, the length of the interframe gap needs to be adjusted to a prescribed value.
[0010]
However, when the conversion of the number of parallel signals is performed, the start position of the frame, that is, the position of the lane to which the signal (S) is assigned changes. However, for example, in the 64B / 66B code, there is a restriction that “the head of the frame must be in lane (0)”.
Therefore, for example, as shown in FIG. 11, it is necessary to increase or decrease the number of idle bytes (I) constituting each interframe gap and move the position of the signal (S) to the lane (0).
[0011]
However, the length of the interframe gap must be controlled to be 12 (bytes) on average.
However, in the case of the interframe gap IFG (2) shown in FIG. 11, for example, the interframe gap length after adjusting the number of idle bytes is 7 (bytes), so that all 8 lanes are configured with idle bytes. There is no idle column in this interframe gap.
[0012]
By the way, generally in signal transmission, there are cases where the clock used for synchronization needs to be corrected to adjust the signal timing. Also, when transmitting parallel signals, timing shifts between parallel signals that should be synchronized with each other due to differences in the lengths of multiple cables and multiple wires used for actual transmission. May occur.
[0013]
In order to correct the timing of the clock and adjust the skew, it is necessary to shift the signal of each lane with respect to the time axis. When there is an idle column composed of only idle bytes as in the interframe gap IFG (1) shown in FIG. 11, one idle column time that does not affect the content of the frame signal is used. The skew can be adjusted by extracting or inserting an idle column to correct the clock timing, or by extracting or inserting idle bytes in some lanes of the idle column.
[0014]
However, when an interframe gap without an idle column is formed, such as the interframe gap IFG (2) shown in FIG. 11, the idle column for clock adjustment and skew adjustment cannot be performed in that interval. End up.
An object of the present invention is to provide a frame signal processing method capable of forming an idle column in an interframe gap where no idle column exists when the parallel number of parallel signals is converted.
[0015]
[Means for Solving the Problems]
In the first aspect, an inter-frame gap is arranged between adjacent frames, and a frame signal in which the inter-frame gap is composed of a plurality of idle bytes is allocated to M lanes representing a plurality of M transmission channels. In a frame signal processing method for processing when the frame signal is input as a parallel byte sequence, the frame signal is rearranged into a K-lane parallel byte sequence assigned to K transmission channels larger than M and output. To generate an internal clock signal with a frequency greater than the clock of the frame signal to be inserted, insert a new number of idle bytes or more into the interframe gap of the frame signal, and temporarily store the frame signal Monitor the signal accumulation amount of the buffer placed in the Te, which comprises carrying out the insertion or extraction of the idle bytes for the inter-frame gap.
[0016]
In order to form an idle column in an interframe gap where no idle column exists, a new idle byte may be inserted into the interframe gap. However, if idle bytes are inserted, the information amount of the entire signal increases, and the bit rate of the signal changes.
According to the first aspect of the present invention, an internal clock signal having a frequency higher than that of the clock of the input frame signal is generated. Therefore, an increase in the bit rate caused by insertion of an idle byte can be dealt with by using the internal clock signal. .
[0017]
In practice, a buffer such as a FIFO (first-in first-out) is used to insert idle bytes into interframe gaps of continuously appearing signals.
In addition, when the clock frequency is fixed, the amount of information stored in the buffer varies as the frame length of the signal varies, and the stored information amount becomes excessive or insufficient. When the amount of stored information is excessive, the buffer may overflow, and when the amount of stored information is insufficient and the information amount becomes zero, discontinuity occurs in the output signal.
[0018]
By monitoring the signal accumulation amount in the buffer and inserting or extracting idle bytes from the interframe gap according to the increase or decrease in the detected signal accumulation amount, the influence of fluctuations in the signal frame length can be absorbed. .
Furthermore , the frame signal processing method according to claim 1 is an idle byte inserted so that a start byte representing the head of each frame moves to a predetermined reference lane on a frame signal rearranged in a parallel byte string of K lanes. It is characterized by adjusting the number of.
[0019]
When an input signal is converted from a parallel byte string of M lanes to a parallel byte string of K lanes, the position of the start byte (S) often moves from the reference lane (lane (0)) to another lane. However, the start byte can be moved to the reference lane by adjusting the number of idle bytes newly inserted in the interframe gap.
[0020]
2. The frame signal processing method according to claim 1, wherein after the input frame signal is rearranged into parallel byte strings of K lanes, idle bytes are inserted into the interframe gap, and the signal of the buffer Comparing the accumulated amount with the predetermined upper and lower limit values, and according to the comparison result, if the accumulation is insufficient, idle bytes are inserted until the accumulation is not insufficient, and if the accumulation is excessive, the accumulation is excessive. It is characterized in that idle bytes are extracted until there are no more.
[0021]
According to the second aspect of the present invention, even when the clock frequency is fixed in advance, it is possible to absorb the influence of fluctuations in the frame length of the signal and maintain the signal accumulation amount of the buffer at an appropriate value .
[0022]
According to a third aspect of the present invention, there is provided the frame signal processing method according to the first aspect, wherein idle bytes are inserted into the inter-frame gap for the frame signal of the parallel byte train of M lanes, and the M lanes are The byte sequence is rearranged into parallel byte sequences of K lanes.
[0023]
Claim 4 is the frame signal processing method according to claim 1, in order to place the start byte as a reference lane,
INSB = (Pa + Pb) K-1-IN
Pb = IG-Pa + 1
Pa = 1: When the start byte and the end byte are in the same column Pa = 2: When the start byte is in the column next to the end byte Pa = 3: When the start byte is in the next column after the end byte IN : Minimum value of the number of idle bytes in the input interframe gap IG: When the minimum number of idle columns is set as the design value, the number of idle bytes of (INSB + 1−K) or more and INSB or less is inserted into the interframe gap, and the internal clock The frequency Brout of the signal is determined by the following equation: Brout = α · Brin
Brin: input clock frequency α = (INSB + IN + minimum frame length) / (IN + minimum frame length)
It is characterized by that.
[0024]
In claim 4, can be fixed to a value determined frequency Brout of the internal clock signal in calculations, it is possible to place the start byte in the reference lane.
[0025]
5. The frame signal processing method according to claim 4 , wherein the input frame signal is a parallel lane of 4 lanes and has an XGMII transmission frame configuration of a 10 gigabit standard network, and is based on the start byte. To place in the lane,
INSB = (Pa + Pb) K-1-IN
Pb = IG-Pa + 1
Pa = 1: When the start byte and the end byte are in the same column Pa = 2: When the start byte is in the column next to the end byte Pa = 3: When the start byte is in the next column after the end byte IN : Minimum value of the number of idle bytes in the input interframe gap IG: When the minimum number of idle columns is set as the design value, the number of idle bytes of (INSB + 1−K) or more and INSB or less is inserted into the interframe gap, and the internal clock The frequency Brout of the signal is determined by the following equation: Brout = α · Brin
Brin: input clock frequency α = (INSB + IN + minimum frame length) / (IN + minimum frame length)
It is characterized by that.
[0026]
According to the fifth aspect of the present invention, when the XGMII signal is handled, the frequency Brout of the internal clock signal can be fixed to the value obtained by the calculation formula, and the start byte can be arranged in the reference lane.
According to a sixth aspect of the present invention, in the frame signal processing method according to the fourth aspect , when the input frame signal is a parallel lane of 4 lanes and has an XGMII transmission frame configuration of a 10 gigabit standard network, the output signal is 8 In order to convert the lane into a parallel byte string and place the start byte in the reference lane, INSB = 14, and the frequency Brout of the internal clock signal is determined by the following equation: Brout = (95/81) Brin
Brin: Input clock frequency.
[0027]
In claim 6 , when the XGMII signal is handled and the signal is output as a parallel byte string of 8 lanes, the frequency Brout of the internal clock signal can be fixed to the value obtained by the calculation formula, and the start byte is used as a reference. Can be placed in the lane.
According to a seventh aspect of the present invention, in the frame signal processing method of the fourth aspect , when the input frame signal is a parallel lane of 4 lanes and has an XGMII transmission frame configuration of a 10 gigabit standard network, the output signal is 10 In order to convert the lane into a parallel byte string and to place the start byte in the reference lane, INSB = 20 and the frequency Brout of the internal clock signal is determined by the following equation: Brout = (101/81) Brin
Brin: Input clock frequency .
[0028]
In claim 7 , when the XGMII signal is handled and the signal is output as a parallel lane of 10 lanes, the frequency Brout of the internal clock signal can be fixed to the value obtained by the calculation formula, and the start byte is used as a reference. Can be placed in the lane.
[0029]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described with reference to FIGS. This form corresponds to all the claims.
[0030]
FIG. 1 is a block diagram showing the configuration (1) of the main part of the relay apparatus. FIG. 2 is a flowchart showing an operation example (1) of the idle byte control circuit. FIG. 3 is a block diagram showing the configuration (2) of the main part of the relay apparatus. FIG. 4 is a block diagram showing the configuration (3) of the main part of the relay apparatus.
[0031]
FIG. 5 is a flowchart showing an operation example (2) of the idle byte control circuit. FIG. 6 is a flowchart showing the procedure for determining INSB. FIG. 7 is a time chart showing a specific example (1) of signal processing. FIG. 8 is a time chart showing a specific example (2) of signal processing.
FIG. 9 is a schematic diagram showing the relationship between the frame gap pattern of the input signal and Pa. FIG. 10 is a schematic diagram showing a specific example of the required number of idle bytes to be inserted. FIG. 11 is a time chart showing an example of frame signal conversion.
[0032]
The relay device shown in FIG. 1 includes an idle byte detection circuit 10, an idle byte control circuit 20, a processing unit 30, a timing adjustment skew correction device 40, a clock generation circuit 50, and a parallel number conversion circuit 60. The processing unit 30 includes a FIFO buffer 31, a selector circuit 32, and an idle byte generation circuit 33.
[0033]
A frame signal FLM1 as shown on the upper side of FIG. 11 and a clock signal CLK1 indicating the timing of the data are input to the input of the relay apparatus shown in FIG. This frame signal FLM1 is composed of a data frame and an interframe gap IFG arranged between adjacent data frames. The interframe gap IFG is composed of only predetermined idle bytes (I).
[0034]
The frame signal FLM1 is an M parallel signal, and is assigned to each lane (0 to M-1) corresponding to M channels.
When data is processed, since it is normally processed for each byte, in the figure, the data of the frame signal FLM1 is delimited for each byte. Each column in the vertical direction across the lanes is called a column.
[0035]
Further, a predetermined start byte (S) is arranged at the head position of the data frame, and a predetermined end byte (T) is arranged at the end of the data frame. Each data representing the main body of the data frame is represented by (d). It is assumed that the start byte (S) and the end byte (T) do not exist in the same column.
[0036]
The length of the inter-frame gap, that is, the number of consecutive idle bytes (I) is defined such that the minimum value is 12 assuming that the XGMII signal is handled. However, this minimum value is allowed to fluctuate within a range of 12 ± 3 instantaneously depending on the situation.
In the 10 gigabit standard network, 4 parallel signals assigned to 4 lanes are handled. In this form, in order to further reduce the speed of signals to be handled, transmission is performed using channels of 8 lanes or 10 lanes. Is assumed.
[0037]
For this purpose, the relay apparatus shown in FIG. The parallel number conversion circuit 60 receives an M parallel signal (FLM1) using M lanes, and rearranges it into a K parallel signal using K lanes (K = 8, 10, etc.).
When such rearrangement of the frame signal FLM1 is performed, the start byte (S) representing the head of the data frame often moves to other than the reference lane (0). In some cases, an interframe gap having no idle column may be formed, such as the interframe gap IFG (2) shown on the lower side of FIG. An idle column is a column composed of only idle bytes.
[0038]
In an interframe gap in which no idle column exists, the timing and skew cannot be adjusted in units of columns in the timing adjustment skew correcting device 40 of FIG.
Therefore, in the processing unit 30 shown in FIG. 1, a new idle byte is inserted into the interframe gap of the input frame signal. Also, since the amount of information increases more than the input by inserting idle bytes, it is necessary to change the bit rate.
[0039]
For this purpose, a clock generation circuit 50 is provided. The clock generation circuit 50 generates an internal clock CLKEXT having a higher frequency based on the input clock signal CLK1. This internal clock CLKEXT is applied to inputs of the processing unit 30 and the timing adjustment skew correcting device 40.
The idle byte detection circuit 10 monitors the frame signal to detect whether or not an idle byte (I) has appeared in order to detect the inter-frame gap timing of the frame signal. When an idle byte is detected, a detection signal IDDET is output.
[0040]
In order to realize insertion and extraction of idle bytes with respect to the inter frame gap, the processing unit 30 is provided with a FIFO buffer 31. The FIFO buffer 31 inserts and removes idle bytes according to the signal IDCNT output from the idle byte control circuit 20.
The FIFO buffer 31 can temporarily store a predetermined amount of information. The input and accumulated signals are output in the same order as the input order. Further, the FIFO buffer 31 compares the amount of information stored therein with a predetermined upper limit value and lower limit value, and outputs the result as a signal IDSTOCK.
[0041]
The idle byte control circuit 20 generates the control signal IDCNT according to the signal IDDET output from the idle byte detection circuit 10 and the signal IDSTOCK output from the FIFO buffer 31.
The control signal IDCNT output from the idle byte control circuit 20 is input to the FIFO buffer 31 and the selector circuit 32.
[0042]
The idle byte generation circuit 33 outputs an idle byte signal. The selector circuit 32 selectively outputs either the output of the FIFO buffer 31 or the output of the idle byte generation circuit 33 as the signal FLM4 in accordance with the control signal IDCNT output from the idle byte control circuit 20.
[0043]
For example, if the selector circuit 32 selects and outputs only one byte of the output of the idle byte generation circuit 33 instead of the output of the FIFO buffer 31, one byte of idle bytes can be inserted into the interframe gap of the frame signal. . In that case, it is necessary to shift the data accumulated in the FIFO buffer 31 backward by one byte.
[0044]
Further, if the data accumulated in the FIFO buffer 31 is shifted forward by 1 byte, 1 byte of idle bytes can be extracted from the frame signal.
An operation example (1) of the idle byte control circuit 20 will be described with reference to FIG.
[0045]
In step S11, the signal IDDET output from the idle byte detection circuit 10 is referenced to identify whether an idle byte is detected, that is, whether an interframe gap has appeared.
When an idle byte is detected, a control signal IDCNT is output in the next step S12, and the FIFO buffer 31 and the selector circuit 32 are controlled so that N idle bytes are newly inserted. The number N of idle bytes to be inserted is determined so that the output frame signal FLM4 during a predetermined time t includes an idle column having a predetermined value or more.
[0046]
In step S13, the signal IDSTOCK output from the FIFO buffer 31 is monitored to check whether the signal accumulation amount in the FIFO buffer 31 is excessive or insufficient. If the signal accumulation amount is insufficient, that is, if the signal accumulation amount becomes equal to or less than the lower limit value due to the variation in the frame length, the process proceeds to step S14. If the signal accumulation amount is excessive, that is, if the signal accumulation amount is greater than or equal to the upper limit value, the process proceeds to step S16.
[0047]
In step S14, the control signal IDCNT is output and a new idle byte is inserted in units of columns.
In step S16, the control signal IDCNT is output, and idle bytes are extracted from the frame signal held in the FIFO buffer 31 in units of columns.
Accordingly, when the signal accumulation amount in the FIFO buffer 31 is excessive, idle bytes are extracted until it becomes appropriate, and when the signal accumulation amount is insufficient, idle bytes are inserted until it becomes appropriate. To be implemented.
[0048]
In the relay apparatus shown in FIG. 1, idle bytes are inserted after the parallel number conversion circuit 60 converts the parallel number of the frame signal from M to K. However, as shown in FIG. The parallel number conversion circuit 60 can be arranged behind 30 and the parallel number can be converted from M to K after insertion of idle bytes.
[0049]
Further, the configuration can be changed as shown in FIG. That is, if the end byte detection circuit 11 and the start byte detection circuit 12 are provided instead of the idle byte detection circuit 10 of FIG. 1, the start and end timings of the interframe gap can be detected.
The operation of the idle byte control circuit 20 may be changed as shown in FIG. In the example of FIG. 5, it is assumed that the signal TDET output from the terminal byte detection circuit 11 shown in FIG. 4 and the signal SDET output from the start byte detection circuit 12 are monitored.
[0050]
The termination byte detection circuit 11 outputs a signal TDET when the termination byte (T) is detected. The start byte detection circuit 12 outputs a signal SDET when detecting the start byte (S).
Next, a method for determining the number N of idle bytes to be inserted and the frequency of the internal clock CLKEXT will be specifically described.
[0051]
For the signal before converting only the parallel number of the frame signal and inserting a new idle byte into the interframe gap, there are three types of patterns as shown in FIG. Therefore, the types of these patterns are defined by the parameter Pa as follows.
Pa = 1: When the start byte and the end byte are in the same column Pa = 2: When the start byte is in the column next to the end byte Pa = 3: When the start byte is in the next column after the end byte The parameter Pb is defined as follows using the minimum idle column number design value IG in the idle gap in the output frame signal.
[0052]
Pb = IG−Pa + 1 (1)
The number of idle bytes INSB to be inserted because there are at least IG idle columns in the idle gap in the output frame signal is expressed by the following equation.
INSB = (Pa + Pb) K-1-IN (2)
IN: Minimum value of the number of idle bytes existing in the idle gap of the input signal, that is, INSB is obtained by the procedure shown in FIG.
[0053]
Further, the frequency Brout required for the internal clock CLKEXT is expressed by the following equation.
Brout = α · Brin (3)
α = (INSB + IN + minimum frame length) / (IN + minimum frame length)
Brin: Clock frequency of the input signal Therefore, if the frequency of the input clock signal CLK1 is constant, the frequency of the internal clock CLKEXT generated by the clock generation circuit 50 can also be determined and fixed in advance.
[0054]
In step S23 shown in FIG. 5, the value of INSB is calculated based on the equation (2). In step S24, the number N of idle bytes to be inserted is determined in the range of (INSB + 1−K) or more and INSB or less. As a result, the start byte can be moved to the first lane (lane (0)).
Regarding INSB and frequency Brout, values obtained in advance can be used as long as the conditions are constant.
[0055]
As a specific example, when the input frame signal FLM1 is a 4-lane byte parallel signal and has a transmission frame configuration of the XGMII standard used in the 10 Gigabit standard network, the parallel number K on the output side of the parallel number conversion circuit 60 Is fixed at 8, and the number of idle columns existing in the interframe gap of the output signal is assumed to be 2 (IN = 9).
[0056]
in this case,
IN = 9
K = 8
Pa = 2
Since there is one idle column in the output signal before the insertion process, the following equation is established.
[0057]
Pb = IG-Pa + 1 = 2-2 + 1 = 1 (4)
INSB = (2 + 1) 8-1-9 = 14 (5)
Further, assuming that the minimum frame length is 72 bytes, the following equation is established.
Brout = (INSB + IN + 72) / (IN + 72) ・ Brin = (95/81) ・ Brin (6)
Another specific example is shown. Here, when the input frame signal FLM1 is a 4-lane byte parallel signal and has a transmission frame configuration of the XGMII standard used in the 10 gigabit standard network, the parallel number K on the output side of the parallel number conversion circuit 60 is calculated. It is assumed that the number of idle columns existing in the interframe gap of the output signal is 2 and (IN = 9).
[0058]
in this case,
IN = 9
K = 10
Pa = 2
Since there is one idle column in the output signal before the insertion process, the following equation is established.
[0059]
Pb = IG-Pa + 1 = 2-2 + 1 = 1 (7)
INSB = (2 + 1) 10-1-9 = 20 (8)
Further, assuming that the minimum frame length is 72 bytes, the following equation is established.
Brout = (INSB + IN + 72) / (IN + 72) ・ Brin = (101/81) ・ Brin (9)
Accordingly, the number of idle bytes INSB to be inserted and the frequency Brout of the internal clock to be generated can be determined in advance.
[0060]
The present invention can be applied not only to signal transmission of the 10 gigabit standard but also to transmission of ultra high speed signals.
[0061]
【The invention's effect】
For example, when an XGMII standard input signal is handled, the minimum number of idle bytes in the interframe gap is 9. When this signal is expanded from, for example, a 4-byte parallel to an 8-byte parallel, an idle column may exist in only one interframe gap among the three interframe gaps. However, by applying the present invention, an idle column can be provided in each interframe gap. Therefore, it is possible to frequently adjust the clock and correct the skew.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration (1) of a main part of a relay device.
FIG. 2 is a flowchart showing an operation example (1) of the idle byte control circuit;
FIG. 3 is a block diagram showing a configuration (2) of a main part of the relay device.
FIG. 4 is a block diagram showing a configuration (3) of a main part of the relay device.
FIG. 5 is a flowchart showing an operation example (2) of the idle byte control circuit;
FIG. 6 is a flowchart illustrating a procedure for determining INSB.
FIG. 7 is a time chart showing a specific example (1) of signal processing.
FIG. 8 is a time chart showing a specific example (2) of signal processing;
FIG. 9 is a schematic diagram illustrating a relationship between a frame gap pattern of an input signal and Pa.
FIG. 10 is a schematic diagram showing a specific example of the required number of idle bytes to be inserted.
FIG. 11 is a time chart showing a conversion example of the arrangement of frame signals.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 10 Idle byte detection circuit 11 End byte detection circuit 12 Start byte detection circuit 20 Idle byte control circuit 30 Processing unit 31 FIFO buffer 32 Selector circuit 33 Idle byte generation circuit 40 Timing adjustment skew correction device 50 Clock generation circuit 60 Parallel number conversion circuit

Claims (7)

An inter-frame gap is arranged between adjacent frames, and a frame signal composed of a plurality of idle bytes is input as a parallel byte sequence assigned to M lanes representing a plurality of M transmission channels. A frame signal processing method for processing the frame signal and rearranging the frame signal into a parallel byte sequence of K lanes assigned to K transmission channels larger than M;
Generate an internal clock signal whose frequency is higher than the clock of the input frame signal,
Insert a new number of idle bytes greater than or equal to the interframe gap of the frame signal,
Monitor the signal accumulation amount of the buffer arranged for temporarily accumulating the frame signal, and according to increase / decrease of the detected signal accumulation amount, insertion or extraction of idle bytes with respect to the interframe gap,
The number of idle bytes to be inserted is adjusted so that a start byte representing the head of each frame moves to a predetermined reference lane on a frame signal rearranged in the parallel byte string of K lanes. Signal processing method. The frame signal processing method according to claim 1, wherein
After the input frame signal is rearranged into parallel lanes of K lanes, idle bytes are inserted into the interframe gap,
The signal accumulation amount of the buffer is compared with a predetermined upper limit value and lower limit value, and in accordance with the comparison result, if the accumulation is insufficient, idle bytes are inserted until the accumulation is not insufficient. Is a frame signal processing method characterized in that idle bytes are extracted until there is no excessive accumulation. The frame signal processing method according to claim 1, wherein
Idle bytes are inserted into the inter-frame gap for the frame signal of the parallel byte sequence of M lanes, and after the processing is completed, the parallel byte sequence of M lanes is rearranged to the parallel byte sequence of K lanes. A frame signal processing method. 2. The frame signal processing method according to claim 1 , wherein the start byte is arranged in the reference lane.
INSB = (Pa + Pb) K-1-IN
Pb = IG-Pa + 1
Pa = 1: When the start byte and the end byte are in the same column Pa = 2: When the start byte is in the column next to the end byte Pa = 3: When the start byte is in the next column after the end byte IN : Minimum value of the number of idle bytes of the input interframe gap IG: When setting the minimum number of idle columns as the design value, insert idle bytes of the number of (INSB + 1−K) or more and INSB or less into the interframe gap,
The frequency Brout of the internal clock signal is determined by the following equation: Brout = α · Brin
Brin: input clock frequency α = (INSB + IN + minimum frame length) / (IN + minimum frame length)
And a frame signal processing method. The frame signal processing method according to claim 4 ,
In order to place the start byte in the reference lane when the input frame signal is a parallel lane of 4 lanes and has an XGMII transmission frame configuration of a 10 gigabit standard network,
INSB = (Pa + Pb) K-1-IN
Pb = IG-Pa + 1
Pa = 1: When the start byte and the end byte are in the same column Pa = 2: When the start byte is in the column next to the end byte Pa = 3: When the start byte is in the next column after the end byte IN : Minimum value of the number of idle bytes of the input interframe gap IG: When setting the minimum number of idle columns as the design value, insert idle bytes of the number of (INSB + 1−K) or more and INSB or less into the interframe gap,
The frequency Brout of the internal clock signal is determined by the following equation: Brout = α · Brin
Brin: input clock frequency α = (INSB + IN + minimum frame length) / (IN + minimum frame length)
And a frame signal processing method. The frame signal processing method according to claim 4 ,
When the input frame signal is a parallel lane of 4 lanes and has an XGMII transmission frame configuration of a 10 gigabit standard network,
In order to convert the output signal into an 8-lane parallel byte sequence and place the start byte in the reference lane,
INSB = 14,
The frequency Brout of the internal clock signal is determined by the following equation: Brout = (95/81) Brin
Brin: Input clock frequency A frame signal processing method characterized by the following. The frame signal processing method according to claim 4 ,
When the input frame signal is a parallel lane of 4 lanes and has an XGMII transmission frame configuration of a 10 gigabit standard network,
In order to convert the output signal into a parallel lane of 10 lanes and to place the start byte in the reference lane,
INSB = 20
The frequency Brout of the internal clock signal is determined by the following equation: Brout = (101/81) Brin
Brin: Input clock frequency A frame signal processing method characterized by the following.

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