JP3968914B2 - Disk array device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a device such as a disk array device that processes a plurality of requests in a multiplexed manner and an access pattern cannot be predicted, and more particularly to a data read control method for operands accessed by a processor.
[0002]
[Prior art]
There is a disk array device that stores and reads data for a plurality of magnetic disk devices (hereinafter referred to as disk devices). In a disk array device, a processor usually performs data control and overall device control. As represented by a disk array device, a system using a processor sequentially processes a program stored in a memory, that is, an instruction code, on the processor. For the operation, an operand which is data on a memory or a register is used. Usually, a system is composed of a processor that performs arithmetic processing, a memory controller that performs memory control, a memory, and a plurality of control LSIs. An example of such a conventional general configuration is shown in FIG.
[0003]
FIG. 9 shows an example of a conventional disk array device. The disk array device roughly includes a plurality of magnetic disk devices 1020 and a disk array control device 1000 that controls the magnetic disk devices. The magnetic disk device 1020 and the disk control device 1000 are connected by a drive IF 1103. The disk array controller 1000 and the host computer 1050 are connected by a host IF 1102. The disk array control apparatus 1000 includes a channel IF unit 1011 that performs connection control with the host computer 1050, a disk IF unit 1012 that performs connection control with the disk device, a shared memory unit 1015 having a shared memory of the entire device, a cache And a cache memory unit 1014 having a memory. The channel IF unit 1011 and the shared memory unit 1015, and the disk IF unit 1012 and the shared memory unit 1015 are connected by an access path 2 137. The channel IF unit 1011 and the cache memory unit 1014, and the disk IF unit 1012 and the cache memory unit 1014 are connected by the access path 0 1135 and the access path 1 1136 via the selector unit 1013. The channel IF unit 1011 includes a host IF 1102, a microprocessor 1101 (hereinafter referred to as a processor), an SM access control unit 1105, a CM access control unit 1104, and an internal bus 1106 that connects them. The disk IF unit 1012 includes a drive IF 1103, a processor 1101, an SM access control unit 1105, a CM access control unit 1106, and an internal bus 1106 for connecting them. The channel IF unit and the cache memory unit include a CM controller 1107 and a memory module 1109 that control the memory. The shared memory unit includes an SM controller 1108 and a memory module 1109 that control the memory. Processors in the channel IF unit and the disk IF unit process data write and read from the host while recognizing the state of the disk array device by accessing operand data in the memory of the shared memory unit and the register of each control unit I do.
[0004]
In such a processor system, in addition to the arithmetic processing performance of the processor, reading performance of operand data from the memory or register to the processor is important. The delay from when the processor requests access until it receives data is called access latency. In recent years, the core performance of processors has been greatly improved, while the read access performance of operand data with external IO access has not been improved much. If the access latency is brought to the surface due to the difference in performance between the two, the processing of the processor is stalled and the processor performance cannot be brought out, so that there is a problem that the memory system becomes a bottleneck on the system.
[0005]
There are roughly two ways to improve operand data access performance. One is performance improvement by reducing access time, and the other is access time concealment. However, in order to reduce the access time, it is necessary to improve the operating frequency of the access path, but mounting noise such as crosstalk is an issue and it is difficult to improve. In particular, in the disk array device as shown in FIG. 9, since the distance between the processor and the operand data is long because a plurality of LSIs are interposed between the processor and the operand data, it is difficult to reduce the access time beyond a certain level. .
[0006]
The second access time concealment includes data prefetching. As a conventional example, there is a prefetch using a dedicated instruction of a processor. As an example, there is a dcbt (Data Cache Block Touch) instruction in the POWERPC instruction set described in “PowerPC Microprocessor Family Programming Environment”. The dcbt instruction is an instruction for reading operand data into a cache inside the processor by a dedicated instruction.
[0007]
However, when a dedicated instruction is used, the external IO access time may require a microsecond order in a large-scale system such as the disk array device already described, and the cache will be cached when data is actually needed. We cannot guarantee if there is data in Further, since a part of the cache is occupied in the order of microseconds, the use efficiency of the cache deteriorates when a plurality of prefetching is executed. In POWERPC, the dcbt instruction is valid for the main memory and cannot be executed for the external IO. Further, it can be realized when a part of processors provided with dedicated instructions is used, and a relatively inexpensive processor used for so-called embedded use does not have such dedicated instructions.
[0008]
[Problems to be solved by the invention]
As described above, with the recent increase in processor speed, the relative performance of operand access accompanied by external IO access represented by external memory and external registers has decreased, resulting in a bottleneck in system performance. It has become. That is, the internal processing performance of the processor is improved as the operating frequency of the processor core unit is improved, but the external IO access speed is not sufficient. Accordingly, the performance of a system that frequently generates external IO access, such as a so-called embedded system, depends on the external IO access performance.
[0009]
The main problem to be solved by the present invention is to improve operand access performance. In particular, it is an object of the present invention to improve the operand data access performance of a processor easily and inexpensively in external IO control.
[0010]
One of the problems common to the operand data access described above is that operand access with a conventional external IO operates only after an external IO request is generated. Therefore, in order to improve the operand data read speed, It is necessary to reduce the access latency from when the processor makes a read request from the memory or register to when it responds, and it is essential to increase the speed of the external IF. High-speed memories such as high-speed SRAMs and dedicated memory for each processor are expensive, leading to an increase in system price. Also, it is difficult to significantly shorten the operand access time.
[0011]
Another problem caused by an increase in access latency is a decrease in the effective performance of the system bus due to an increase in system bus occupancy.
[0012]
[Means for Solving the Problems]
In short, the means of the present invention for solving the above-described problems will be described. Before the operand data is required for the external access control unit, the operand data is previously stored in the memory or the register in the external access control unit. (Referred to as prefetching below). Hereinafter, specific means will be described.
[0013]
A prefetch control unit is provided in the external access control LSI that controls the external access of the processor.
[0014]
The prefetch control unit includes an address register that specifies the address of the memory or register that performs prefetching, an address register valid flag that indicates the validity of the data in the address register, a data register that stores the prefetched data, and the validity of the data in the data register A prefetch register circuit having one or more prefetch register sets each having a data register valid flag indicating the characteristics, an address determination circuit for judging whether the address of the access destination matches the value of the address register, and the prefetch register An access control circuit that performs read-ahead control using the circuit and the address determination circuit is provided.
[0015]
When the prefetch control unit detects a write access to the prefetch register, it stores the write access data in the address register, sets the address register valid bit, and further, for the address indicated by the data stored in the address register. Read access, store the read data in the data register, set the data valid flag, read access to the address that has the address register valid bit set and matches the data stored in the address register If the data valid flag is already set, the data stored in the data register is immediately transmitted. If the data valid flag is not set, the data valid flag is transmitted. Is set in the data register after It transmits the data that has been paid, and to reset the address valid flag and the data valid flag.
[0016]
When a write access to the address stored in the address register of the prefetch register occurs, the prefetch control unit sets the write access data in the data register and sets the data register valid flag.
[0017]
When the prefetch control unit detects a write access to the prefetch register, if all the address register valid flags of the prefetch register set are set, the prefetch is not performed.
[0018]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, the details of the invention will be described with reference to the drawings.
[0019]
First, I will briefly touch on access to the processor 1. The processor accesses the memory and the register via the processor local bus and the external access LSI. At this time, the processor performs all external accesses such as instruction codes, data, and external registers via the processor local bus. Accordingly, the processor can access only one of the areas at the same time.
[0020]
FIG. 1 is an example of a block diagram showing an outline of the present invention. The present embodiment is an example when prefetching is performed for external access. The disk array control apparatus shown in FIG. 1 mainly includes a microprocessor 1, an external access LSI 2, a memory unit 21, and another LSI 23. The processor 1 and the external access LSI 2 are connected by a processor local bus 100. The external access LSI 2 and the memory unit 21 or the other LSI 23 are connected by an inter-LSI connection dedicated IF 20. The memory unit 21 includes a memory control LSI 22 and a memory 24 that directly control the memory. The memory control LSI 22 includes an IF control unit 31 and a register 24 inside. The other LSI 23 includes an IF control unit 31 and a register 24 therein. The external access LSI 2 includes a bus control unit 201, a memory access control unit 3, an external register control unit 9, and an internal bus 202 that connects them. The memory access control unit 3 and the external register control unit 9 have the same configuration. The memory access control unit 3 will be described as an example. The prefetch register 6 for storing the address to be prefetched and the prefetched data, the address determination unit 7 for comparing the address of the data prefetched by the access destination address, and the prefetching It comprises a prefetch control unit 4 and an IF control unit 31 provided with an access control unit 5 that processes access and controls the prefetch register and the address determination unit. Details of the prefetch control unit 4 will be described later with reference to FIGS.
[0021]
As described above, the present embodiment is characterized in that operand data prefetching is realized by providing a dedicated register for prefetching purposes.
[0022]
Next, the operation flow of the method for accessing operand data according to the present invention will be described with reference to FIGS.
[0023]
FIG. 2 is an example of a program according to the present invention. The program 11 starts the prefetch mechanism by writing the operand data address to the prefetch register using a store instruction prior to the read access of the operand data accompanied by the external IO access. Thereafter, the program reads the operand data by a load instruction when the operand data is needed.
[0024]
The present embodiment is characterized in that operand data is prefetched using a store instruction and a load instruction provided in all processors. Accordingly, since a dedicated instruction for prefetching is not required, prefetching of operand data can be realized even with an inexpensive processor for embedded use.
[0025]
FIG. 3 is an operation diagram showing a comparison between the conventional method and the present invention regarding the program operation and the LSI operation according to the present invention. In the conventional method, a load instruction is issued when operand data is required. Thereafter, in order to perform external IO access, the processor is stalled until the operand data is actually read into the processor. On the other hand, in the present invention, prefetching is performed by a store instruction prior to the time when operand data is required. As a result, the external control LSI reads the operand data into the prefetch register. The processor can execute other processes from the time when the prefetch is issued to the time when the operand data is actually read. The store process is at most several cycles in the operation cycle of the processor. On the other hand, the read command depends on the system configuration and is on the order of several microseconds in a large-scale system. Therefore, in the conventional method, the processing is interrupted for several microseconds, whereas in the present invention, the operand data access time can be concealed by performing other processing.
[0026]
Next, an implementation example of the prefetch control unit will be described with reference to FIGS. 4, 5, and 6. FIG. 4 is a block diagram illustrating an example of the prefetch control unit illustrated in FIG. The prefetch register 6 includes an address register 60 that stores an address to be prefetched, an AD valid flag 61 that indicates whether the data in the address register 60 is valid, invalid, a data register 62 that stores operand data, and the data register 62. A plurality of prefetch register sets 64 each having a DT valid flag 63 indicating whether the data is valid or invalid are provided. A register EMTY signal 65 is provided to indicate whether or not there is a space in the register set by the logical product of AD valid flags of all register sets. The address determination circuit 7 includes an access address determination circuit 71 and a prefetch address determination circuit 72. The access address determination circuit 71 includes a comparator that determines whether the address accessed by the processor is an access to the prefetch register, and generates an address match signal 41 that reports the determination result. The prefetch address determination circuit 72 includes a comparator that compares the address accessed by the processor and the prefetch address stored in the prefetch register 6, and whether the address matches the logical product of the result of the comparator and the AD valid flag. Is generated. The comparators are provided in the number corresponding to the prefetch register set. A prefetch hit signal 42 indicating whether or not the address requested by the processor is in the prefetch register is generated by the logical sum of signals from the respective comparators. In this embodiment, a time measuring unit 68 for managing the prefetch register set is provided. The time measurement unit 68 includes a time measurement counter circuit, starts measurement by a measurement activation signal 66 indicating the start of a prefetch operation, and reports a timeout signal 67 when a preset timeout value is exceeded. The prefetch register 6 clears the AD valid flag 61 and the DT valid flag 64 of the corresponding prefetch register set by a time-out signal, interrupts the prefetch process, and releases the prefetch register set 64.
[0027]
Next, the operation of the access control unit 5 will be described. 5 and 6 are flowcharts showing the operation of the access control unit 5. The access control unit 5 can be easily realized by a sequencer from the flowcharts shown in FIGS. FIG. 5 shows a control flow when an access from a processor occurs. Access from the processor can be recognized by decoding the control signal. When an access occurs, first, it is determined whether the access is a write access to the prefetch register from the state of the address match signal and the internal bus control signal (step 1). In the case of write access to the prefetch register, the prefetch routine is started and terminated (step 2). Details of the prefetch routine will be described later with reference to FIG. If it is not a write access to the prefetch register, it is determined whether the access is to the address set in the prefetch register from the state of the prefetch hit signal (step 3). In the case of access to the address set in the prefetch register, it indicates that prefetching has already been activated. In this case, it is determined whether the current access is a write access (step 4). If the access is a write access, the data is stored in the prefetch data register and the DT valid flag is set (step 5). Therefore, if a write access to the same address occurs after pre-reading is activated, the write data becomes valid and no data mismatch occurs. Step 5 ends the access. On the other hand, if it is not an access to the address set in the prefetch register in step 3, it is a normal access not related to the prefetch, and a normal IO access is performed (step 6) and the process is terminated. Further, in step 4, when the access is not a write access, that is, in the case of a read access, the read access to the prefetch address is indicated. In this case, it is confirmed that the DT valid flag is set. If it is not set, the process waits until it is set (step 7). If the DT valid flag is set, it indicates that the prefetch data is stored in the data register, and the prefetch data is transmitted to the processor (step 8). Further, the AD validity flag and the DT validity flag are cleared and the access is terminated (step 9).
[0028]
When pre-read data exists by the above control, the pre-read data can be transmitted to the processor.
[0029]
FIG. 6 shows the flow of control when prefetching is started. When prefetching is activated in step 2 of FIG. 5, it is first determined whether there is an empty register set in the prefetch register (step 1). If there is a vacant register set, the address is stored in the address register and the AD valid flag is set (step 2). Thereafter, the actual data read is started (step 3) and waits until the data reception is completed (step 3). When the data reception is completed, it is determined whether the DT valid flag has already been set (step 5). If the DT valid flag is not already set, the received read data is stored in the data register, the DT valid flag is set (step 6), and the process ends. If the DT valid flag is already set in step 5, it indicates that a write access to the same address has occurred during the pre-read access, and the received data is discarded and the process is terminated. If the prefetch register set is not empty in step 1, the prefetch process is not performed and the process is terminated.
[0030]
FIG. 7 is a block diagram showing another example of the disk array control apparatus according to the present invention. This embodiment is characterized in that the external access LSI 2, the memory control LSI 22, and another LSI 23 are connected by a system bus 24. Since LSIs are connected by a bus, systemization is easy when configuring a small-scale system.
[0031]
FIG. 8 is a block diagram showing another example of the disk array control apparatus according to the present invention. The present invention is characterized in that the memory access control unit 3 including the microprocessor 1 and the prefetch control unit 4 or the external register control unit 9 including the prefetch control unit 4 is provided in the same LSI. Since the frequency of the processor local bus can be increased, the access time from the processor to the prefetch register can be reduced.
[0032]
【The invention's effect】
The effect of the present invention will be described in a word. Before the operand data is required for the external access control unit, the operand data is read in advance from the memory or the register into the register in the external access control unit. Therefore, the operand data access time accompanied by external access can be concealed, and the stall of the processor can be reduced. As a result, the processing performance of the processor can be improved. Hereinafter, specific effects will be described.
[0033]
A prefetch control unit is provided in the external access control unit that controls the external access of the processor. The prefetch control unit is an address register that specifies the address of the memory or register that performs prefetching and an address register that indicates the validity of the data in the address register. A prefetch register circuit having at least one prefetch register set having a flag, a data register for storing prefetched data, and a data register valid flag indicating the validity of the data in the data register, and an address to be accessed is the address register Since the address determination circuit for determining whether or not the value matches, the prefetch register circuit and the access control circuit for performing prefetch control using the address determination circuit, prefetch can be instructed by a store instruction of the processor. There is an effect.
[0034]
When a write access to the address stored in the address register of the prefetch register occurs, the prefetch control unit sets the data of the write access to the data register and sets the data register valid flag. Even when a write to the specified address occurs, there is an effect that data consistency can be obtained.
[0035]
When the prefetch control unit detects a write access to the prefetch register, if all the address register valid flags of the prefetch register set are set, prefetch is not performed, so the prefetch register set can be easily managed. There is an effect that can be realized.
[Brief description of the drawings]
FIG. 1 is an example of a block diagram showing an outline of an external access control unit according to the present invention.
FIG. 2 is a list diagram showing an example of a program according to the present invention.
FIG. 3 is a flowchart showing an example of an operation according to the present invention.
FIG. 4 is a block diagram illustrating an example of a prefetch control unit according to the present invention.
FIG. 5 is a flowchart showing an example of the operation of the access control unit in the prefetch control unit according to the present invention.
FIG. 6 is a flowchart showing an example of the operation of the access control unit in the prefetch control unit according to the present invention.
FIG. 7 is an example of a block diagram showing an outline of an external access control unit according to the present invention.
FIG. 8 is an example of a block diagram showing an outline of an external access control unit according to the present invention.
FIG. 9 is a block diagram showing a conventional example of a disk array device according to the present invention.
[Explanation of symbols]
1 ... Processor 2 ... External access LSI
DESCRIPTION OF SYMBOLS 3 ... Memory access control part 4 ... Prefetch control part 5 ... Access control part 6 ... Prefetch register 7 ... Address determination part 8 ... Data path 9 ... External register control part 8 ... Buffer memory 30 ... Memory part 31 ... IF control part 40 ... Control LSI.

Claims (7)

A disk array device,
A processing unit for executing the instruction code;
A memory for storing operand data related to the instruction code;
A register for storing the operand data;
A prefetch control unit connected to the processing unit, the memory, and the register;
The processing unit executes another instruction code while the prefetch control unit reads the operand data from the memory or the register before issuing a load instruction ,
The prefetch control unit includes:
An address register that specifies the address of the memory or register that performs prefetching, an address register valid flag that indicates the validity of the data in the address register, a data register that stores the prefetched data, and data that indicates the validity of the data in the data register A prefetch register circuit comprising a prefetch register having a register valid flag;
An address determination circuit for determining whether the address of the access destination matches the value of the address register;
An access control circuit that performs prefetch control using the prefetch register circuit and the address determination circuit;
When a write access to the prefetch register is detected, the write access data is stored in the address register, the address register valid flag is set, and a read access is performed to the address indicated by the data stored in the address register. Store read data in the data register, set the data register valid flag,
When a read access to an address matching the address indicated by the data stored in the address register is detected, and the data register valid flag is already set, the data stored in the data register is And when the data register valid flag is not set, the data stored in the data register is transmitted after the data register valid flag is set, and the address register valid flag and the data register valid flag are transmitted. A disk array device characterized by resetting the disk. The disk array device according to claim 1, wherein the prefetch control unit further includes:
The memory prefetch controller that reads the operand data from the memory in advance before the load instruction to load the operand data read from the memory is issued;
A disk array device comprising: the register prefetch controller that reads the operand data from the register in advance before the load instruction for loading the operand data read from the register is issued . The disk array device according to claim 2,
A first dedicated bus connecting the memory prefetch controller and the memory;
A disk array device comprising: the prefetch controller for registers and a second dedicated bus for connecting the registers. The disk array device according to claim 1, wherein
The disk array device, wherein the processing unit and the prefetch control unit are mounted on an LSI package. The disk array device according to claim 1,
The prefetch control unit checks the data register valid flag corresponding to the prefetch target operand data when receiving the prefetch target operand data,
If the data register valid flag has not been set yet, the operand data to be prefetched is written to the data register, and if the data register valid flag has already been set, the operand data to be prefetched is not written to the data register. A disk array device characterized by that. The disk array device according to claim 1, further comprising:
A measurement circuit for measuring the time for which the address register valid flag is set;
The disk array device, wherein when the set time of the address register valid flag becomes longer than a predetermined timeout value, both the address register valid flag and the data register valid flag are reset.   2. The disk array device according to claim 1, wherein when the prefetch control unit detects a write access to the prefetch register, if all the address register valid flags of the prefetch register are set, the prefetch is not performed. A disk array device characterized by the above.

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