JP4061686B2 - Liquid crystal display - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a digital input type liquid crystal display device. Specifically, serial video data is input, and data of each pixel constituting the serial video data is distributed to a plurality of serial / parallel conversion means and converted into parallel data. The present invention relates to a liquid crystal display device that provides a high-resolution display in which the processing time interval of the sample-and-hold circuit in the serial / parallel conversion means has a margin and the number of pixels increases and the bit rate of serial video data increases. is there.
[0002]
[Prior art]
Conventionally, an analog signal is mainly used for a video signal input to a liquid crystal display device used as a display such as a personal computer. However, with the rapid digitization of peripheral devices in recent years, the number of input video signals that have been digitized also increases in liquid crystal display devices. However, in the case of such a digital input system, since the video signal is input to the liquid crystal display device as n-bit parallel data, if the number of bits of the video signal is increased in order to improve the image quality, the corresponding input terminal It is also necessary to increase the number. When the number of input terminals is increased, problems such as the influence of disturbances such as static electricity on the input terminals and the reliability of the terminal connection portion are caused.
[0003]
In order to solve this problem, n-bit parallel data as a video signal for determining the display state of the liquid crystal display panel is converted into serial data and then input to the liquid crystal display device. This serial data is provided inside the liquid crystal display device. In addition, a liquid crystal display device has been proposed in which the number of input terminals can be reduced by returning to n-bit parallel data again with a serial / parallel converter.
[0004]
The liquid crystal display device 10 in FIG. 3 is a liquid crystal display device to which serial video data is input. An analog video signal SV is converted into n-bit parallel video data PVD (D _{0 to} D _n-1 ) by an A / D (analog / digital) converter 2 at an input terminal 6 of the liquid crystal display device 10. Is further converted into serial video data SVD by a P / S (parallel / serial) converter 4 and supplied.
[0005]
FIG. 4 shows a schematic configuration of the above-described conventional liquid crystal display device 10. The liquid crystal display device 10 includes an input terminal 6 for inputting serial video data SVD, and an S / P (serial / parallel) converter 11 for converting the input serial video data SVD into n-bit parallel video data PVD. From a D / A (digital / analog) converter 12 that converts parallel video data PVD output from the S / P converter 11 into an analog video signal SV, a liquid crystal display panel 15, and a D / A converter 12. A selector 14 that distributes and supplies pixel signals constituting each line of the output analog video signal SV to the N signal lines X _{1 to} X _N of the liquid crystal display panel 15, a D / A converter 12, and a selector 14 And a buffer 13 disposed between them. As a result, an image corresponding to the serial video data SVD input to the input terminal 6 is displayed on the liquid crystal display panel 15.
[0006]
FIG. 5 shows a specific configuration of the S / P converter 11. The S / P converter 11 includes n sample and hold circuits 20 _{0 to} 20 _n−1 and n sample and hold circuits 21 _{0 to} 21 _n−1 . In this case, the serial video data SVD is input to the sample-and-hold circuit 20 ₀ ~20 _n-1, an input each of these sample and hold circuits 20 ₀ ~20 _n-1 of the output signal to the sample hold circuit 21 ₀ ~21 _n-1 Is done.
[0007]
In such a configuration, sampling pulses φ0 to φn−1 are supplied to the sample hold circuits 20 _{0 to} 20 _n−1 at the timing shown in FIG. 6B for each bit data of the serial video data SVD (FIG. 6A). Then, the bit data D _{0 to} D _n-1 are sequentially sampled and held. Further, the sample hold circuits 21 _{0 to} 21 _n-1 are supplied with the sampling pulse φr at the timing shown in FIG. 6C, and the bit data D _{0 to} D _n-1 are sampled and held all at once. Therefore, n-bit parallel video data PVD is output from the sample hold circuits 21 _{0 to} 21 _n−1 .
[0008]
[Problems to be solved by the invention]
By the way, the above-described conventional liquid crystal display device 10 is configured by providing only one system of the S / P converter 11 and the D / A converter 12 for the input serial video data SVD. . That is, all the serial data of N pixels constituting the serial video data SVD of each line is converted into parallel data by the S / P converter 11. Therefore, the processing time interval of the sample / hold circuit of the S / P converter 11 has no margin.
[0009]
Therefore, when the number of pixels increases and the bit rate of the serial video data SVD increases, it becomes difficult to perform S / P conversion processing, and it is difficult to perform high-resolution display.
[0010]
Therefore, according to the present invention, a high-resolution display in which the bit rate of serial video data is increased by increasing the number of pixels by providing a margin for the processing time interval of the sample and hold circuit in one S / P converter can be satisfactorily performed. An object is to provide a liquid crystal display device.
[0011]
The liquid crystal display device according to the present invention includes an input terminal for serial video data, serial / parallel conversion means for distributing serial video data input to the input terminal and converting it into parallel data, and the serial / parallel conversion means. A digital / analog conversion means for converting the output parallel video data into an analog signal, and a liquid crystal display panel for displaying an image based on the analog video signal supplied with the analog video signal output from the digital / analog conversion means. The serial / parallel conversion means and the digital / analog conversion means are provided in a plurality of systems in parallel. In the serial / parallel conversion means provided in parallel, the serial / parallel conversion means is provided. For each pixel supplied to each Alternatively, the serial video data for a plurality of non-consecutive pixels are converted into parallel data in parallel, and the digital / analog conversion means converts the parallel data supplied from the serial / parallel conversion means into the analog video in parallel. It is converted into a signal.
[0012]
Serial video data input to the input terminal is supplied to a plurality of S / P converters. Data of each pixel constituting the serial video data is distributed to a plurality of S / P converters and converted into parallel video data. In addition, parallel video data output from a plurality of S / P converters is converted into analog video signals by corresponding D / A converters. Then, analog video signals output from a plurality of D / A converters are supplied to corresponding signal lines of the liquid crystal display panel.
[0013]
As a result, the processing time interval of the sample-and-hold circuit in one serial / parallel conversion means can be provided, and high-resolution display in which the number of pixels increases and the bit rate of serial video data increases can be performed satisfactorily. Can do.
[0014]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, a first embodiment of the present invention will be described with reference to the drawings. FIG. 1 shows a configuration of a liquid crystal display device 100 as a first embodiment. In this first embodiment, when the number of signal lines of the liquid crystal display panel is N, N systems of S / P converters and D / A converters are provided in parallel. In FIG. 1, parts corresponding to those in FIG.
[0015]
The liquid crystal display device 100 includes an input terminal 6 for inputting serial video data SVD, and N S / P converters 11 ₁ to 11 11 for converting the input serial video data SVD into n-bit parallel video data PVD. 11 _N. These S / P converters 11 _{1 to} 11 _N are configured in the same manner as the S / P converter 11 in the liquid crystal display device 10 shown in FIG. 4 (see FIG. 5). In these S / P converters 11 _{1 to} 11 _N , for each line, one pixel of serial data of N pixels constituting the serial video data of the line is converted into parallel data.
[0016]
The liquid crystal display device 100 also includes N D / A converters 12 _{1 to} 12 _N that convert parallel video data PVD output from the S / P converters 11 _{1 to} 11 _N into analog video signals SV, and The liquid crystal display panel 15 and the analog video signals SV _{1 to} SV _N as the pixel signals of the lines respectively output from the D / A converters 12 _{1 to} 12 _{N for} each line are used as _N signals of the liquid crystal display panel 15. and a buffer 13 ₁ to 13 _N and supplies the line X ₁ to X _N.
[0017]
In the above configuration, the serial video data SVD input to the input terminal 6 is supplied to the S / P converters 11 _{1 to} 11 _N. In each of the S / P converters 11 _{1 to} 11 _N , for each line, one pixel of serial data of N pixels constituting serial video data of the line is converted into parallel data. For example, serial data of N pixels constituting one line of serial video data is d ₁ [D _{0 to} D _n-1 ], d ₂ [D _{0 to} D _n-1 ],..., D _N [D ₀ when to D _n-1] is, only the S / P converter 11 _{1, d 1 [D 0 ~D n-} 1] is converted into parallel data, the S / P converter 11 _2, d ₂ [D _{0 to} D _n-1 ] are converted into parallel data. Similarly, in the S / P converters 11 _{3 to} 11 _N , d ₃ [D _{0 to} D _n-1 ] to d _N [D _{0 to} D _{n, respectively. -1} ] is converted into parallel data.
[0018]
Further, the parallel data output from S / P converter 11 ₁ to 11 _N is converted into an analog signal is supplied to the D / A converter 12 ₁ to 12 _N, respectively. The analog video signal SV ₁ Sv outputted from the D / A converter 12 ₁ to 12 _{N N} is, N of signal lines X ₁ of the liquid crystal display panel 15 via a buffer 13 ₁ to 13 _N respectively ~X Supplied to _N. Accordingly, analog signal signals SV _{1 to} SV _N related to serial data of N pixels constituting serial video data of the line are supplied to the _N signal lines X _{1 to} X _N of the liquid crystal display panel 15 for each line. Is done. As a result, an image corresponding to the serial video data SVD input to the input terminal 6 is displayed on the liquid crystal display panel 15.
[0019]
As described above, in the first embodiment, the S / P converters 11 _{1 to} 11 _N perform the S / P conversion process only once for each line. Therefore, the sample hold circuit in each of the S / P converters 11 _{1 to} 11 _N is different from the liquid crystal display device 10 shown in FIG. 4 having one S / P converter and one D / A converter. The processing time interval can be afforded, and high-resolution display in which the number of pixels increases and the bit rate of serial video data increases can be performed satisfactorily.
[0020]
Next explained is the second embodiment of the invention. FIG. 2 shows a configuration of a liquid crystal display device 110 as the second embodiment. In the second embodiment, when the number of signal lines of the liquid crystal display panel 15 is N (= 4 × Q), S / P converters and D / A converters are provided in Q systems in parallel. It is. In FIG. 2, parts corresponding to those in FIG.
[0021]
The liquid crystal display device 110 includes an input terminal 6 for inputting serial video data SVD, and Q S / P converters 11 ₁ to 11 for converting the input serial video data SVD into n-bit parallel video data PVD. 11 _Q. Each of these S / P converters 11 _{1 to} 11 _Q is configured similarly to the S / P converter 11 in the liquid crystal display device 10 shown in FIG. 4 (see FIG. 5). In each of these S / P converters 11 _{1 to} 11 _Q , for each line, four pixels at an interval of Q pixels are converted into parallel data among the serial data of N pixels constituting the serial video data of the line. .
[0022]
The liquid crystal display device 110 includes a latch portion 30 ₁ to 30 _Q for latching the parallel video data PVD ₁ ~PVD _Q of four pixels are sequentially output from the S / P converter 11 ₁ to 11 _Q in each line, Q-number of D / a converter for converting a parallel video data PVD ₁ ~PVD _Q of four pixels which are sequentially output from the latches portions 30 ₁ to 30 _Q in each line into an analog video signal SV ₁ ~SV _Q 12 ₁ ~ 12 _Q. Each of the latch units 30 ₁ to 30 _Q includes four latch circuits.
[0023]
In addition, the liquid crystal display device 110 receives the analog video signals SV _{1 to} SV _Q for four pixels sequentially output on each line from the liquid crystal display panel 15 and the D / A converters 12 _{1 to} 12 _Q. The selectors 14 _{1 to} 14 _Q selectively supplied to the 15 corresponding signal lines and the analog video signals SV _{1 to} SV _Q output from the D / A converters 12 _{1 to} 12 _Q are respectively selected from the selectors 14 _{1 to} 14 _Q. And buffers 13 _{1 to} 13 _Q to be supplied. Here, the output switching of the four latch circuits in the latch units 30 ₁ to 30 _Q and the switching of the output signal lines in the selectors 14 _{1 to} 14 _Q are performed in conjunction with each other.
[0024]
In the above configuration, the serial video data SVD input to the input terminal 6 is supplied to the S / P converters 11 _{1 to} 11 _Q. In each of the S / P converters 11 _{1 to} 11 _Q , for each line, four pixels at the Q pixel interval are converted into parallel data among the N pixel serial data constituting the serial video data of the line. The For example, serial data of N pixels constituting one line of serial video data is d ₁ [D _{0 to} D _n-1 ], d ₂ [D _{0 to} D _n-1 ],..., D _N [D _{0 to} D _n-1 ], the S / P converter 11 ₁ has d ₁ [D _{0 to} D _n-1 ], d _{Q + 1} [D _{0 to} D _n-1 ], d _{2Q + 1} [ _{D 0 ~D n-1],} d 3Q + 1 [D 0 ~D n-1] is converted into parallel data, S / P converter 11 _{2, d 2 [D 0 ~D n-} 1], d _{Q + 2} [D _{0 to} D _n-1 ], d _{2Q + 2} [D _{0 to} D _n-1 ], d _{3Q + 2} [D _{0 to} D _n-1 ] are converted into parallel data, and S / Similarly, in the P converters 11 _{3 to} 11 _Q , four pixels at the Q pixel interval are converted into parallel data.
[0025]
Further, the parallel video data PVD _{1 to} PVD _Q for four pixels sequentially output from the S / P converters 11 _{1 to} 11 _Q on each line are supplied to and latched by the latch units 30 ₁ to 30 _Q , respectively. Then, the parallel video data PVD _{1 to} PVD _Q for four pixels sequentially output from the latch units 30 ₁ to 30 _Q on each line are supplied to the D / A converters 12 _{1 to} 12 _Q , respectively, to be analog video signals. Converted to SV _{1 to} SV _Q.
[0026]
The analog video signals SV _{1 to} SV _Q for four pixels sequentially output from the D / A converters 12 _{1 to} 12 _Q on each line pass through the buffers 13 _{1 to} 13 _Q and the selectors 14 _{1 to} 14 _Q , respectively. The signal is supplied to the corresponding signal line of the display panel 15. Therefore, the N video lines of the liquid crystal display panel 15 are supplied with an analog video signal related to serial data of N pixels constituting serial video data of the line for each line. As a result, an image corresponding to the serial video data SVD input to the input terminal 6 is displayed on the liquid crystal display panel 15.
[0027]
As described above, in the second embodiment, the S / P converters 11 _{1 to} 11 _Q perform the S / P conversion process only four times at intervals of Q pixels on each line. Therefore, the sample hold circuit of each of the S / P converters 11 _{1 to} 11 _Q is different from that of the liquid crystal display device 10 shown in FIG. 4 having one system of S / P converter and D / A converter. The processing time interval can be afforded, and high-resolution display in which the number of pixels increases and the bit rate of serial video data increases can be performed satisfactorily. In addition, when the number of signal lines of the liquid crystal display panel 15 is N (= 4 × Q), the S / P converter and the D / A converter are provided in Q systems in parallel. The first system shown in FIG. There is an advantage that the circuit scale can be reduced as compared with the embodiment.
[0028]
In the second embodiment shown in FIG. 2, the system of S / P converters and D / A converters is provided by 1/4 of the number of signal lines of the liquid crystal display panel 15. Is an example and the present invention is not limited to this. In short, the number of systems may be set so as to allow a margin for the processing time interval of the sample hold circuit in the S / P converter.
[0029]
【The invention's effect】
According to the present invention, serial video data is input, and data of each pixel constituting the serial video data is distributed to a plurality of S / P converters and converted into parallel data. Therefore, the processing time interval of the sample-and-hold circuit in one S / P converter can be afforded, and high-resolution display in which the number of pixels is increased and the serial video data bit rate is increased can be satisfactorily performed. it can.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of a liquid crystal display device as a first embodiment.
FIG. 2 is a block diagram illustrating a configuration of a liquid crystal display device as a second embodiment.
FIG. 3 is a block diagram showing a schematic configuration of a serial data input type liquid crystal display device.
FIG. 4 is a block diagram showing a configuration of a conventional liquid crystal display device.
FIG. 5 is a block diagram showing a specific configuration of an S / P converter.
FIG. 6 is a timing chart showing sampling timing of a sample hold circuit constituting the S / P converter.
[Explanation of symbols]
6 ... input terminal, 11 _{1 to} 11 _N ... S / P converter, 12 _{1 to} 12 _N ... D / A converter, 13 _{1 to} 13 _N ... buffer, 14 _{1 to} 14 _Q ... Selector, 15 ... Liquid crystal display panel, 20 _{0 to} 20 _n-1 , 21 _{0 to} 21 _n-1 ... Sample hold circuit, 30 ₁ to 30 _Q ... Latch section, 100, 110 ..Liquid crystal display devices

Claims (4)

Serial video data input terminal,
Serial / parallel conversion means for dispersing and converting serial video data input to the input terminal into parallel data;
Digital / analog conversion means for converting parallel video data output from the serial / parallel conversion means into analog signals;
A liquid crystal display device including an analog video signal output from the digital / analog conversion means and a liquid crystal display panel for displaying an image based on the analog video signal,
The serial / parallel conversion means and the digital / analog conversion means are provided in parallel in a plurality of systems,
In the serial / parallel conversion means provided in parallel, the serial video data for one pixel or a plurality of non-consecutive pixels supplied to the serial / parallel conversion means is converted into parallel data in parallel. ,
In the digital / analog conversion means, the parallel data supplied from the serial / parallel conversion means is converted into the analog video signal in parallel. When the number of signal lines of the liquid crystal display panel is N, the plurality of systems are N systems,
In each of the N systems of serial / parallel conversion means, for each line, one pixel of serial data of N pixels constituting serial video data of the line is converted into parallel data,
2. The analog video signal relating to the serial data of the N pixels output from the N systems of digital / analog conversion means is supplied to N signal lines of the liquid crystal display panel, respectively. The liquid crystal display device described. When the liquid crystal display panel has N signal lines, the plurality of systems are M systems (M <N),
In each of the M systems of serial / parallel conversion means, for each line, one pixel of serial data of N pixels constituting serial video data of the line or a plurality of non-continuous pixels are converted into parallel data,
2. The analog video signal relating to the serial data of the N pixels output from the M systems of digital / analog conversion means is supplied to N signal lines of the liquid crystal display panel, respectively. A liquid crystal display device according to 1.   Between the digital / analog conversion means and the liquid crystal display panel of the same system as the serial / parallel conversion means for converting the non-continuous pixels into parallel data, the plurality of pixels output from the digital / analog conversion means. 4. The liquid crystal display device according to claim 3, further comprising a selector for distributing and supplying the analog video signal to the corresponding signal lines of the liquid crystal display panel.

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