JP4161454B2 - Display element, driving method thereof, and display device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a display element, a driving method thereof, and a display device, and more particularly to a self-luminous display element having a memory property.
[0002]
[Prior art]
As mobile computing becomes popular, there is an increasing demand for flat display devices. Conventionally, a liquid crystal display device has been generally used as a flat display device. However, the liquid crystal display device has problems such as a narrow viewing angle and poor response characteristics.
[0003]
On the other hand, in recent years, organic electroluminescence (EL) display devices have attracted attention as flat-type self-luminous display devices with good response characteristics and wide viewing angles. Since the organic EL element used in such an organic EL display device emits light at a high luminance of a predetermined luminance or higher, the light emission efficiency is remarkably lowered. Therefore, the same display luminance (instantaneous luminance value and time) Therefore, it is possible to extend the lifetime of the organic EL element by emitting light at a low luminance for a long time rather than emitting light at a high luminance for a short time. For this reason, it is important to provide a memory property to the voltage applied between the electrodes of the organic EL element.
[0004]
FIG. 9 shows an equivalent circuit for one pixel of a conventional organic EL display element that realizes such a voltage memory property. As shown in the figure, this organic EL element includes an organic EL element 251 constituting a light emitting region of a pixel, a driving transistor 252 for applying a voltage to the organic EL element 251, and a voltage applied by the driving transistor 252. The capacitor 253 to be held and a selection transistor 254 for selecting and writing an image signal to the capacitor 253 are configured. The gate of the selection transistor 254 is connected to the gate driver via the gate line gl, and the drain is connected to the drain driver via the drain line dl.
[0005]
When driving the organic EL element 251, the selection transistor 254 corresponding to the organic EL element 251 to be driven in the matrix is selected by the selection signal from the gate driver, and the drain line from the drain driver to the capacitor 253 of the selected line is selected. dl, the image signal is written through the selection transistor 254. The driving transistor 252 drives the organic EL element 251 in accordance with the magnitude of the image signal written in the capacitor 253, and applies a voltage corresponding to the gradation to the organic EL element 251 to display a desired image. Display.
[0006]
As described above, in the conventional organic EL display element, the image signal written from the driving transistor 252 is held in the capacitor 253, and the light emission of the organic EL element 251 is maintained for almost one frame period by the image signal held in the capacitor 253. It was. Therefore, in this organic EL display element, sufficient display luminance can be obtained without causing the organic EL element 251 to emit light with high luminance, and a display image can be obtained efficiently with low power consumption.
[0007]
However, in the conventional organic EL display element, in addition to the organic EL element 251, a driving transistor 252, a capacitor 253, and a selection transistor 254 have to be formed for each pixel. By the way, when any of these constituent elements is defective, the entire organic EL display element becomes a defective product. However, in the organic EL display element of the above-described conventional example, the number of constituent elements is large. As a result, the probability of defects occurring in the wafer becomes high, resulting in a problem that the yield during manufacturing is lowered.
[0008]
Further, as shown in the plan view of FIG. 10, it is necessary to form the driving transistor 252, the capacitor 253, and the selection transistor 254 in addition to the organic EL element 251 in the region for one pixel. There is a problem that a region where the element 251 can be formed becomes relatively small, and the pixel aperture ratio becomes small.
[0009]
[Problems to be solved by the invention]
The present invention has been made to solve the above-described problems of the conventional example. A display element having a high pixel aperture ratio and a high manufacturing yield, a method for driving the display element, and the An object is to provide a self-luminous display device using such a display element.
[0010]
[Means for Solving the Problems]
In order to achieve the above object, a display element according to the first aspect of the present invention includes:
A display element in which a plurality of pixels are arranged vertically and horizontally in a predetermined arrangement,
Each of the plurality of pixels is
A lower gate electrode; a lower gate insulating film formed on the lower gate electrode; a semiconductor layer that is excited by incident light to generate carriers therein; and a drain electrode and a source connected to the semiconductor layer, respectively An upper gate insulating film formed on the semiconductor layer, the drain electrode and the source electrode, and a trap region for trapping carriers generated in the semiconductor layer at an interface with the semiconductor layer; A memory formed on the upper gate insulating film at a position corresponding to the semiconductor layer and traps carriers in the semiconductor layer in a trap region of the upper gate insulating film according to a supplied voltage. Elements,
A light emitting element that is connected to a drain electrode or a source electrode of the memory element and emits light by a current flowing through a channel formed in the semiconductor layer when a voltage corresponding to data reading is supplied to the lower gate electrode;
It is characterized by providing.
[0011]
In the display element described above, only the memory element described above may be formed in addition to the light emitting element in order to provide memory characteristics in each pixel. The constituent elements of the memory element are sequentially stacked and do not require a large area. For this reason, the display element can increase the relative area of the light emitting element, that is, the pixel aperture ratio. In addition, since the number of elements constituting one pixel is only two, that is, a memory element and a light emitting element, the possibility that any element which is a constituent element has a defect is low, and the yield in manufacturing is reduced. Get higher.
[0012]
In the display element, a voltage supplied to the lower gate electrode when erasing or writing data can form a channel in the semiconductor layer. In this case, one of the holes or electrons of the carriers trapped in the upper gate insulating film pinches off the channel formed in the semiconductor layer by the voltage supplied to the lower gate electrode when reading data. In addition, by preventing current from flowing between the drain electrode and the source electrode, current can be prevented from flowing through the light emitting element.
[0013]
In the display element, the type of carriers trapped in the trap region may be different by making the voltage supplied to the upper gate electrode different.
[0014]
In addition, the said light emitting element can be made into an organic electroluminescent element, for example.
[0015]
In the display element, it is preferable that the memory element further includes a light blocking unit that allows only light emitted from the light emitting element of the same pixel to enter and blocks light emitted from the light emitting element of the adjacent pixel. To do.
[0016]
In the display element, the light emitting element may emit light including all of light in a red wavelength range, light in a green wavelength range, and light in a blue wavelength range. In this case, each of the plurality of pixels includes a red color filter that transmits light in a red wavelength region out of light emitted from the light emitting element and emits the light to the outside, and green among light emitted from the light emitting element. A green color filter that transmits light in the wavelength region of the light and emits the light to the outside, and a blue color filter that transmits blue light of the light emitted from the light emitting element and emits the light to the outside The red color filter, the green color filter, or the blue color filter can be arranged in each of the plurality of pixels in a predetermined order according to the arrangement of the pixels.
[0017]
In the display element, each light emitting element of the plurality of pixels may emit one of light in a red wavelength range, light in a green wavelength range, and light in a blue wavelength range. . In this case, the light emitting element that emits light in the red wavelength band, the light emitting element that emits light in the green wavelength band, or the light emitting element that emits light in the blue wavelength band is in a predetermined order according to the arrangement of the pixels. Can be arranged in each of the plurality of pixels.
[0018]
By displaying a color filter that transmits light in different wavelength ranges of red, green, and blue, or by arranging light emitting elements that emit light in different wavelength ranges of red, green, and blue, the display element can display a full-color image. It can be displayed.
[0019]
In order to achieve the above object, a display element driving method according to a second aspect of the present invention includes:
A driving method of a display element in which pixels are arranged in a matrix,
Each pixel of the display element is
A lower gate electrode; a lower gate insulating film formed on the lower gate electrode; a semiconductor layer that is excited by incident light to generate carriers therein; and a drain electrode and a source connected to the semiconductor layer, respectively An upper gate insulating film formed on the semiconductor layer, the drain electrode and the source electrode, and a trap region for trapping carriers generated in the semiconductor layer at an interface with the semiconductor layer; A memory formed on the upper gate insulating film at a position corresponding to the semiconductor layer and traps carriers in the semiconductor layer in a trap region of the upper gate insulating film according to a supplied voltage. Elements,
A light emitting element that is connected to a drain electrode or a source electrode of the memory element and emits light by current flowing through a channel formed in the semiconductor layer when a voltage corresponding to data reading is supplied to the lower gate electrode; Prepared,
The driving method is:
A selection step of selecting a plurality of pixels in a matrix for each row and sequentially supplying a predetermined voltage corresponding to erasing and writing of data to the lower gate electrode;
A voltage corresponding to data erasure or writing is supplied to the upper gate electrode of the memory element of the pixel in the row selected by the selection step, and either a hole or an electron in the carrier is trapped in the trap region. A memory step for storing data, and
After the selection in the selection step, a voltage corresponding to data read is applied to the lower gate electrode and the upper gate electrode of all the memory elements of the plurality of pixels until the selection in the next selection step. A light emitting step of supplying and supplying a predetermined voltage to the drain electrode or the source electrode to cause the corresponding light emitting element to emit light according to a state stored in each memory element; and
It is characterized by including.
[0020]
In order to achieve the above object, a display device according to the third aspect of the present invention provides:
A lower gate electrode; a lower gate insulating film formed on the lower gate electrode; a semiconductor layer that is excited by incident light to generate carriers therein; and a drain electrode and a source connected to the semiconductor layer, respectively An upper gate insulating film formed on the semiconductor layer, the drain electrode and the source electrode, and a trap region for trapping carriers generated in the semiconductor layer at an interface with the semiconductor layer; A memory formed on the upper gate insulating film at a position corresponding to the semiconductor layer and traps carriers in the semiconductor layer in a trap region of the upper gate insulating film according to a supplied voltage. Connected to the drain electrode or the source electrode of the memory element and the lower gate electrode. When the voltage corresponding to the out is supplied, and a display device and a light emitting element which emits light by a current flowing through the channel formed in the semiconductor layer, each of a plurality of pixels arranged in a matrix,
Selecting means for selecting the memory element corresponding to any row of pixels and sequentially supplying a voltage corresponding to erasing and writing of data to the lower gate electrode;
When a voltage corresponding to erasing and writing of data is supplied from the selection means to the lower gate electrode, a voltage corresponding to erasing or writing of data is supplied to the upper gate electrode of the corresponding memory element to Memory means for storing
All selection means for supplying a voltage corresponding to data reading to the lower gate electrodes of the memory elements of all pixels;
When a voltage corresponding to data reading is supplied to the lower gate electrode by the all selection means, a predetermined voltage is supplied to the drain electrode or the source electrode to form the semiconductor layer. A light emitting means for causing a current to flow through the channel to the corresponding light emitting element;
Control means for controlling the selection means, the memory means, the full selection means and the light emitting means,
It is characterized by providing.
[0021]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the accompanying drawings.
[0022]
FIG. 1 is a block diagram showing the configuration of the organic EL display device according to this embodiment. As shown, the organic EL display device includes an organic EL display panel 1, an address driver 2, a data driver 3, an EL drive voltage generation circuit 4, and a controller 5.
[0023]
The organic EL display panel 1 has (m × n) pixels formed in a matrix. As shown in an equivalent circuit diagram in the figure, each pixel has a double gate memory transistor 11 and an organic EL element. 12 are provided.
[0024]
The double gate memory transistor 11 is a memory element that stores data according to the voltage applied to each of the two gates and the incident light. The top gate of the double gate memory transistor 11 is connected to m columns of data lines DL1 to DLm, the bottom gate is connected to n rows of address lines AL1 to ALn, and the drain is connected to n rows of voltage lines VL1 to VLn. The source is connected to the anode of the organic EL element 12. Details of the double gate memory transistor 11 will be described later.
[0025]
The organic EL element 12 has an anode connected to the source of the double-gate memory transistor 11 and a cathode grounded, and the current flowing between the anode and the cathode is applied with a voltage higher than a threshold value. It is a self-luminous element in which an organic semiconductor provided therebetween emits light. Details of the organic EL element 12 will be described later.
[0026]
Next, the structure of the organic EL display panel 1 will be described in detail.
2A is a plan view showing the structure of the organic EL display panel 1 of FIG. 1, and FIG. 2B is a cross-sectional view taken along line AA of FIG. 2A. In these drawings, only one pixel among the pixels formed in a matrix on the organic EL display panel 1 is shown.
[0027]
As shown in FIGS. 2A and 2B, in the organic EL display panel 1, first, Cr is formed on the upper layer and dark CrO is formed on the lower layer on the glass substrate 10. _x The bottom gate electrode 11a of the double gate memory transistor 11 having a light shielding property is formed. The bottom gate electrode 11 a is formed integrally with the address line AL connected to the address driver 2.
[0028]
A bottom gate insulating film 11b made of SiN is formed on the glass substrate 10 so as to cover the bottom gate electrode 11a and the voltage line VL. On the bottom gate insulating film 11b, a semiconductor layer 11c of the double gate memory transistor 11 made of a-Si is formed at a position corresponding to the bottom gate electrode 11a.
[0029]
A drain electrode 11e and a source electrode 11f of the double gate memory transistor 11 are formed on both sides of the semiconductor layer 11c via an n + Si layer 11d. The drain electrode 11 e is formed integrally with the voltage line VL connected to the EL drive voltage generation circuit 4. On top of these, light having a light-shielding property is formed by cutting out only the direction toward the organic EL layer 12b of the same pixel and forming a film with a thickness that blocks light from the organic EL layer 12b of other pixels. A block layer 11g is formed. Further, a top gate insulating film 11h made of SiN is formed on the bottom gate insulating film 11b so as to cover them.
[0030]
A top gate electrode 11i of the double gate memory transistor 11 having a two-layer structure made of Al or an Al alloy and having a light shielding property is formed so as to include a position facing the semiconductor layer 11c on the top gate insulating film 11h. ing. The top gate electrode 11 i is formed integrally with the data line DL connected to the data driver 3. An insulating protective film 11j made of SiN is formed on the top gate insulating film 11h and the data line DL.
[0031]
Note that the top gate insulating film 11h has a higher Si ratio in the vicinity of the interface with the semiconductor layer 11c or the bottom gate insulating film 11b than other portions, and Si: N≈1: 1, and the carrier (positive A trap region (indicated by “− − − − −” in the figure) for trapping holes or electrons) is formed. It should be noted that Si: N≈3: 4 in the region of the bottom gate insulating film 11b and the top gate insulating film 11h in the vicinity of the top gate electrode 11i.
[0032]
On the other hand, on the top gate insulating film 11h, the bottom gate electrode 11a, the semiconductor layer 11c, the drain electrode 11e, the source electrode 11f and the top gate electrode 11i (that is, the double gate memory transistor 11), the address line AL, the data line DL, and At a position where the voltage line VL is not formed, a color filter 13 that transmits light in a predetermined wavelength region out of light emitted from the organic EL layer 12b is formed.
[0033]
On the color filter 13, an anode electrode 12a of an organic EL element 12 made of transparent ITO (Indium Tin Oxide) is formed. The anode electrode 12a is connected to the source electrode 11f of the double gate memory transistor 11 through a contact hole indicated by a dotted circle in FIG.
[0034]
An organic EL layer 12b is formed on the entire surface of the organic EL display panel 1 so as to cover all of the above. A cathode electrode 12c made of MgAg, MgIn, AlLi or the like is formed on the organic EL layer 12b. The cathode electrode 12c is grounded.
[0035]
The organic EL layer 12b is made of 30 wt% 1,3,4-oxadiazole, 3 mol% tetraphenylbutadiene derivative, 0.04 mol% in poly (N-vinylcarbazole) which is a binder / charge transport layer. Of coumarin 6, 0.02 mol% DCM1, 0.015 mol% Nile Red.
[0036]
Since the organic EL layer 12b is made of a material having such a composition, recombination of electrons and holes caused by a current flowing when a voltage is applied between the anode electrode 12a and the cathode electrode 12c. It absorbs the accompanying energy and emits white light (including all light in the red wavelength band, light in the green wavelength band, and light in the blue wavelength band). Further, the cathode electrode 12c is reflective to the light emitted from the organic EL layer 12b and blocks light incident on the cathode electrode 12c from the upper part of the figure to be applied to the semiconductor layer 11c of the double gate memory transistor 11. Prevents incidence.
[0037]
In addition, among the white light emitted from the organic EL layer 12b, the color filter 13 transmits light in the red wavelength band (R), transmits light in the green wavelength band (G), and blue wavelength. Any one (B) that transmits the light of the region is provided in each pixel in a diagonal array as shown in FIG.
[0038]
Next, the operation principle of the double gate memory transistor 11 will be described in detail with reference to the schematic diagrams shown in FIGS.
[0039]
First, in the case of storing light emission, as shown in FIG. 4A, −20 (V) is applied to the top gate electrode 11i, +35 (V) is applied to the bottom gate electrode 11a, and V is applied to the drain electrode 11e. _x Apply (V). The source electrode 11f is connected to the anode of the organic EL element 12, and the cathode of the organic EL element 12 is grounded. At this time, +35 (V) of the bottom gate electrode 11a attracts electrons in the semiconductor layer 11c to the bottom gate electrode 11a side, and an n-channel is formed in the semiconductor layer 11c. When an electric current flows through the n channel, the organic EL element 12 emits light, and the light enters the semiconductor layer 11c. As a result, the semiconductor layer 11c is photoexcited to generate carriers (holes and electrons), and the holes are attracted by −20 (V) of the top gate electrode 11i and trapped in the trap region of the bottom gate insulating film 11h. Is done. This state is a data erasing state in the double gate memory transistor 11 and corresponds to a case where the value of display image data img described later is “1”.
[0040]
Next, when storing non-light emission, as shown in FIG. 4B, +20 (V) is applied to the top gate electrode 11i, +35 (V) is applied to the bottom gate electrode 11a, and V is applied to the drain electrode 11e. _x Apply (V). The source electrode 11f is connected to the anode of the organic EL element 12, and the cathode of the organic EL element 12 is grounded. At this time, +35 (V) of the bottom gate electrode 11a attracts electrons in the semiconductor layer 11c to the bottom gate electrode 11a side, and an n-channel is formed in the semiconductor layer 11a. When an electric current flows through the n channel, the organic EL element 12 emits light, and the light enters the semiconductor layer 11c. As a result, the semiconductor layer 11c is photoexcited to generate carriers (holes and electrons), and these electrons are attracted by +20 (V) of the top gate electrode 11i and trapped in the trap region of the bottom gate insulating film 11h. . This state is a data writing state in the double gate memory transistor 11 and corresponds to a case where the value of display image data img described later is “0”.
[0041]
Further, when the organic EL element 12 emits / does not emit light in the memory state, as shown in FIGS. 4C and 4D, 0 (V) is applied to the top gate electrode 11i and +10 is applied to the bottom gate electrode 11a. (V) is applied and V is applied to the drain electrode 11e. _x Apply (V). The source electrode 11f is connected to the anode of the organic EL element 12, and the cathode of the organic EL element 12 is grounded.
[0042]
Here, when light emission is stored, as shown in FIG. 4C, the semiconductor layer is formed by an electric field generated by holes trapped in the trap region and +10 (V) of the bottom gate electrode 11a. An n channel is formed in 11c. When an electric current flows through this n channel, the organic EL element 12 emits light. In this case, the semiconductor layer 11c is photoexcited by light emission of the organic EL element 12 to generate carriers (holes and electrons). However, since the top gate electrode 11i is 0 (V), substantially any Carriers are not attracted to the top gate electrode 11i side.
[0043]
On the other hand, when non-light emission is stored, as shown in FIG. 4D, the electric field generated by the electrons trapped in the trap region suppresses the electric field of the voltage +10 (V) of the bottom gate electrode 11a. The n channel in the semiconductor layer 11c is pinched off. That is, a continuous n channel is not formed. Thus, no current flows between the source electrode 11f and the drain electrode 11e, that is, no current flows in the organic EL layer 12b of the organic EL element 12, and the organic EL element 12 does not emit light.
[0044]
Returning to FIG. 1, the address driver 2 performs the organic EL display panel 1 in a selection period (described later) at the beginning of one line period (described later) in the subframe in accordance with the control signal Acnt from the controller 5. The address lines AL1 to ALn are sequentially selected to output a voltage of +35 (V), and 0 (V) is output to the unselected address lines AL1 to ALn. Thereafter, the address driver 2 adds +10 (+10) to all the address lines AL1 to ALn of the organic EL display panel 1 in the light emission maintenance period (described later) in accordance with the control signal Acnt from the controller 5. V) is output.
[0045]
In accordance with the control signal Dcnt from the controller 5, the data driver 3 sequentially captures display image data img described later for one line. The display image data img is captured in the line period immediately before the corresponding line.
[0046]
In accordance with the control signal Dcnt from the controller 5, the data driver 3 applies the data lines DL1 to DLm corresponding to the captured display image data img of one line whose value is “1” (indicating light emission) in the selection period. Outputs a voltage of -20 (V). A voltage of +20 (V) is output to the data lines DL1 to DLm corresponding to the display image data img whose value is “0” (indicating non-light emission) during the selection period. The data driver 3 outputs 0 (V) to all the data lines DL1 to DLm in the light emission sustain period.
[0047]
The EL drive voltage generation circuit 4 generates 0, V, in accordance with the control signal Vcnt from the controller 5. ₁ , V ₂ , V ₃ Any voltage of (V) is output to the voltage lines VL <b> 1 to VLn of the organic EL display panel 1. Voltage V ₁ , V ₂ , V ₃ The values of are obtained experimentally according to the characteristics of the organic EL element 12, and are set such that the ratio of the light emitted from the organic EL layer 12b is 1: 2: 4.
[0048]
The controller 5 controls the display image data img corresponding to light emission / non-light emission of each pixel in one subframe period, the control signal Acnt for controlling the address driver 2 and the data driver 3 from the video signal inputted from the outside. And a control signal Vcnt for controlling the EL drive voltage generation circuit 4 are generated. Details of the controller 5 will be described next.
[0049]
FIG. 5 is a block diagram showing the configuration of the controller 5. As shown in the figure, the controller 5 includes an internal clock generation circuit 50, a synchronization separation circuit 51, a control signal generation circuit 52, a decoder 53, an A / D converter 54, a γ (gamma) correction circuit 55, The correction table 56 includes an image data memory 57, an image data buffer 58, and a selector 59.
[0050]
The internal clock generation circuit 50 generates an internal clock signal Ck according to the oscillation pulse of the crystal oscillation pulse device and supplies it to the control signal generation circuit 52.
[0051]
The synchronization separation circuit 51 separates a synchronization signal (horizontal synchronization signal Hsync and vertical synchronization signal Vsync, and a video signal (luminance signal Y and color difference signal C) from an externally input video signal, and generates synchronization signals Hsync and Vsync. The video signal Y / C is supplied to the decoder 53 to the control signal generation circuit 52.
[0052]
The control signal generation circuit 52 controls each part in the controller 5 based on the internal clock signal Ck supplied from the internal clock generation circuit 50 and the synchronization signals Hsync and Vsync supplied from the synchronization separation circuit 51. A control signal Icnt, a control signal Acnt for controlling the address driver 2, a control signal Dcnt for controlling the data driver 3, and a control signal Vcnt for controlling the EL drive voltage generation circuit 4 are generated.
[0053]
The decoder 53 generates analog R (red), G (green), and B (blue) signals from the video signal Y / C including the luminance signal Y and the color difference signal C, and supplies them to the A / D converter 54. To do. The A / D converter 54 performs A / D (analog-to-digital) conversion of analog RGB signals at predetermined timings in accordance with the arrangement of pixels (phases of R, G, and B differ by 120 degrees). Then, a digital R signal, a digital G signal, and a digital B signal each having 3 bits are supplied to the γ correction circuit 55.
[0054]
The γ correction circuit 55 refers to the correction table 56 and performs gamma correction on the digital R signal, digital G signal, and digital B signal supplied from the A / D converter 54 in accordance with the gamma characteristics of the organic EL display panel 1. To do. The correction table 56 associates and stores values before and after gamma correction for each of the digital R signal, digital G signal, and digital B signal.
[0055]
The image data memory 57 stores at least one frame of the digital R signal, digital G signal, and digital B signal (hereinafter collectively referred to as image data IMG) that have been gamma corrected by the γ correction circuit 55.
[0056]
The image data buffer 58 reads out image data IMG of a predetermined pixel from the image data memory 57 according to the control signal Icnt and temporarily stores it. In accordance with the control signal Icnt, the selector 59 selects a bit corresponding to the subframe during the display operation in the image data IMG temporarily stored in the image data buffer 58, and supplies it to the data driver 3 as display image data img. .
[0057]
Note that the image data IMG has eight gradations represented by 3 bits “000” to “111”, and the larger the value, the brighter the gradation. The display image data img corresponds to light emission in the subframe when the value is “1”, and corresponds to non-light emission in the subframe when the value is “0”.
[0058]
The operation of the organic EL display device according to this embodiment will be described below.
A video signal is supplied to the controller 5 from the outside. This video signal is separated into synchronization signals Hsync and Vsync and a video signal Y / C by a synchronization separation circuit 51 and supplied to a control signal generation circuit 52 and a decoder 53, respectively.
[0059]
The control signal generation circuit 52 generates control signals Icnt, Acnt, Dcnt, and Vcnt based on the supplied synchronization signals Hsync and Vsync and the internal clock signal Ck generated by the internal clock generation circuit 50. The output timing of these control signals will be described in detail later.
[0060]
An analog RGB signal is generated by the decoder 53 from the video signal Y / C output from the synchronization separation circuit 51, and further A / D converted by the A / D converter 54, and each of the digital R signals is composed of 4 bits. , A digital G signal and a digital B signal are generated. The digital R signal, digital G signal, and digital B signal are gamma corrected by the γ correction circuit 55 and stored in the image data memory 57 as image data IMG.
[0061]
The image data IMG stored in the image data memory 57 is sequentially stored in the image data buffer 58 in accordance with the control signal Icnt, and any bit corresponding to the subframe is selected by the selector 59 to be controlled as display image data img. The signals are sequentially supplied to the data driver 3 in synchronization with the operation timings of the address driver 2 and the data driver 3 by the signals Acnt and Dcnt.
[0062]
Next, the operations of the address driver 2, the data driver 3 and the EL drive voltage generation circuit 4 controlled by the control signals Acnt, Dcnt and Vcnt, respectively, and the output from the address driver 2, the data driver 3 and the EL drive voltage generation circuit 4 are output. The light emission / non-light emission operation of the organic EL element 12 of each pixel according to the voltage will be described with reference to the timing chart of FIG.
[0063]
When the period of the first subframe (t10 to t1n) is entered, in the period (selection period) of the timing t10 to t10 ′ in the first line periods t10 to t11, the address driver 2 performs the address line AL1 of the first row. Is set to +35 (V), and voltages output to the other address lines AL2 to ALn are set to 0 (V). As a result, a voltage of +35 (V) is applied to the bottom gate electrode 11a of the double-gate memory transistor 11 in the first row, and even if the carriers accumulated in the period of the previous subframe are electrons, there is n in the semiconductor layer 11c. A channel is formed.
[0064]
Further, the EL drive voltage generation circuit 4 supplies the voltage output to the voltage line VL1 of the first row to V ₁ (V) and the voltage output to the other voltage lines VL2 to VLn is 0 (V). Therefore, in the organic EL elements 12 in the second row to the nth row, the top gate insulation is used even during the period of the previous subframe. Even if holes are accumulated in the film 11h, the emission threshold is not exceeded and no light is emitted. As a result, a current flows only through the organic EL layer 12b of the organic EL element 12 in the first row via the n channel formed in the semiconductor layer 11c of the double gate memory transistor 11, and light is emitted.
[0065]
This light is incident on the semiconductor layer 11c of the corresponding double gate memory transistor 11, and carriers (holes and electrons) are generated in the semiconductor layer 11c. The data driver 3 outputs a voltage of −20 (V) to the data line DL corresponding to the display image data value “1” (light emission), and the top gate electrode of the double-gate memory transistor 11 in the first row. Holes are trapped in the trap region by −20 (V) of 11i. On the other hand, the data driver 3 outputs a voltage of +20 (V) to the data line DL corresponding to the value of the display image data “0” (non-light emitting), and the top gate electrode of the double-gate memory transistor 11 in the first row. Electrons are trapped in the trap region by +20 (V) of 11i.
[0066]
On the other hand, in the double gate memory transistors 11 corresponding to the other rows, the corresponding organic EL elements 12 do not emit light, so that the carriers trapped in the trap region are maintained in that state.
[0067]
Next, at the timing t10 ′ to t11 (light emission sustaining period), the data driver 3 outputs 0 (V) to all the data lines DL1 to DLm, and the address driver 2 outputs all the address lines AL1 to AL1. A voltage of +10 (V) is output to ALm. Thereby, the voltage of the bottom gate electrode 11a of all the double gate memory transistors 11 on the organic EL display panel 1 becomes +10 (V), and the voltage of the top gate electrode 11i becomes 0 (V).
[0068]
Thereby, in the organic EL elements 12 in the first row, during the period from the timing t10 ′ to t11, the pixels whose display image data value is “1” continue to emit light at the timing t10 to t10 ′, and the period of the next subframe. The pixels continue to emit light at substantially the same luminance for a certain period until the timing t20, and the pixels whose display image data value is “0” maintain non-emission until the next subframe period. On the other hand, in the second to nth rows, the light emission or the non-light emission is continuously continued according to the display image data rewritten between the timing t31 in the previous subframe and the timing t10 ′ in the current subframe. That is, in the pixel of data “1”, a continuous n channel is maintained in the semiconductor layer 11c of the double gate memory transistor 11 in which holes are trapped in the trap region, and in the pixel of data “0”, electrons are trapped. In the semiconductor layer 11c of the double gate memory transistor 11, the n channel continues to be pinched off.
[0069]
During the period from the timing t10 ′ to t11, the EL drive voltage generation circuit 4 applies the voltage output to the voltage line VL1 of the first row to V ₁ The organic EL element 12 corresponding to the double gate memory transistor 11 in which holes are trapped in the trap region is caused to emit light at a luminance ratio of 1 and corresponds to the double gate memory transistor 11 in which electrons are trapped. The organic EL element 12 is not allowed to emit light.
[0070]
In addition, the EL drive voltage generation circuit 4 outputs the voltage to be output to the voltage lines VL2 to VLn from the second row to the nth row. ₃ (V), and the organic EL element 12 corresponding to the double-gate memory transistor 11 in which holes are trapped in the trap region in the third sub-frame period of the previous frame is changed to a luminance ratio of 4 during the period from the timing t10 ′ to t11. The flash continues on.
[0071]
In the period from timing t11 to t12, which is the next line period, in timing t11 to t11 ′ (selection period), the address driver 2 outputs a voltage of +35 (V) only to the address line AL2 in the second row, and EL The drive voltage generation circuit 4 applies V only to the voltage line VL2 of the second row. ₁ The voltage of (V) is output. Thereby, holes or electrons are trapped in the trap region of the double-gate memory transistor 11 in the second row in accordance with the value of the display image data img, as in the line period of the first row.
[0072]
In the period from the timing t11 ′ to t12 (light emission sustaining period), the address driver 2 and the data driver 3 operate in the same manner as the line period of the first row, and the EL drive voltage generation circuit 4 includes the first and first EL elements. V to two voltage lines VL1 and VL2 ₁ The voltage of (V) is output, and the voltage lines VL3 to VLn of the third to n-th rows are continuously connected to the third subframe period of the previous frame. ₃ The voltage of (V) is output. Thereby, the organic EL elements 12 in the first and second rows in which holes are trapped in the corresponding double gate memory transistors 11 emit light with a luminance ratio of 1, and the organic EL elements 12 in the third to nth rows have luminance. Light is emitted at a ratio of 4.
[0073]
Thereafter, the address driver 2, the data driver 3, and the EL drive voltage generation circuit 4 operate in the same manner in each line period, and the timing t1 (n-1) in the line periods t1 (n-1) to t1n of the nth row. In the selection period of ˜t1 (n−1) ′, holes or electrons are trapped in the trap region of the n-th double gate memory transistor 11 in accordance with the display image data img, and t1 (n−1) ′ to t1n. In the light emission sustain period, all the organic EL elements 12 in which holes are trapped in the trap region of the corresponding double gate memory transistor 11 emit light with a luminance ratio of 1.
[0074]
In this way, in the k-th row, the pixel of the display image data value “1” at the time of selection is t1 (k−1) until the k-th row is selected in the next second subframe. Light emission with a luminance ratio of 1 is continued intermittently during the period of “˜t1k, t1k” ˜t1 (k + 1),..., T2 (k-2) ′-t2 (k−1). Therefore, when any row of the organic EL elements 12 is trapped in the trap region of the corresponding double gate memory transistor 11, the period of light emission with the luminance ratio of 1 is the same.
[0075]
Next, the operation in the second subframe period (t20 to t2n) is substantially the same as that in the first subframe period, but light emission at timings t20 ′ to t21 in the line period (t20 to t21) of the first row. In the sustain period, the EL drive voltage generation circuit 4 applies V to the voltage line VL1 in the first row. ₂ The voltage of (V) is output and V is applied to the voltage lines VL2 to VLn of the second to nth rows. ₁ The voltage of (V) is output. Accordingly, all the organic EL elements 12 in which holes are trapped in the trap region of the corresponding double gate memory transistor 11 have a luminance ratio of 2 in the first row and luminance in the 2nd to nth rows. Light is emitted at a ratio of 1.
[0076]
In the light emission sustaining period from the timing t21 ′ to t22 in the line period (t21 to t22) of the second row, the EL drive voltage generation circuit 4 applies V to the voltage lines VL1 and VL2 of the first and second rows. ₂ The voltage of (V) is output and V is applied to the voltage lines VL3 to VLn of the third to nth rows. ₁ The voltage of (V) is output. Similarly, in the light emission sustaining period from the timing t2 (n−1) ′ to t2n in the line period (t2 (n−1) to t2n) of the nth row, the EL drive voltage generation circuit 4 operates for all voltage lines. V to VL1 to VLn ₂ The voltage of (V) is output.
[0077]
In this way, in the k-th row, the pixel of the display image data value “1” at the time of selection is t2 (k−1) until the k-th row is selected in the next third subframe. ) ′ To t2k, t2k ′ to t2 (k + 1),..., T3 (k−2) ′ to t3 (k−1), and continuously emits light with a luminance ratio of 2. Therefore, when any row of the organic EL elements 12 is trapped in the trap region of the corresponding double gate memory transistor 11, the period of light emission with the luminance ratio of 2 is the same.
[0078]
Next, the operation in the third subframe period (t30 to t3n) is substantially the same as that in the first subframe period, but light emission at timings t30 ′ to t31 in the line period (t30 to t31) of the first row. In the sustain period, the EL drive voltage generation circuit 4 applies V to the voltage line VL1 in the first row. ₃ The voltage of (V) is output and V is applied to the voltage lines VL2 to VLn of the second to nth rows. ₂ The voltage of (V) is output. Accordingly, all the organic EL elements 12 in which holes are trapped in the trap region of the corresponding double gate memory transistor 11 have a luminance ratio of 4 in the first row and luminance in the second to nth rows. Light is emitted at a ratio of 2.
[0079]
In the light emission sustaining period from the timing t31 ′ to t32 in the line period (t31 to t32) of the second row, the EL drive voltage generation circuit 4 applies V to the voltage lines VL1 and VL2 of the first and second rows. ₃ The voltage of (V) is output and V is applied to the voltage lines VL3 to VLn of the third to nth rows. ₂ The voltage of (V) is output. Similarly, in the light emission sustain period of timings t3 (n−1) ′ to t3n in the line period (t3 (n−1) to t3n) of the nth row, the EL drive voltage generation circuit 4 operates for all voltage lines. V to VL1-VLn ₃ The voltage of (V) is output.
[0080]
As described above, when any row of the organic EL elements 12 is trapped in the trap region of the corresponding double gate memory transistor 11, the period of light emission at the luminance ratio 2 is the same. In the k-th row, the pixel of the value “1” of the display image data value at the time of selection is t3 (k−1) ′ to t3k until the k-th row is selected in the next first subframe. , T3k ′ to t3 (k + 1),..., T1 (k−2) ′ to t1 (k−1), so that the light emission of the luminance ratio 4 is intermittently continued. When trapped in the trap region of the corresponding double gate memory transistor 11, the light emission period with the luminance ratio of 4 is the same.
[0081]
By the operation as described above, the organic EL element 12 for each pixel that emits light or does not emit light in each sub-frame is visually synthesized in one frame and emits light with brightness corresponding to the image data IMG. Then, a color image is displayed on the organic EL display panel 1 by visual color mixing based on the arrangement of R, G, and B of the color filter 13 shown in FIG.
[0082]
Hereinafter, the operation of the organic EL display device according to this embodiment will be described in detail with a specific example. Here, for simplicity of explanation, the organic EL display panel 1 is assumed to be composed of 2 × 2 pixels as shown in FIG. 7, the upper left pixel is the pixel (1, 1), and the upper right pixel is The pixel is called pixel (1, 2), the lower left pixel is called pixel (2, 1), and the lower right pixel is called pixel (2, 2).
[0083]
The image data IMG corresponding to the pixels (1, 1), (1, 2), (2, 1), (2, 2) in the frame described here is 1, 3, 5, 7 (3 bits), respectively. And “001”, “011”, “101”, “111”). Also, in the figure, each pixel with a cross indicates that it is an operation other than data relating to this frame. The shaded pixels indicate that they are not selected in the selection period.
[0084]
First, as shown in FIG. 7A, in the selection period t10 to t10 ′ of the first subframe and the first line period, the traps of the double gate memory transistors 11 of the pixels (1,1) and (1,2). Holes or carriers are trapped in the region (hereinafter, in this example, trapping carriers is referred to as a memory operation). Here, since all the display image data img is “1”, light emission that is a hole trap is stored (represented by □ in the figure). Then, as shown in FIG. 7B, the pixels (1, 1) and (1, 2) in which the light emission is stored are caused to emit light at a luminance ratio of 1 during the light emission sustain period t10 ′ to t11.
[0085]
Next, as shown in FIG. 7C, in the selection periods t11 to t11 ′ of the first subframe and the second line period, the double gate memory transistors 11 of the pixels (2, 1) and (2, 2) are transferred. Perform the memory operation. Here, since all the display image data img is “1”, the light emission is stored. Next, as shown in FIG. 7D, in the light emission maintenance period t11 ′ to t12, the pixels (1,1), (1,2), (2,1), (2, 2) is emitted with a luminance ratio of 1.
[0086]
Next, as shown in FIG. 7E, in the selection period t20 to t20 ′ of the second subframe and the first line period, to the double gate memory transistor 11 of the pixels (1,1) and (1,2). Perform the memory operation. Here, since the display image data img is “0” for the pixel (1, 1) and “1” for the pixel (1, 2), the pixel (1, 1) emits light and the pixel (1, 2). ) Stores no light emission (represented by a black square in the figure). Next, as shown in FIG. 7F, in the light emission maintenance period t20 ′ to t21, the pixel (1,2) in which the light emission has been stored so far has the luminance of 2, and the pixel (2,1), ( 2 and 2) are emitted with a luminance ratio of 1.
[0087]
Next, as shown in FIG. 7G, in the selection period t21 to t21 ′ of the second subframe and the second line period, to the double gate memory transistor 11 of the pixels (2, 1) and (2, 2). Perform the memory operation. Here, since the display image data img is “0” for the pixel (1, 1) and “1” for the pixel (1, 2), the pixel (1, 1) emits light and the pixel (1, 2). ) Stores non-light emission. Next, as shown in FIG. 7 (h), in the light emission sustaining period t21 'to t22, the pixels (1, 2) and (2, 2) in which the light emission has been stored so far are caused to emit light at a luminance ratio of 2. It is done.
[0088]
Next, as shown in FIG. 7I, in the selection period t30 to t30 ′ of the third subframe and the first line period, the double gate memory transistor 11 of the pixels (1,1) and (1,2) is transferred. Perform the memory operation. Here, since the display image data img is both “0”, non-light emission is stored in the pixels (1, 1) and (1, 2). Next, as shown in FIG. 7 (j), in the light emission sustaining period t30 ′ to t31, the pixel (2, 2) in which the light emission has been stored so far is caused to emit light at a luminance ratio of 2.
[0089]
Next, as shown in FIG. 7 (k), in the selection period t31 to t31 ′ of the second subframe and the second line period, to the double gate memory transistor 11 of the pixels (2, 1) and (2, 2). Perform the memory operation. Here, since the display image data img is “1”, the light emission is stored in the pixels (1, 1) and (1, 2). Next, as shown in FIG. 7 (l), the pixels (2, 1) and (2, 2) in which light emission has been stored so far are caused to emit light at a luminance ratio of 4 during the light emission sustain period t31 ′ to t32. It is done.
[0090]
Further, the process proceeds to the first subframe and the first line period of the next frame period. In order to equalize the light emission period, the display image of the third subframe is used for the pixels (2, 1) and (2, 2). Light emission is performed using data img. That is, as shown in FIG. 7 (m), display image data corresponding to the next frame is stored in the pixels (1, 1) and (1, 2) in the selection period t10 to t10 ′, As shown in n), in the light emission maintenance period t10 ′ to t11, the pixels (2, 1) and (2, 2) in which the light emission has been stored so far are emitted with a luminance ratio of 4.
[0091]
The luminance ratio and the number of times of each of the pixels (1, 1), (1, 2), (2, 1), (2, 2) in the above one frame period are added and visually combined in one frame. The brightness of each pixel is obtained. Then, as shown in FIG. 7 (o), the pixels (1, 1), (1, 2), (2, 1), and (2, 2) respectively become 2, 6, 10, and 14, and the image data The ratios of IMG 1, 3, 5, and 7 are equal.
[0092]
As described above, in the organic EL display panel 1 according to this embodiment, only the double gate memory transistor 11 is formed in addition to the organic EL element 12 in each pixel. For this reason, it is possible to increase the relative area ratio of the organic EL elements 12 in one pixel region, and the pixel aperture ratio increases. Moreover, since the element provided in addition to the organic EL element 12 may be only the double gate memory transistor 11, the possibility that any element in the manufactured organic EL display panel 1 is defective is reduced. The yield can be increased.
[0093]
Moreover, what should be made to light-emit by the organic EL element 12 of each pixel can be made to light-emit in the whole 1 sub-frame period except for the selection period which is first in one line period. For this reason, even if the organic EL element 12 does not emit light for a short time with high brightness at which the light emission efficiency deteriorates, sufficient display brightness can be obtained, and power consumption can be kept low.
[0094]
Further, in the organic EL display device according to this embodiment, one frame image is represented by a plurality of subframe images each represented by a binary image, and the images of each subframe are sequentially displayed. For this reason, the light emitted by each organic EL element 12 is visually synthesized and can represent gradation according to light emission / non-light emission for each subframe. Moreover, since the light emitted from the organic EL element 12 is diagonally arranged and is transmitted through the color filter 13 that transmits light in the respective wavelength regions of red, green, and blue, the display image of the organic EL display panel 1 is displayed. A full color image can be obtained.
[0095]
The present invention is not limited to the above-described embodiment, and various modifications and applications are possible. Hereinafter, modifications of the above-described embodiment applicable to the present invention will be described in detail.
[0096]
In the above embodiment, the organic EL display panel 1 is driven in a subframe to display an 8-gradation image. However, the present invention can also display a binary image on the organic EL display panel 1. In this case, it is not necessary to finely control the value of the voltage output to the voltage lines VL1 to VLn, and the voltage supplied to all of the voltage lines VL1 to VLn may be set to the constant voltage Vdd as shown in FIG.
[0097]
When the binary image is displayed on the organic EL display panel 1 in this way, the controller 5 compares the display image signal img supplied to the data driver 3 with respect to whether or not the luminance signal Y is larger than a predetermined threshold value. Then, it can be generated based on the comparison result, or can be generated using an error diffusion method or the like.
[0098]
In the above embodiment, the anode electrode 12 a of the organic EL element 12 is connected to the source electrode 11 f of the double gate memory transistor 11 in each pixel of the organic EL display panel 1. On the other hand, the anode electrode of the organic EL element 12 may be grounded, and the cathode electrode 12 c may be connected to the drain electrode 11 e of the double gate memory transistor 11. In this case, the voltage output from the EL drive voltage generation circuit 4 may be set to 0 (V) or a negative value.
[0099]
In the embodiment described above, one frame is divided into three subframes with a display luminance ratio of 1: 2: 4, and each gray level display is obtained by selecting each subframe. However, in the present invention, an image having an arbitrary number of gradations of three or more gradations can be displayed by subframe driving. For example, when displaying an image of 2n gradations, one frame is divided into n subframes, and the display luminance ratio in each subframe is 1: 2: 4:...: 2 ^n-1 (N is an integer of 1 or more). At this time, whether or not each pixel selectively emits light in each subframe may be determined based on the gradation value of the pixel displayed in binary as in the above embodiment.
[0100]
In the above embodiment, the controller 5 controls the subframe period so that the display luminance of the pixels emitting light in order from the first subframe increases in one frame. However, in the present invention, the order of the sub-frames in one frame can be arbitrarily set, for example, the order in which the display luminance of the light emitting pixels is large.
[0101]
In the above embodiment, one frame is divided into three subframes, and the images of the subframes are displayed by visually synthesizing the images of the subframes. However, when such sub-frame driving is performed, the data driver 3 must be operated at a considerably high frequency. Therefore, in the present invention, the organic EL display device may be driven by thinning out image data, for example, by setting an image of 30 frames per second to be substantially 15 frames.
[0102]
In the above embodiment, a color filter that transmits light in the red wavelength region of white light emitted from the organic EL layer 12b, a color filter that transmits light in the green wavelength region, and a blue wavelength region. The color filters that transmit light are arranged in a diagonal array as shown in FIG. 3 to display a full color image. However, the color filters may be arranged in other arrangements such as a delta arrangement, a stripe arrangement, or a square arrangement.
[0103]
Moreover, it is good also as an organic electroluminescence display which displays a monochrome gradation image, without using such a color filter. In addition, as a material constituting the organic EL layer 12b without using such a color filter, a material that emits light in the red wavelength region, a material that emits light in the green wavelength region, and light in the blue wavelength region are used. An organic EL display device that displays a full-color image can also be created by selecting the ones that emit and arranging them in the same order as in FIG. 3, for example. Further, the material of the organic EL layer 12b emits light in any one of the red, green, and blue wavelength ranges, and a light conversion layer that converts the wavelength of light and emits it may be used instead of the color filter. Good.
[0104]
In this case, the organic EL layer 12b that emits light in the red wavelength region is formed of an electron transport layer composed of α-NPD and Alq3 in which DCM-1 is dispersed in the direction from the anode electrode 12a to the cathode electrode 12c. A transporting light-emitting layer can be laminated. The organic EL layer 12b that emits light in the green wavelength range is configured by laminating a hole transport layer composed of α-NPD and an electron transport light-emitting layer composed of Bebq2 in the direction from the anode electrode 12a to the cathode electrode 12c. can do. The organic EL layer 12b that emits light in the blue wavelength range is a light emission composed of α-NPD hole transport layer, 96 wt% DPVBi, and 4 wt% BCzVBi in the direction from the anode electrode 12a to the cathode electrode 12c. A layer and an electron transport layer made of Alq3 can be stacked.
[0105]
In the above embodiment, the organic EL element 12 in which the organic semiconductor as described above is applied to the light emitting layer is applied as the light emitting element. However, the present invention is a display using another type of self-luminous light emitting element such as an inorganic EL element that emits light by applying a voltage higher than a predetermined value between its electrodes, even if it is not an organic EL element. It can be applied to the device.
[0106]
【The invention's effect】
As described above, since the number of elements provided in each pixel can be reduced, it is possible to provide a self-luminous display element, a display device, and the like that have a high pixel aperture ratio and a high manufacturing yield. Become.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of an organic EL display device according to an embodiment of the present invention.
2A and 2B are diagrams showing a structure of the organic EL display panel of FIG. 1, in which FIG. 2A is a plan view and FIG. 2B is a cross-sectional view taken along line AA of FIG.
3 is a diagram illustrating an arrangement of color filters in FIG. 2. FIG.
4 is a diagram for explaining the operation principle of the double gate memory of FIGS. 1 and 2; FIG.
FIG. 5 is a block diagram showing a configuration of the controller of FIG. 1;
FIG. 6 is a timing chart showing the operation of the organic EL display device according to the embodiment of the present invention.
FIG. 7 is an explanatory diagram of an operation of the organic EL display device according to the embodiment of the present invention.
FIG. 8 is a block diagram showing a configuration of an organic EL display device according to a modification of the embodiment of the present invention.
FIG. 9 is an equivalent circuit diagram for one pixel of a conventional organic EL display element.
10 is a diagram showing a structure of the organic EL display element of FIG.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Organic EL display panel, 2 ... Address driver, 3 ... Data driver, 4 ... EL drive voltage generation circuit, 5 ... Controller, 10 ... Substrate, 11 ... Double Gate memory transistor, 11a ... bottom gate electrode, 11b ... bottom gate insulating film, 11c ... semiconductor layer, 11d ... n + Si layer, 11e ... drain electrode, 11f ... source electrode, 11g ... light blocking layer, 11h ... top gate insulating film, 11i ... top gate electrode, 11j ... insulating protective film, 12 ... organic EL element, 12a ... anode electrode, 12b organic EL Layer 12c... Cathode electrode 13 color filter 50 internal clock generation circuit 51 synchronization separation circuit 52 control signal generation circuit 53 .. Decoder, 54... A / D converter, 55... Gamma (γ) correction circuit, 56... Correction table, 57. ..Selector, AL, AL1 to ALn ... Address line, DL, DL1 to DLm ... Data line, VL, VL1 to VLn ... Voltage line

Claims (9)

A display element in which a plurality of pixels are arranged vertically and horizontally in a predetermined arrangement,
Each of the plurality of pixels is
A lower gate electrode; a lower gate insulating film formed on the lower gate electrode; a semiconductor layer that is excited by incident light to generate carriers therein; and a drain electrode and a source connected to the semiconductor layer, respectively An upper gate insulating film formed on the semiconductor layer, the drain electrode and the source electrode, and a trap region for trapping carriers generated in the semiconductor layer at an interface with the semiconductor layer; A memory formed on the upper gate insulating film at a position corresponding to the semiconductor layer and traps carriers in the semiconductor layer in a trap region of the upper gate insulating film according to a supplied voltage. Elements,
A light emitting element that is connected to a drain electrode or a source electrode of the memory element and emits light by a current flowing through a channel formed in the semiconductor layer when a voltage corresponding to data reading is supplied to the lower gate electrode;
A display element comprising: The voltage supplied to the lower gate electrode at the time of erasing or writing data is to form a channel in the semiconductor layer,
2. The display element according to claim 1, wherein one of holes or electrons among carriers trapped in the upper gate insulating film pinches off a channel in the semiconductor layer when reading data. 3. The type of carriers trapped in the trap region is made different by making the voltage supplied to the upper gate electrode different when erasing and writing data. The display element as described in. The display element according to claim 1, wherein the light emitting element is an organic electroluminescence element. 5. The memory device according to claim 1, further comprising a light blocking unit that allows only light emitted from a light emitting device of the same pixel to enter and blocks light emitted from a light emitting device of an adjacent pixel. The display element according to any one of the above. The light emitting element emits light including all of light in a red wavelength range, light in a green wavelength range, and light in a blue wavelength range,
Each of the plurality of pixels includes a red color filter that transmits light in a red wavelength region of light emitted from the light emitting element and emits the light to the outside, and a green wavelength region of light emitted from the light emitting element. A green color filter that transmits the light of the light and emits the light to the outside, and a blue color filter that transmits the blue light of the light emitted from the light emitting element and emits the light to the outside.
The red color filter, the green color filter, or the blue color filter is disposed in each of the plurality of pixels in a predetermined order according to the arrangement of the pixels.
The display element according to claim 1, wherein the display element is a display element. Each light emitting element of the plurality of pixels emits one of light in a red wavelength range, light in a green wavelength range, and light in a blue wavelength range,
The light emitting element that emits light in the red wavelength range, the light emitting element that emits light in the green wavelength range, or the light emitting element that emits light in the blue wavelength range are arranged in a predetermined order according to the arrangement of the pixels. The display element according to claim 1, wherein the display element is disposed in each of the pixels. A driving method of a display element in which pixels are arranged in a matrix,
Each pixel of the display element is
A lower gate electrode; a lower gate insulating film formed on the lower gate electrode; a semiconductor layer that is excited by incident light to generate carriers therein; and a drain electrode and a source connected to the semiconductor layer, respectively An upper gate insulating film formed on the semiconductor layer, the drain electrode and the source electrode, and a trap region for trapping carriers generated in the semiconductor layer at an interface with the semiconductor layer; A memory formed on the upper gate insulating film at a position corresponding to the semiconductor layer and traps carriers in the semiconductor layer in a trap region of the upper gate insulating film according to a supplied voltage. Elements,
A light emitting element that is connected to a drain electrode or a source electrode of the memory element and emits light by current flowing through a channel formed in the semiconductor layer when a voltage corresponding to data reading is supplied to the lower gate electrode; Prepared,
The driving method is:
A selection step of selecting a plurality of pixels in a matrix for each row and sequentially supplying a predetermined voltage corresponding to erasing and writing of data to the lower gate electrode;
A voltage corresponding to data erasure or writing is supplied to the upper gate electrode of the memory element of the pixel in the row selected by the selection step, and either a hole or an electron in the carrier is trapped in the trap region. A memory step for storing data, and
After the selection in the selection step, a voltage corresponding to data read is applied to the lower gate electrode and the upper gate electrode of all the memory elements of the plurality of pixels until the selection in the next selection step. A light emitting step of supplying and supplying a predetermined voltage to the drain electrode or the source electrode to cause the corresponding light emitting element to emit light according to a state stored in each memory element; and
A method for driving a display element, comprising: A lower gate electrode; a lower gate insulating film formed on the lower gate electrode; a semiconductor layer that is excited by incident light to generate carriers therein; and a drain electrode and a source connected to the semiconductor layer, respectively An upper gate insulating film formed on the semiconductor layer, the drain electrode and the source electrode, and a trap region for trapping carriers generated in the semiconductor layer at an interface with the semiconductor layer; A memory formed on the upper gate insulating film at a position corresponding to the semiconductor layer and traps carriers in the semiconductor layer in a trap region of the upper gate insulating film according to a supplied voltage. Connected to the drain electrode or the source electrode of the memory element and the lower gate electrode. When the voltage corresponding to the out is supplied, and a display device and a light emitting element which emits light by a current flowing through the channel formed in the semiconductor layer, each of a plurality of pixels arranged in a matrix,
Selecting means for selecting the memory element corresponding to any row of pixels and sequentially supplying a voltage corresponding to erasing and writing of data to the lower gate electrode;
When a voltage corresponding to erasing and writing of data is supplied from the selection means to the lower gate electrode, a voltage corresponding to erasing or writing of data is supplied to the upper gate electrode of the corresponding memory element to Memory means for storing
All selection means for supplying a voltage corresponding to data reading to the lower gate electrodes of the memory elements of all pixels;
When a voltage corresponding to data reading is supplied to the lower gate electrode by the all selection means, a predetermined voltage is supplied to the drain electrode or the source electrode to form the semiconductor layer. A light emitting means for causing a current to flow through the channel to the corresponding light emitting element;
Control means for controlling the selection means, the memory means, the full selection means and the light emitting means,
A display device comprising:

Images