[go: up one dir, main page]

JP4108909B2 - Semiconductor device - Google Patents

Semiconductor device Download PDF

Info

Publication number
JP4108909B2
JP4108909B2 JP2000255337A JP2000255337A JP4108909B2 JP 4108909 B2 JP4108909 B2 JP 4108909B2 JP 2000255337 A JP2000255337 A JP 2000255337A JP 2000255337 A JP2000255337 A JP 2000255337A JP 4108909 B2 JP4108909 B2 JP 4108909B2
Authority
JP
Japan
Prior art keywords
resin package
semiconductor device
power semiconductor
resin
sealed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2000255337A
Other languages
Japanese (ja)
Other versions
JP2002076258A (en
Inventor
宗良 河口
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP2000255337A priority Critical patent/JP4108909B2/en
Publication of JP2002076258A publication Critical patent/JP2002076258A/en
Application granted granted Critical
Publication of JP4108909B2 publication Critical patent/JP4108909B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H01L2224/48139—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate with an intermediate bond, e.g. continuous wire daisy chain
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/49105—Connecting at different heights
    • H01L2224/49109—Connecting at different heights outside the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires

Landscapes

  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Description

【０００１】
【発明の属する技術分野】
この発明は、パワー半導体モジュール等の半導体装置に関する。
【０００２】
【従来の技術】
図５は、従来のパワー半導体モジュールの概略構成を示す説明図であり、図５における(a)，(b)及び(c)は、それぞれ平面図、縦断面図及び裏面図を示している。このパワー半導体モジュールでは、収納空間２４において、パワー半導体素子である複数のシリコンチップ３が絶縁セラミック基板１１（基板本体１１ａとその表裏面に銅等で形成された回路パターン１１ｂとの３層構造）の表主面の回路パターン１１ｂ上に半田１８によって半田付けされて、樹脂製のケース２内に収納されている。ケース２には、外部接続端子１がインサートされ、ケース底部にはヒートシンクとして機能する銅ベース板１７が配置されており、その銅ベース板１７の上に絶縁セラミック基板１１の裏主面の回路パターン１１ｂが半田１８によって半田付けされ、各シリコンチップ３と外部接続端子１とがワイヤ１３で接続されている。そして、収納空間２４にシリコンゲル２３が充填され、さらにその上部がエポキシ樹脂１４で封止され、収納空間２４の上部が蓋体２５で閉じられる。なお、３１はパワー半導体素モジュール自体の取り付け穴である。
【０００３】
【発明が解決しようとする課題】
しかし、上記のパワー半導体モジュールのように、絶縁セラミック基板１１上に複数のシリコンチップ３を半田付けする構成では、それらシリコンチップ３のうち一つだけが不良となった場合でも、モジュール全体を不良品としなければならず、多くの正常なシリコンチップ３を無駄にしてしまうという問題点があった。
【０００４】
また、多くのシリコンチップ３を一つの絶縁セラミック基板１１上に搭載すると、絶縁セラミック基板１１のサイズが大きくなり、基板割れ、半田ボイド不良の発生が高くなるという問題点もあった。
【０００５】
この発明は上記問題点を解決するためになされたもので、一部のパワー半導体素子が不良となっても、そのパワー半導体素子を含む必要最小限の取り替え作業だけで良品とすることができる半導体装置を得ることを目的とする。
【０００６】
【課題を解決するための手段】
この発明に係る請求項１記載の本願発明は、外部接続端子が設けられたケース内に複数のパワー半導体素子を収納してなる半導体装置であって、前記複数のパワー半導体素子のうち、少なくとも一部のパワー半導体素子それぞれを専用の樹脂パッケージで封止し、前記樹脂パッケージから露出した端子を前記ケース内で前記外部接続端子に接続し、前記ケース内における前記樹脂パッケージから露出した端子と前記外部接続端子との接続をねじ止めによって行っている。
【０００７】
また、請求項２の発明は、請求項１記載の半導体装置であって、前記複数のパワー半導体素子すべてを２以上の前記樹脂パッケージに分けて封止している。
【０００８】
また、請求項３の発明は、請求項１記載の半導体装置であって、前記複数のパワー半導体素子は、前記樹脂パッケージで封止されずに所定の基板の表面上に実装されたパワー半導体素子を含み、ヒートシンクを前記所定の基板の裏面に当接させている。
【０００９】
また、請求項４の発明は、請求項３記載の半導体装置であって、前記ヒートシンクは前記樹脂パッケージにさらに当接される。
【００１１】
【発明の実施の形態】
以下、この発明をその実施の形態を示す図面に基づいて具体的に説明する。なお、図５に示す従来例と同一または同等の部材には一部同一符号を付している。
【００１２】
＜実施の形態１＞
図１は、この発明の実施の形態１である半導体装置の概略の構成を示す説明図であり、図１の(a)，(b)及び(c)は、それぞれ一部破断した平面図、縦断面図及び裏面図を示している。実施の形態１の半導体装置は、外部接続端子１をインサートした樹脂製のケース２内に、パワー半導体素子である複数のシリコンチップを収納して構成されるパワー半導体モジュールである。
【００１３】
図２は樹脂パッケージの概略の構成を示す説明図であり、図２の(a)，(b)及び(c)は、それぞれ一部破断した平面図、縦断面図及び裏面図を示している。各シリコンチップ３は、図２に示すように、２つのディスクリートタイプの樹脂パッケージ４に分けて封止される。
【００１４】
すなわち、一つまたは複数のシリコンチップ３が、絶縁セラミック基板１１（基板本体１１ａとその表裏面に銅等で形成された回路パターン１１ｂとの３層構造）の表主面上に形成された回路パターン１１ｂに半田１８による半田付けにより実装され、その絶縁セラミック基板１１の裏主面がヒートシンクである銅ベース板１２に半田１８によって半田付けされる。さらに、絶縁セラミック基板１１の主表面上の回路パターン１１ｂに端子５が半田１８によって半田付けされ、各シリコンチップ３と端子５とがワイヤ１３及び回路パターン１１ｂによって電気的に接続された後で、シリコンチップ３を搭載した絶縁セラミック基板１１及び端子５を含む銅ベース板１２上の主要部がエポキシ樹脂１４によって封止され、樹脂パッケージ４とされる。
【００１５】
このようにして、複数のシリコンチップ３が、ここでは２つの樹脂パッケージ４に分けて封止され、図１に示すように、各樹脂パッケージ４から露出した端子５は、対応する外部接続端子１にねじ６により接続される。また、各樹脂パッケージ４は、ケース２の底部にねじ７により固定されている。さらに、ケース２の底部の樹脂パッケージ４が配置される部分には、放熱用窓８が開口させてあり、ケース２の上部開口９は蓋体１０によって閉じられる。なお、３１は実施の形態１の半導体装置自体の取り付け穴である。
【００１６】
このような構成としたパワー半導体モジュールでは、一方の樹脂パッケージ４に封止されているシリコンチップ３に不良があった場合、該当する樹脂パッケージ４を同一機能の新たな樹脂パッケージ４と取り替えることにより良品とすることができるので、製品の不良率を大幅に低減できる。また、もう一方の樹脂パッケージ４やケース２を無駄にすることなく、そのまま使用することができる。
【００１７】
このように、実施の形態１の半導体装置は、樹脂パッケージ４単位の取り替え作業という、必要最小限の取り替え作業によって良品とすることができる。
【００１８】
また、樹脂パッケージ４から露出するシリコンチップ３用の端子５と外部接続端子１とはねじ６で接続され、樹脂パッケージ４そのものも、例えばその銅ベース板１２のねじ孔１５などを利用してねじ７でケース２に固定されているので、前記取替え作業を汎用工具を用いて簡単かつ迅速に行うことができる。さらに、樹脂パッケージ４を種類の異なる別の樹脂パッケージ４と交換することもできるので、ケース２をそのまま利用して特性の異なるパワー半導体モジュールを容易に作製することができる。
【００１９】
加えて、複数のシリコンチップ３が２つの樹脂パッケージ４に分けて封止されるため、複数のシリコンチップ３を１つの絶縁セラミック基板１１上に搭載する従来構造に比べ、絶縁セラミック基板１１のサイズを小さくすることができるため、基板割れ、半田ボイド不良の発生の低減化を図ることができる。
【００２０】
＜実施の形態２＞
図３はこの発明の実施の形態２である半導体装置の概略の構成を示す説明図であり、図３の(a)，(b)及び(c)は、それぞれ一部破断した平面図、縦断面図及び裏面図を示している。実施の形態２の半導体装置も、外部接続端子１をインサートした樹脂製のケース２内に、パワー半導体素子である複数のシリコンチップを収納して構成されるパワー半導体モジュールである。
【００２１】
このパワー半導体モジュールでは、外部接続端子１をインサートした樹脂製のケース２内を２つの収納空間２１，２２に区分して、一方の収納空間２１には、実施の形態１で示した一つの樹脂パッケージ４を収納し、他方の収納空間２２には、樹脂パッケージ４で封止しない複数のシリコンチップ３を収納している。なお、樹脂パッケージ４で封止しないシリコンチップ３には、樹脂パッケージ４で封止するシリコンチップ３よりも発熱量が大きいものが含まれる。
【００２２】
収納空間２１内への樹脂パッケージ４の収納構造は、図１及び図２で示した実施の形態１の場合と同様であり、ここではその説明を省略する。収納空間２２へのシリコンチップ３の収納は、図５で示した従来例の場合と同様である。すなわち、複数のシリコンチップ３は、絶縁セラミック基板１１の表主面上に形成された回路パターン１１ｂに半田１８による半田付けにより実装され、その絶縁セラミック基板１１が収納空間２２内に収納されている。収納空間２２の底部にはヒートシンクである銅ベース板１９が設置され、絶縁セラミック基板１１の裏主面が半田１８による半田付けにより銅ベース板１９に当接させてある。
【００２３】
また、絶縁セラミック基板１１上のシリコンチップ３，３間や、シリコンチップ３と対応する外部接続端子１との間や、絶縁セラミック基板１１上の回路パターン１１ｂと対応する外部接続端子１との間がワイヤ１３で接続される。このように、絶縁セラミック基板１１を収納空間２２に収納した後に、その収納空間２２にはシリコンゲル２３が充填され、さらにその上部がエポキシ樹脂１４で封止され、最後にその収納空間２２の上部開口２９が蓋体３０で閉じられる。なお、図３の(a)では、収納空間２２内にシリコンゲル２３やエポキシ樹脂１４を充填しない状態を示している。
【００２４】
このパワー半導体モジュールでも、樹脂パッケージ４で封止したシリコンチップ３に不良があった場合には、その樹脂パッケージ４を取り替えることができるので、製品の不良率を低減できる。
【００２５】
また、このパワー半導体モジュールでは、樹脂パッケージ４で封止されず、樹脂パッケージ４に含まれるシリコンチップ３よりも発熱量の大きいシリコンチップ３を搭載した絶縁セラミック基板１１の裏主面を、半田１８による半田付けにより収納空間２２の底部に設置されたヒートシンクである銅ベース板１９の表面に当接させて接続している。
【００２６】
したがって、実施の形態２の半導体装置では、樹脂パッケージ４で封止されたシリコンチップ３と樹脂封止されずに絶縁セラミック基板１１上に実装されたシリコンチップ３とをケース２の収納空間２１，２２内にそれぞれ混在させることにより、設計自由度の向上を図ることができる。
【００２７】
また、樹脂封止されずに絶縁セラミック基板１１上に実装されたシリコンチップ３からの発熱は、銅ベース板１９を介した放熱作用によって効率良く放熱することができる。図３の(c)に示すように、銅ベース板１９の表面積は、樹脂パッケージ４の銅ベース板１２の表面積に比べて十分広く形成されているため、発熱量の大きい収納空間２２内のシリコンチップ３からの発熱を銅ベース板１９によって効率良く放熱できる。
【００２８】
＜実施の形態３＞
図４はこの発明の実施の形態３でよる半導体装置の概略の構成を示す説明図であり、図４の(a)，(b)及び(c)は、それぞれ一部破断した平面図、縦断面図及び裏面図を示している。実施の形態３の半導体装置も、外部接続端子１をインサートした樹脂製のケース２内に、パワー半導体素子である複数のシリコンチップ３を収納して構成されるパワー半導体モジュールである。
【００２９】
このパワー半導体モジュールでは、実施の形態２のパワー半導体モジュールにおいて、収納空間２１に収納される樹脂パッケージ４と、収納空間２２に収納されるシリコンチップ３とに共通のヒートシンクである共通銅ベース板１６を、ケース２の底部の全域にわたって設置している。
【００３０】
すなわち、シリコンチップ３を搭載した収納空間２２内の絶縁セラミック基板１１の裏主面を、共通銅ベース板１６の表面に半田１８による半田付けにより当接させて接続すると共に、収納空間２１内の樹脂パッケージ４も同じ共通銅ベース板１６の表面に当接させ、ねじ２７を用いたねじ止めにより接続している。その他の構成は、実施の形態２の場合と同様である。
【００３１】
図４の(c)に示すように、共通銅ベース板１６の表面積はケース２の底面積に相当する十分広い形成面積を有しており、放熱作用が格段に優れているため、収納空間２１及び収納空間２２のいずれのシリコンチップ３からの発熱も効率良く放熱できる。
【００３２】
また、ヒートシンクである共通銅ベース板１６が収納空間２１の樹脂パッケージ４と収納空間２２の絶縁セラミック基板１１との間で共通化されるので、組立が簡単になる。
【００３３】
＜その他＞
なお、前記各実施の形態では、樹脂パッケージ４から露出した端子５と外部接続端子１との接続をねじ止めにより行う場合を示したが、これに限らず、リード線や半田付けにより接続しても良い。また、樹脂パッケージ４も、前記各実施の形態の場合のように、ケース２にねじ７で固定する場合に限らず、その他の態様によって、ケース２内に安定良く収納するようにしても良い。
【００３４】
前記各実施の形態は、複数のシリコンチップ３のうち一部のシリコンチップ３が当該一部のシリコンチップ３に専用の樹脂パッケージ４で封止された例を示しており、実施の形態１では複数のシリコンチップ３のすべてが２つの樹脂パッケージ４に分けて封止された例を示し、実施の形態２及び実施の形態３では、複数のシリコンチップ３の一部のみが一つの樹脂パッケージ４で封止された例を示している。
【００３５】
また、前記各実施の形態では、複数のシリコンチップ３の一部を樹脂パッケージ４に封止する例として、２以上のシリコンチップ３を一つの樹脂パッケージ４で封止した例を示したが、一つのシリコンチップ３を一つの樹脂パッケージ４で封止する構成も考えられる。
【００３６】
【発明の効果】
以上説明したように、この発明における請求項１記載の半導体装置は、複数のパワー半導体素子の一部のパワー半導体素子を当該一部のパワー半導体素子専用の樹脂パッケージで封止し、樹脂パッケージから露出したパワー半導体素子用の端子をケース内で外部接続端子に接続したため、樹脂パッケージに封止されている一部のパワー半導体素子に不良があった場合でも、一部のパワー半導体素子に専用の樹脂パッケージを同一機能の新たな樹脂パッケージと取り替えるという、必要最小限の取り替え作業によって良品とすることができる。その結果、製品としての不良率を大幅に低減できる。
加えて、請求項１記載の半導体装置は、樹脂パッケージから露出した端子と外部接続端子との接続をねじ止めにより行っているため、樹脂パッケージの取り替え作業を簡単に行うことができる。
【００３７】
請求項２記載の半導体装置は、２以上の樹脂パッケージのうち一部の樹脂パッケージに封止されているシリコンチップに不良があった場合、該当する樹脂パッケージを同一機能の新たな樹脂パッケージと取り替えることにより良品とすることができるので、製品の不良率を大幅に低減でき、他の樹脂パッケージやケースを無駄にすることなく、そのまま使用することができる。
【００３８】
さらに、２以上の樹脂パッケージそれぞれにおいて、種類の異なる別の樹脂パッケージと交換することもできるので、ケースをそのまま利用して特性の異なる製品を容易に作製することができる。
【００３９】
請求項３記載の半導体装置は、樹脂パッケージで封止されたパワー半導体素子と樹脂封止されずに所定の基板上に実装されたパワー半導体素子とをケース内に混在させることにより、設計自由度の向上を図ることができる。
【００４０】
また、所定の基板上に実装されたパワー半導体素子は、ヒートシンクを介した放熱作用によって、その発熱を効率良く放熱することができる。
【００４１】
請求項４記載の半導体装置は、樹脂パッケージと所定の基板との間でヒートシンクが共通化されるため、組立が簡単になる。
【００４２】
さらに、樹脂パッケージ内のパワー半導体素子による発熱も上記ヒートシンクを介した放熱作用によって効率良く放熱できる。
【図面の簡単な説明】
【図１】 この発明の実施の形態１である半導体装置の概略の構成を示す説明図である。
【図２】 樹脂パッケージの概略の構成を示す説明図である。
【図３】 この発明の実施の形態２である半導体装置の概略の構成を示す説明図である。
【図４】 この発明の実施の形態３よる半導体装置の概略の構成を示す説明図である。
【図５】 従来の半導体装置の概略構成を示す説明図である。
【符号の説明】
１ 外部接続端子、２ ケース、３ シリコンチップ（パワー半導体素子）、４ 樹脂パッケージ、５ 端子、６ ねじ、１１ 絶縁セラミック基板、１２，１９ 銅ベース板（ヒートシンク）、１４ エポキシ樹脂、１６ 共通銅ベース板。[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device such as a power semiconductor module.
[0002]
[Prior art]
FIG. 5 is an explanatory view showing a schematic configuration of a conventional power semiconductor module, and (a), (b) and (c) in FIG. 5 show a plan view, a longitudinal sectional view and a back view, respectively. In this power semiconductor module, in the storage space 24, a plurality of silicon chips 3 as power semiconductor elements are insulated ceramic substrate 11 (a three-layer structure of a substrate body 11a and a circuit pattern 11b formed of copper or the like on the front and back surfaces). These are soldered onto the circuit pattern 11b on the front main surface by solder 18 and housed in the resin case 2. The external connection terminal 1 is inserted into the case 2, and a copper base plate 17 that functions as a heat sink is disposed at the bottom of the case. A circuit pattern on the back main surface of the insulating ceramic substrate 11 is placed on the copper base plate 17. 11 b is soldered by the solder 18, and each silicon chip 3 and the external connection terminal 1 are connected by the wire 13. The storage space 24 is filled with the silicon gel 23, and the upper portion thereof is sealed with the epoxy resin 14, and the upper portion of the storage space 24 is closed with the lid body 25. Reference numeral 31 denotes a mounting hole for the power semiconductor element module itself.
[0003]
[Problems to be solved by the invention]
However, in the configuration in which a plurality of silicon chips 3 are soldered onto the insulating ceramic substrate 11 as in the power semiconductor module described above, even if only one of the silicon chips 3 becomes defective, the entire module is not suitable. There was a problem that many normal silicon chips 3 were wasted because they had to be made non-defective.
[0004]
Further, when many silicon chips 3 are mounted on one insulating ceramic substrate 11, the size of the insulating ceramic substrate 11 is increased, and there is a problem in that the occurrence of substrate cracking and solder void defects is increased.
[0005]
The present invention has been made to solve the above problems, and even if some power semiconductor elements are defective, the semiconductor can be made a non-defective product by a minimum necessary replacement operation including the power semiconductor elements. The object is to obtain a device.
[0006]
[Means for Solving the Problems]
The invention of claim 1 according to the present invention is a semiconductor device in which a plurality of power semiconductor elements are housed in a case provided with an external connection terminal , and at least one of the plurality of power semiconductor elements. each power semiconductor element parts sealed with only the resin package, connect the pin exposed from the resin package to the external connection terminals in the case, and terminals exposed from the resin package within said casing Connection with the external connection terminal is performed by screwing.
[0007]
According to a second aspect of the present invention, in the semiconductor device according to the first aspect, all of the plurality of power semiconductor elements are divided into two or more resin packages and sealed.
[0008]
The invention according to claim 3 is the semiconductor device according to claim 1, wherein the plurality of power semiconductor elements are mounted on the surface of a predetermined substrate without being sealed with the resin package. The heat sink is in contact with the back surface of the predetermined substrate.
[0009]
The invention according to claim 4 is the semiconductor device according to claim 3, wherein the heat sink is further brought into contact with the resin package.
[0011]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, the present invention will be specifically described with reference to the drawings showing embodiments thereof. Members that are the same as or equivalent to those in the conventional example shown in FIG.
[0012]
<Embodiment 1>
FIG. 1 is an explanatory view showing a schematic configuration of a semiconductor device according to Embodiment 1 of the present invention. FIGS. 1 (a), (b) and (c) are plan views partially broken, respectively. The longitudinal cross-sectional view and the back view are shown. The semiconductor device of the first embodiment is a power semiconductor module configured by housing a plurality of silicon chips, which are power semiconductor elements, in a resin case 2 in which an external connection terminal 1 is inserted.
[0013]
FIG. 2 is an explanatory view showing a schematic configuration of the resin package. FIGS. 2A, 2B, and 2C are respectively a plan view, a longitudinal sectional view, and a rear view, partially broken. . As shown in FIG. 2, each silicon chip 3 is divided into two discrete type resin packages 4 and sealed.
[0014]
That is, a circuit in which one or a plurality of silicon chips 3 are formed on the front main surface of an insulating ceramic substrate 11 (a three-layer structure of a substrate body 11a and a circuit pattern 11b formed of copper or the like on the front and back surfaces). The pattern 11b is mounted by soldering with the solder 18, and the back main surface of the insulating ceramic substrate 11 is soldered to the copper base plate 12 as a heat sink by the solder 18. Furthermore, after the terminals 5 are soldered to the circuit pattern 11b on the main surface of the insulating ceramic substrate 11 by the solder 18, and each silicon chip 3 and the terminals 5 are electrically connected by the wires 13 and the circuit pattern 11b, The main part on the copper base plate 12 including the insulating ceramic substrate 11 on which the silicon chip 3 is mounted and the terminals 5 is sealed with an epoxy resin 14 to form a resin package 4.
[0015]
In this way, the plurality of silicon chips 3 are sealed in two resin packages 4 here, and as shown in FIG. 1, the terminals 5 exposed from each resin package 4 are the corresponding external connection terminals 1. Are connected by screws 6. Each resin package 4 is fixed to the bottom of the case 2 with a screw 7. Furthermore, a heat radiating window 8 is opened at a portion where the resin package 4 at the bottom of the case 2 is disposed, and the upper opening 9 of the case 2 is closed by a lid 10. Reference numeral 31 denotes a mounting hole for the semiconductor device itself of the first embodiment.
[0016]
In the power semiconductor module having such a configuration, when there is a defect in the silicon chip 3 sealed in one resin package 4, the corresponding resin package 4 is replaced with a new resin package 4 having the same function. Since it can be made non-defective, the product defect rate can be greatly reduced. Further, the other resin package 4 and the case 2 can be used as they are without being wasted.
[0017]
As described above, the semiconductor device according to the first embodiment can be made a non-defective product by the minimum necessary replacement work, that is, the replacement work of the resin package 4 unit.
[0018]
Further, the terminal 5 for the silicon chip 3 exposed from the resin package 4 and the external connection terminal 1 are connected by a screw 6, and the resin package 4 itself is also screwed using, for example, the screw hole 15 of the copper base plate 12. 7, the replacement work can be performed easily and quickly using a general-purpose tool. Furthermore, since the resin package 4 can be exchanged for another resin package 4 of a different type, the power semiconductor module having different characteristics can be easily manufactured using the case 2 as it is.
[0019]
In addition, since the plurality of silicon chips 3 are sealed by being divided into two resin packages 4, the size of the insulating ceramic substrate 11 is larger than the conventional structure in which the plurality of silicon chips 3 are mounted on one insulating ceramic substrate 11. Therefore, it is possible to reduce the occurrence of substrate cracks and solder void defects.
[0020]
<Embodiment 2>
3 is an explanatory view showing a schematic configuration of a semiconductor device according to Embodiment 2 of the present invention. FIGS. 3 (a), (b) and (c) are respectively a partially broken plan view and a longitudinal section. A front view and a back view are shown. The semiconductor device of the second embodiment is also a power semiconductor module configured by housing a plurality of silicon chips as power semiconductor elements in a resin case 2 in which the external connection terminals 1 are inserted.
[0021]
In this power semiconductor module, the inside of the resin case 2 into which the external connection terminal 1 is inserted is divided into two storage spaces 21 and 22, and one storage space 21 has one resin shown in the first embodiment. The package 4 is stored, and the other storage space 22 stores a plurality of silicon chips 3 that are not sealed with the resin package 4. The silicon chip 3 that is not sealed with the resin package 4 includes a chip that generates a larger amount of heat than the silicon chip 3 that is sealed with the resin package 4.
[0022]
The storage structure of the resin package 4 in the storage space 21 is the same as that of the first embodiment shown in FIGS. 1 and 2, and the description thereof is omitted here. The storage of the silicon chip 3 in the storage space 22 is the same as in the conventional example shown in FIG. That is, the plurality of silicon chips 3 are mounted on the circuit pattern 11 b formed on the front main surface of the insulating ceramic substrate 11 by soldering with the solder 18, and the insulating ceramic substrate 11 is stored in the storage space 22. . A copper base plate 19 as a heat sink is installed at the bottom of the storage space 22, and the back main surface of the insulating ceramic substrate 11 is brought into contact with the copper base plate 19 by soldering with solder 18.
[0023]
Further, between the silicon chips 3 and 3 on the insulating ceramic substrate 11, between the silicon chip 3 and the corresponding external connection terminal 1, or between the circuit pattern 11b on the insulating ceramic substrate 11 and the corresponding external connection terminal 1. Are connected by a wire 13. As described above, after the insulating ceramic substrate 11 is stored in the storage space 22, the storage space 22 is filled with the silicon gel 23, and the upper portion thereof is sealed with the epoxy resin 14, and finally the upper portion of the storage space 22. The opening 29 is closed by the lid 30. FIG. 3A shows a state in which the storage space 22 is not filled with the silicon gel 23 or the epoxy resin 14.
[0024]
Even in this power semiconductor module, when the silicon chip 3 sealed with the resin package 4 has a defect, the resin package 4 can be replaced, so that the defect rate of the product can be reduced.
[0025]
In this power semiconductor module, the back main surface of the insulating ceramic substrate 11 on which the silicon chip 3 that is not sealed with the resin package 4 and has a larger calorific value than the silicon chip 3 included in the resin package 4 is mounted on the solder 18 The contact is made by contacting with the surface of the copper base plate 19 which is a heat sink installed at the bottom of the storage space 22 by soldering.
[0026]
Therefore, in the semiconductor device of the second embodiment, the silicon chip 3 sealed with the resin package 4 and the silicon chip 3 mounted on the insulating ceramic substrate 11 without being resin-sealed are combined with the storage spaces 21, The degree of freedom in design can be improved by intermingling them in each of them.
[0027]
Further, heat generated from the silicon chip 3 mounted on the insulating ceramic substrate 11 without being resin-sealed can be efficiently radiated by the heat radiation action via the copper base plate 19. As shown in FIG. 3 (c), the surface area of the copper base plate 19 is sufficiently larger than the surface area of the copper base plate 12 of the resin package 4, so that the silicon in the storage space 22 having a large heat generation amount is formed. Heat generated from the chip 3 can be efficiently radiated by the copper base plate 19.
[0028]
<Embodiment 3>
FIG. 4 is an explanatory view showing a schematic configuration of a semiconductor device according to Embodiment 3 of the present invention. FIGS. 4 (a), 4 (b) and 4 (c) are respectively a partially broken plan view and a longitudinal section. A front view and a back view are shown. The semiconductor device of the third embodiment is also a power semiconductor module configured by housing a plurality of silicon chips 3 that are power semiconductor elements in a resin case 2 in which the external connection terminals 1 are inserted.
[0029]
In this power semiconductor module, the common copper base plate 16 which is a heat sink common to the resin package 4 accommodated in the accommodation space 21 and the silicon chip 3 accommodated in the accommodation space 22 in the power semiconductor module of the second embodiment. Is installed over the entire area of the bottom of the case 2.
[0030]
That is, the back main surface of the insulating ceramic substrate 11 in the storage space 22 in which the silicon chip 3 is mounted is connected to the surface of the common copper base plate 16 by soldering with the solder 18 and is connected to the inside of the storage space 21. The resin package 4 is also brought into contact with the surface of the same common copper base plate 16 and connected by screwing using screws 27. Other configurations are the same as those in the second embodiment.
[0031]
As shown in FIG. 4C, the surface area of the common copper base plate 16 has a sufficiently large formation area corresponding to the bottom area of the case 2, and the heat radiation function is remarkably excellent. Heat generated from any silicon chip 3 in the storage space 22 can be efficiently radiated.
[0032]
Further, since the common copper base plate 16 serving as a heat sink is shared between the resin package 4 in the storage space 21 and the insulating ceramic substrate 11 in the storage space 22, assembly is simplified.
[0033]
<Others>
In each of the above-described embodiments, the case where the terminal 5 exposed from the resin package 4 and the external connection terminal 1 are connected by screwing has been described. Also good. Further, the resin package 4 is not limited to the case where the resin package 4 is fixed to the case 2 with the screws 7 as in the above-described embodiments, but may be stably housed in the case 2 according to other modes.
[0034]
Each of the above embodiments shows an example in which a part of silicon chips 3 among a plurality of silicon chips 3 are sealed in the part of the silicon chips 3 with a dedicated resin package 4. An example in which all of the plurality of silicon chips 3 are divided and sealed into two resin packages 4 is shown. In the second and third embodiments, only a part of the plurality of silicon chips 3 is a single resin package 4. The example sealed with is shown.
[0035]
In each of the above-described embodiments, an example in which two or more silicon chips 3 are sealed with one resin package 4 as an example of sealing a part of the plurality of silicon chips 3 with the resin package 4 has been described. A configuration in which one silicon chip 3 is sealed with one resin package 4 is also conceivable.
[0036]
【The invention's effect】
As described above, in the semiconductor device according to claim 1 of the present invention, a part of the power semiconductor elements of the plurality of power semiconductor elements is sealed with the resin package dedicated to the part of the power semiconductor elements. Since the exposed terminals for power semiconductor elements are connected to external connection terminals in the case, even if some power semiconductor elements sealed in the resin package are defective, they are dedicated to some power semiconductor elements. The resin package can be made a non-defective product by the minimum necessary replacement work of replacing the resin package with a new resin package having the same function. As a result, the defective rate as a product can be greatly reduced.
In addition, in the semiconductor device according to the first aspect, since the connection between the terminal exposed from the resin package and the external connection terminal is performed by screwing, the replacement work of the resin package can be easily performed.
[0037]
According to a second aspect of the present invention, when a silicon chip sealed in a part of the two or more resin packages is defective, the corresponding resin package is replaced with a new resin package having the same function. Therefore, the defective rate of the product can be greatly reduced, and other resin packages and cases can be used as they are without being wasted.
[0038]
Furthermore, since each of the two or more resin packages can be exchanged for another type of resin package, products having different characteristics can be easily produced by using the case as it is.
[0039]
The semiconductor device according to claim 3 includes a power semiconductor element sealed with a resin package and a power semiconductor element not mounted on the resin and mounted on a predetermined substrate in a case, thereby allowing a degree of design freedom. Can be improved.
[0040]
Further, the power semiconductor element mounted on a predetermined substrate can efficiently dissipate the heat generated by the heat dissipation action via the heat sink.
[0041]
In the semiconductor device according to the fourth aspect, since the heat sink is shared between the resin package and the predetermined substrate, the assembly is simplified.
[0042]
Furthermore, heat generated by the power semiconductor element in the resin package can also be efficiently dissipated by the heat dissipating action via the heat sink.
[Brief description of the drawings]
FIG. 1 is an explanatory diagram showing a schematic configuration of a semiconductor device according to a first embodiment of the present invention;
FIG. 2 is an explanatory diagram showing a schematic configuration of a resin package.
FIG. 3 is an explanatory diagram showing a schematic configuration of a semiconductor device according to a second embodiment of the present invention;
FIG. 4 is an explanatory diagram showing a schematic configuration of a semiconductor device according to a third embodiment of the present invention.
FIG. 5 is an explanatory diagram showing a schematic configuration of a conventional semiconductor device.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 External connection terminal, 2 Case, 3 Silicon chip (power semiconductor element), 4 Resin package, 5 Terminal, 6 Screw, 11 Insulating ceramic substrate, 12, 19 Copper base board (heat sink), 14 Epoxy resin, 16 Common copper base Board.

Claims (4)

外部接続端子が設けられたケース内に複数のパワー半導体素子を収納してなる半導体装置であって、
前記複数のパワー半導体素子のうち、少なくとも一部のパワー半導体素子それぞれを専用の樹脂パッケージで封止し、前記樹脂パッケージから露出した端子を前記ケース内で前記外部接続端子に接続し、
前記ケース内における前記樹脂パッケージから露出した端子と前記外部接続端子との接続をねじ止めによって行ったことを特徴とする、
半導体装置。A semiconductor device comprising a plurality of power semiconductor elements housed in a case provided with external connection terminals,
Wherein among the plurality of power semiconductor elements, at least a portion of the power semiconductor elements respectively sealed with only the resin package, connect the pin exposed from the resin package to the external connection terminals in the case,
The connection between the terminal exposed from the resin package in the case and the external connection terminal is performed by screwing,
Semiconductor device. 請求項１記載の半導体装置であって、
前記複数のパワー半導体素子すべてを２以上の前記樹脂パッケージに分けて封止したことを特徴とする、
半導体装置。The semiconductor device according to claim 1,
The plurality of power semiconductor elements are all divided into two or more resin packages and sealed,
Semiconductor device. 請求項１記載の半導体装置であって、
前記複数のパワー半導体素子は、前記樹脂パッケージで封止されずに所定の基板の表面上に実装されたパワー半導体素子を含み、
ヒートシンクを前記所定の基板の裏面に当接させたことを特徴とする、
半導体装置。The semiconductor device according to claim 1,
The plurality of power semiconductor elements include a power semiconductor element mounted on a surface of a predetermined substrate without being sealed with the resin package,
A heat sink is brought into contact with the back surface of the predetermined substrate,
Semiconductor device. 請求項３記載の半導体装置であって、
前記ヒートシンクは前記樹脂パッケージにさらに当接される、
半導体装置。The semiconductor device according to claim 3,
The heat sink is further brought into contact with the resin package;
Semiconductor device.
JP2000255337A 2000-08-25 2000-08-25 Semiconductor device Expired - Fee Related JP4108909B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2000255337A JP4108909B2 (en) 2000-08-25 2000-08-25 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2000255337A JP4108909B2 (en) 2000-08-25 2000-08-25 Semiconductor device

Publications (2)

Publication Number Publication Date
JP2002076258A JP2002076258A (en) 2002-03-15
JP4108909B2 true JP4108909B2 (en) 2008-06-25

Family

ID=18744144

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2000255337A Expired - Fee Related JP4108909B2 (en) 2000-08-25 2000-08-25 Semiconductor device

Country Status (1)

Country Link
JP (1) JP4108909B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2013121491A1 (en) 2012-02-13 2013-08-22 パナソニック株式会社 Semiconductor device and method for manufacturing same

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5895220B2 (en) * 2012-05-15 2016-03-30 パナソニックＩｐマネジメント株式会社 Manufacturing method of semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2013121491A1 (en) 2012-02-13 2013-08-22 パナソニック株式会社 Semiconductor device and method for manufacturing same
US9136193B2 (en) 2012-02-13 2015-09-15 Panasonic Intellectual Property Management Co., Ltd. Semiconductor device and method of manufacturing the same

Also Published As

Publication number Publication date
JP2002076258A (en) 2002-03-15

Similar Documents

Publication Publication Date Title
EP0594395B1 (en) Semiconductor power module
US5598031A (en) Electrically and thermally enhanced package using a separate silicon substrate
US5886408A (en) Multi-chip semiconductor device
KR100752239B1 (en) Power module package structure
US6091142A (en) Assembly for dissipating heat from a stacked semiconductor package
US6404048B2 (en) Heat dissipating microelectronic package
JPH09139461A (en) Semiconductor power module
US5525835A (en) Semiconductor chip module having an electrically insulative thermally conductive thermal dissipator directly in contact with the semiconductor element
US6922338B2 (en) Memory module with a heat dissipation means
KR100598652B1 (en) Semiconductor device
JP4108909B2 (en) Semiconductor device
GB2168533A (en) Package for integrated circuits having improved heat sinking capabilities
JPH11307721A (en) Power module device and method of manufacturing the same
US7310224B2 (en) Electronic apparatus with thermal module
US20060220188A1 (en) Package structure having mixed circuit and composite substrate
KR20000071430A (en) Electrical power component mounted by brazing on a support and corresponding mounting process
JPH08264688A (en) Ceramic package for semiconductor
JPH02278856A (en) Semiconductor integrated circuit device
JPH09121018A (en) Semiconductor device
JP2765242B2 (en) Integrated circuit device
JP2919313B2 (en) Printed wiring board and its mounting method
JPH0393259A (en) Semiconductor device
JP4330293B2 (en) Power semiconductor device
JP3235346B2 (en) IC package
JP2001024149A (en) Semiconductor device

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20060206

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20080111

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20080122

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20080303

RD04 Notification of resignation of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7424

Effective date: 20080303

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20080401

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20080403

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20110411

Year of fee payment: 3

R150 Certificate of patent or registration of utility model

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120411

Year of fee payment: 4

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120411

Year of fee payment: 4

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130411

Year of fee payment: 5

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130411

Year of fee payment: 5

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20140411

Year of fee payment: 6

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

LAPS Cancellation because of no payment of annual fees