JP4284783B2 - Solid-state imaging device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a solid-state imaging device.
[0002]
[Prior art]
2. Description of the Related Art Conventionally, a solid-state imaging device used for a video camera or a digital camera is generally configured using a CCD (Charge Coupled Device) type solid-state imaging device.
This type of solid-state imaging device includes a plurality of optical sensors arranged in a matrix, a vertical transfer unit that transfers signal charges obtained by the optical sensors in a vertical direction, and each optical sensor when a timing signal is given. And a plurality of readout gates that read out the signal charges obtained from step 1 from each photosensor and supply them to the vertical transfer unit.
[0003]
The timing signal is supplied from a timing signal generator that constitutes the solid-state imaging device. When the timing signal is supplied to the solid-state imaging device, a bias of 15 V or 12 V is applied to the readout gate, whereby the light sensor outputs The signal charge is read out.
FIG. 5 is a timing chart showing the timing signal.
When the vertical transfer unit is a three-phase drive system, the timing signal generator generates three-phase timing signals V1, V2, and V3 and supplies them to the vertical transfer unit as shown in FIG. Then, the bias voltage is applied to the read gate during the period t1 when the timing signal V2 is at a high level.
[0004]
By the way, one effective method for reducing the power consumption of the electronic device is to reduce the power supply voltage. In the solid-state imaging device, the power consumption can be reduced by reducing the power supply voltage.
However, if this method is simply applied to a solid-state imaging device and the bias voltage applied to the readout gate is lowered, there is a problem that the signal charge cannot be sufficiently read from the photosensor.
FIG. 6 is a potential distribution diagram showing the potential distribution around the optical sensor of the solid-state imaging device, and FIG. 7 is a sectional side view showing the periphery of the optical sensor. FIG. 6 shows a potential distribution along the line II ′ in FIG. In FIG. 7, an optical sensor 104 is formed on a semiconductor substrate (SUB) 102, and a vertical transfer unit 106 is formed adjacent to the optical sensor 104. A readout gate 108 is formed between the optical sensor 104 and the vertical transfer unit 106.
[0005]
When the bias voltage applied to the read gate 108 is sufficiently high, as indicated by the solid line 110 in FIG. 6, the potential in the vertical transfer unit 106 is sufficiently low, and the signal charge from the photosensor 104 to the vertical transfer unit 106 is high. Is reliably read out. On the other hand, when the bias voltage applied to the readout gate 108 is low, as indicated by the dotted line 112 in FIG. It will be enough.
[0006]
Conventionally, as a technique for lowering the bias voltage applied to the readout gate 108, a technique has been used in which the sensor potential is lowered by adjusting the impurity concentration in the semiconductor material constituting the photosensor portion. There is a tendency that excessive charges accumulated in the sensor 104 are not properly discharged to the semiconductor substrate 102.
[0007]
FIG. 8 is a potential distribution diagram showing the potential distribution around the optical sensor 104 when the sensor potential is lowered, and shows the potential distribution at the same position as in FIG. The dotted curve 114 in the figure shows the distribution when the sensor potential is lowered. As can be seen from FIG. 7, the barrier potential 118 of the overflow barrier (OFB) formed by the P-type well region 116 in FIG. 7 is greatly increased, and excess charge accumulated in the photosensor 104 is discharged to the semiconductor substrate 102. It has become difficult.
[0008]
In FIG. 8, a curve 120 indicates a potential when reading out signal charges from the optical sensor 104, and a curve 122 and a curve 124 indicate potentials when transferring signal charges in the vertical transfer unit 106. When the barrier potential 118 is increased to the state shown in FIG. 7, the height exceeds the potential 126 of the readout gate 108 at the time of signal charge transfer. Therefore, in this case, vertical transfer from the photosensor 104 also at the time of signal charge transfer. There is also a problem that signal charges are read out to the unit 106.
In FIG. 8, the areas A to F indicate the pixel separation portion, the vertical transfer unit 106, the readout gate 108, the photosensor 104, the overflow barrier, and the semiconductor substrate 102.
[0009]
[Problems to be solved by the invention]
The present invention has been made to solve such problems, and an object of the present invention is to provide a solid-state imaging device capable of reducing power consumption by suppressing a voltage applied to a read gate without degrading performance. There is.
[0010]
[Means for Solving the Problems]
In order to achieve the above object, the present invention provides a plurality of photosensors arranged in a matrix, a vertical transfer unit for transferring signal charges obtained by the photosensors in the vertical direction, and a timing signal. A solid-state imaging device comprising: a plurality of readout gates that read out the signal charges obtained from each photosensor from each photosensor and supply the signal charges to the vertical transfer unit; and a timing signal generation unit that generates the timing signal. The readout gate includes at least first and second readout gates that read out the signal charges from the different photosensors, and the timing signal generation unit uses the first and second readout gates as the timing signal. the generating a first and a second timing signal for driving each of said first read gate is the The photosensors for reading signal charges form a first pair, the photosensors for each pair are arranged adjacent in the vertical direction, and the second read gate reads the signal charges for the photosensors. The pair of optical sensors are arranged adjacent to each other in the vertical direction, and the first pair and the second pair are alternately arranged in the vertical direction, and the timing signal generator Is characterized in that the second timing signal is generated with a delay of time t2 (t2 <t1) from the start of generation of the first timing signal of duration t1 .
[0011]
As a result of the experiment by the inventor of the present invention, when the second timing signal is delayed from the first timing signal, the amount of signal charge read from the photosensor is not reduced within a range up to a certain delay amount, It has been found that the voltage applied to the read gate can be reduced as the delay amount of the second timing signal is increased.
In the present invention, since the potential distribution around the optical sensor is invariant, the conventional problems such as poor signal charge readout, insufficient sweeping out of excessive signal charge, or unnecessary signal charge readout do not occur.
Therefore, according to the present invention, it is possible to reduce the power supply voltage of the solid-state imaging device by suppressing the voltage applied to the read gate without degrading the performance, thereby realizing reduction in power consumption.
Conversely, if the voltage applied to the readout gate is the same as before, the signal charge from the optical sensor can be read more reliably, improving the performance of the solid-state imaging device and improving the manufacturing yield. It is valid.
[0012]
DETAILED DESCRIPTION OF THE INVENTION
Next, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 is a schematic partial configuration diagram showing a solid-state imaging device constituting an example of a solid-state imaging device according to the present invention, and FIG. 2 is a configuration diagram showing an example of a solid-state imaging device according to the present invention. In the figure, the same elements as those in FIG.
As illustrated in FIGS. 1 and 2, the solid-state imaging device 2 according to the embodiment includes a plurality of optical sensors 104 arranged in a matrix on a semiconductor substrate 102 constituting the solid-state imaging element 3, and the optical sensors 104. And a vertical transfer unit 106 that transfers the signal charge obtained in the above in the vertical direction, and when a timing signal is given, the signal charge obtained by each photosensor 104 is read from each photosensor 104 and supplied to the vertical transfer unit 106 And a timing signal generator 4 for supplying a timing signal to the read gate 108.
[0013]
In the present embodiment, the read gate 108 includes first and second read gates 6 and 8 (FIG. 1) that read signal charges from different optical sensors A and B (104), respectively, and the timing signal generator 4 Generates timing signals V2A and V2B (first and second timing signals according to the present invention) as timing signals for driving the first and second read gates 6 and 8, respectively. In this embodiment, the timing signal V2B is delayed by 100 ns or more from the timing signal V2A.
[0014]
The solid-state image pickup device 3 is provided with a driver circuit (not shown) for driving the read gate 108. When the timing signals V2A and V2B are supplied from the timing signal generator 4, the driver circuit reads the signal charge. Is applied to each read gate 108.
[0015]
As shown in FIG. 1, the optical sensor A from which the first readout gate 6 reads out signal charges and the optical sensor B from which the second readout gate 8 reads out signal charges alternate in the vertical direction (the direction of the arrow V). Is arranged.
More specifically, in the present embodiment, as shown in FIG. 1 as an example, the first read gate 6 reads out the signal charges to form a pair, and each pair of the photosensors A is in the vertical direction. The photosensors B are arranged adjacent to each other, and the second readout gate 8 reads the signal charges to form a pair, and the photosensors B forming each pair are arranged adjacent to each other in the vertical direction.
[0016]
As an example in the present embodiment, the vertical transfer unit 106 transfers the signal charges received from the respective optical sensors 104 based on the three-phase driving method. For this purpose, the timing signal generation unit 4 uses the three-phase timing signal as the first phase signal. The one-phase timing signal V1, the second-phase timing signals V2A and V2B, and the third-phase timing signal V3 are generated and supplied to the vertical transfer unit 106.
[0017]
As shown in FIGS. 1 and 2, the horizontal transfer unit 10 is disposed at the lower end of the vertical transfer unit 106, and is configured to receive signal charges from the vertical transfer units 106 and sequentially transfer them in the horizontal direction. .
In addition, the solid-state imaging device 2 includes a mechanical shutter 11, which is opened and closed by a signal from a control unit 12 that operates under the control of the timing signal generation unit 4. The optical sensor 104 is exposed by the mechanical shutter 11 for a necessary time, and accumulates signal charges.
[0018]
Next, the operation of the solid-state imaging device 2 configured as described above will be described.
FIG. 3 is a timing chart showing the operation of the solid-state imaging device 2 of the embodiment.
As shown in FIG. 3, in the present embodiment, the timing signal generation unit 4 outputs the timing signal V <b> 1 and then generates the timing signal V <b> 2 </ b> A (high level) and supplies it to the solid-state imaging device 3. As a result, the driver circuit applies a bias voltage for reading the signal charge to the first read gate 6 for the duration t1 of the timing signal V2A, and the signal from each photosensor A through the first read gate 6. The charges are read and supplied to the vertical transfer unit 106.
[0019]
Thereafter, the timing signal generator 4 generates the timing signal V2B (high level) and supplies it to the solid-state imaging device after the time t2 of 100 ns or more has elapsed. As a result, the driver circuit applies a bias voltage for reading the signal charge to the second read gate 8, and the signal charge is read from each photosensor B through the second read gate 8, and is sent to the vertical transfer unit 106. Supplied.
The timing signal generator 4 outputs the timing signal V2A, then sets the timing signal V1 to a low level, and the time t3 from the rise of the timing signal V2A to the fall of the timing signal V1 , Approximately t2 / 2.
[0020]
The signal charges supplied to the vertical transfer unit 106 are transferred in the vertical direction and reach the horizontal transfer unit 10, and then, in the horizontal transfer unit 10, the two-phase timing signals H 1 and H 2 supplied from the timing signal generation unit 4. Are transferred in the horizontal direction and output from the terminal 14 as a video signal.
[0021]
The inventor of the present invention conducted an experiment to examine the relationship between the delay time of the timing signal V2B with respect to the timing signal V2A and the bias voltage applied to the read gate 108. Specifically, the magnitude of the bias voltage that can secure the required amount of signal charge read was measured while gradually increasing the delay time.
FIG. 4 shows the measurement results, and is a graph showing the relationship between the delay time of the timing signal V2B with respect to the timing signal V2A and the bias voltage applied to the read gate 108. In the figure, the horizontal axis represents the delay time t2, and the vertical axis represents the amount of decrease ΔVT from the conventional bias voltage VT.
[0022]
As can be seen from this graph, the decrease amount ΔVT of the bias increases in proportion to the delay time until the delay time t2 is 600 ns, and the decrease amount ΔVTmax when the delay time t2 is 600 ns is about 0.5V. ing.
Therefore, from this experimental result, the delay time t2 is set within the range of 100 ns or more and 700 ns or less in consideration of the variation of the elements in the solid-state imaging device 3 and the timing signal generation unit 4, and is applied to the readout gate 108. It can be said that the bias voltage can be effectively reduced.
[0023]
In this embodiment, since the potential distribution around the optical sensor 104 is not changed, there are problems such as conventional signal charge reading failure, insufficient signal charge sweeping out, or unnecessary signal charge reading. Does not occur.
Therefore, in the solid-state imaging device 2 according to the present embodiment, the power supply voltage of the solid-state imaging device 2 can be lowered by suppressing the voltage applied to the readout gate 108 without degrading the performance, and the power consumption can be reduced.
Conversely, when the voltage applied to the readout gate 108 is the same as before, the signal charge from the optical sensor 104 can be read more reliably, improving the performance of the solid-state imaging device 2 and the production yield. It is effective for improvement.
In this embodiment, the optical sensor and the readout gate are divided into two systems. However, the optical sensor and the readout gate may be divided into three or more systems so that signal charges are read from the optical sensors at different timings. Can be obtained.
[0024]
【The invention's effect】
As described above, the present invention provides a plurality of photosensors arranged in a matrix, a vertical transfer unit that transfers signal charges obtained by the photosensors in the vertical direction, and a timing signal. A solid-state imaging device comprising: a plurality of readout gates for reading out the signal charges obtained by the optical sensors from the optical sensors and supplying the signal charges to the vertical transfer unit; and a timing signal generating unit for generating the timing signal. The readout gate includes at least first and second readout gates that read out the signal charges from the different photosensors, and the timing signal generator uses the first and second readout gates as the timing signals, respectively. generating a first and a second timing signal for driving said first read gate is the signal electric The photosensors for reading out a first pair form the first pair, the photosensors in each pair are arranged adjacent to each other in the vertical direction, and the second readout gate reads out the signal charge. The photosensors forming a pair are arranged adjacent to each other in the vertical direction, the first pair and the second pair are alternately arranged in the vertical direction, and the timing signal generation unit includes: The second timing signal is generated with a delay of time t2 (t2 <t1) from the generation start of the first timing signal of the duration t1 .
[0025]
As a result of the experiment by the inventor of the present invention, when the second timing signal is delayed from the first timing signal, the amount of signal charge read from the photosensor is not reduced within a range up to a certain delay amount, It has been found that the voltage applied to the read gate can be reduced as the delay amount of the second timing signal is increased.
In the present invention, since the potential distribution around the optical sensor is invariant, there are no problems such as conventional signal charge readout failure, insufficient signal charge sweeping out, or unnecessary signal charge readout.
Therefore, according to the present invention, it is possible to reduce the power supply voltage of the solid-state imaging device by suppressing the voltage applied to the read gate without degrading the performance, thereby realizing reduction in power consumption.
Conversely, if the voltage applied to the readout gate is the same as before, the signal charge from the optical sensor can be read more reliably, improving the performance of the solid-state imaging device and improving the manufacturing yield. It is valid.
[Brief description of the drawings]
FIG. 1 is a schematic partial configuration diagram showing a solid-state imaging device constituting an example of a solid-state imaging device according to the present invention.
FIG. 2 is a configuration diagram showing an example of a solid-state imaging device according to the present invention.
FIG. 3 is a timing chart illustrating an operation of the solid-state imaging device according to the embodiment.
FIG. 4 is a graph showing a relationship between a delay time of the timing signal V2B with respect to the timing signal V2A and a bias voltage applied to the read gate.
FIG. 5 is a timing chart showing timing signals in a conventional solid-state imaging device.
FIG. 6 is a potential distribution diagram showing a potential distribution around the optical sensor of the solid-state imaging device.
FIG. 7 is a sectional side view showing the periphery of the optical sensor.
FIG. 8 is a potential distribution diagram showing a potential distribution around the optical sensor when the sensor potential is lowered.
[Explanation of symbols]
2... Solid-state imaging device, 3... Solid-state imaging device, 4... Timing signal generator, 6... First readout gate, 8. Control unit 14 ... Terminal 102 102 Semiconductor substrate 104 Optical sensor 106 Vertical transfer unit 108 Reading gate 110 Solid line 112 Dotted line 114 Curve 116 ... P-type well region, 118 ... barrier potential, 120 ... curve, 122 ... curve, 124 ... curve, 126 ... potential.

Claims (1)

A plurality of optical sensors arranged in a matrix;
A vertical transfer unit for transferring the signal charge obtained by the photosensor in the vertical direction;
When a timing signal is given, a plurality of readout gates that read out the signal charges obtained from each photosensor from each photosensor and supply the signal charges to the vertical transfer unit,
A solid-state imaging device comprising a timing signal generator for generating the timing signal,
The read gate comprises at least first and second read gates for reading the signal charges from the different photosensors,
The timing signal generator generates first and second timing signals for driving the first and second read gates as the timing signal,
The photosensors from which the first readout gate reads the signal charge form a first pair, and the photosensors in each pair are arranged adjacent in the vertical direction;
The photosensors from which the second readout gates read the signal charges form a second pair, and the photosensors in each pair are arranged adjacent in the vertical direction;
The first pair and the second pair are alternately arranged in a vertical direction;
The timing signal generation unit generates the second timing signal with a delay of time t2 (t2 <t1) from the generation start of the first timing signal of the duration t1.
Solid-state imaging device.

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