JP4214978B2 - Semiconductor memory device and signal processing system - Google Patents

Description

  The present invention relates to a semiconductor memory device such as a NAND flash memory in which a memory string is connected to a bit line and a source line via a selection switch, for example, and a signal processing system including the semiconductor memory device. The present invention relates to speeding up the reading operation of the apparatus.

  In a NAND flash memory, a plurality of memory transistors are connected in series to form a memory string, and two memory strings share one bit contact and a source line, thereby realizing high integration. Yes.

In a general NAND flash memory, the erase operation is performed on the substrate of the memory array, for example, by setting 0V to all word lines to which the selected memory string is connected and floating all word lines to which the non-selected memory string is connected. A high voltage (20V) is applied.
As a result, electrons are extracted from the floating gate to the substrate only in the memory transistor of the selected memory string. As a result, the threshold voltage of the memory transistor shifts in the negative direction to be, for example, -3V.

In addition, the data write operation is performed in units of so-called pages of several hundred to several thousand bytes in a batch of memory transistors connected to the selected word line.
Specifically, for example, a high voltage (for example, 18V) is connected to the word line to be selected, 0V is applied to the bit line to which the memory transistor to be written (0 data) is connected, and a memory transistor to be prohibited from being written (1 data). A high level (eg, 3.3 V) is applied to the bit line.
As a result, electrons are injected into the floating gate only in the selected memory transistor to be written, and the threshold voltage of the selected memory transistor shifts in the positive direction to be about 2V, for example.

In such a NAND flash memory, since data writing and erasing are performed by an FN (Fowler Nordheim) tunnel current, it is relatively easy to supply an operating current from an on-chip booster circuit, and it operates with a single power source. There is an advantage that it is easy to make.
Furthermore, data is written in units of pages, that is, in a batch of memory transistors connected to the selected word line, which is advantageous in terms of writing speed as compared with the NOR type flash memory.

In addition, in reading data in a NAND flash memory, data stored in a memory cell is determined through a sense amplifier in units of randomly accessed pages, stored in a data register, and then page data is stored in units of 1 or 2 bytes. This is done by serially transferring externally.
Specifically, for example, 0V is applied to the selected word line, and a voltage of about 4V is applied to all unselected word lines.
In the case of a NAND type flash memory, since a plurality of memory cells are connected in series, the read current of the memory cell is smaller than that of a NOR type flash memory, so that data stored in the memory cell is passed through a sense amplifier. The so-called random access time is long.

As described above, the NAND flash memory can be performed at a certain high speed in the writing and erasing times.
However, the conventional NAND flash memory has a disadvantage that the read transfer rate is low in the following points in addition to the long random access time.

A conventional NAND flash memory can only instruct reading from a page corresponding to one address at a time from the outside, regardless of the physical configuration of bank division inside the flash memory.
When internal reading of the page corresponding to a certain address is completed, the determined data is stored in the data register, but the next page cannot be automatically read internally until this data is transferred to the outside. . For this reason, it is necessary to have a long random access time again even if an instruction for reading the next page is given from the outside after the external transfer of data.

  Further, since command / address input and data input / output interface (I / F) pins are shared, no other access is possible during the data input / output period.

  The present invention has been made in view of such circumstances, and an object thereof is to provide a semiconductor memory device and a signal processing system capable of reading data at high speed and continuously.

In order to achieve the above object, a semiconductor memory device according to a first aspect of the present invention includes a cell array in which memory cells are arranged in a matrix and reads data according to an address, and data read from the cell array. A first latch circuit for holding, and a second latch circuit for transferring the held data of the first latch circuit at a predetermined timing and holding the transferred data. a flag register in advance flag value is set and data holding means which allows to transfer the read out data data is stored in the external, and a plurality of banks including, the command value input to the above second A bank switching circuit for inputting / outputting data from a latch circuit through a column selector selectively controlled by a column decoder; Select any one of the banks in the tank, and a control circuit for the completion of the access of the memory cell array is notified with reference to the value set in the flag register, and outputs an access instruction in the selected bank Current address holding means provided corresponding to each of the plurality of banks and holding an address for reading data of the cell array, and at least a reserved address from the outside in advance by an access reservation command for the next reading Receiving and holding reserved address holding means and data read from the cell array by the address supplied from the control circuit and held in the current address holding means and held in the data holding means When but a possible transfer to the outside, the access reservation command Anda bank control circuit to be held in the data holding means more reserved address held in the reserved address holding portion to perform the reading of the data is held in the current address holding portion, the control circuit, Internally, address transfer from the reserved address holding means to the current address holding means, and from the first latch circuit to the second latch circuit are automatically performed internally for the bank from which data has been read from the cell array. It is possible to perform internal processing to start the next data read from the cell array, and the internal processing is performed by setting the next read address in the reserved address holding means by the access reservation command. After that, the automatic migration process reservation command that instructs the operation to automatically perform the above internal process is Referring to those the flag value the value of a preset the flag register is inputted to perform the process only if the predetermined value.

Preferably, when the data held in the data holding means can be transferred to the outside, the bank control circuit corresponding to each bank uses a control signal during a period in which data transfer from other banks is not performed to the outside. The held data is transferred from the data holding means to the outside via the bank switching circuit .

  Preferably, the bank control circuit corresponding to each bank reads data by the address held in the current address holding means, and until the data held by the data holding means can be transferred to the outside, A busy signal indicating a busy state in which read data transfer preparation is not ready is output to the outside, and the reserved address holding unit corresponding to each bank receives the reserved address from the outside even in the busy state. It can be received and held.

Preferably, the bank control circuit corresponding to each bank reads out data according to the address held in the current address holding means, and the data held in the data holding means can be transferred to the outside. to the external, to output a ready over signal indicating a ready state that could transfer preparation of the read data.

Preferably, the bank control circuit corresponding to each bank can transfer the data held in the data holding means to the outside, and after receiving the ready signal, receives a command for instructing the external transfer of data by the outside. When the data transfer from the other bank to the outside is not performed, the held data is transferred from the data holding means to the outside via the bank switching circuit by the control signal.

Preferably, the bank control circuit corresponding to each bank outputs the ready signal to the outside when the read data is held in the second latch circuit and can be transferred to the outside.

Preferably, when the read data is held in the second latch circuit and can be transferred to the outside, the bank control circuit corresponding to each bank outputs the ready signal to the outside, and externally transfers the data externally. When the command to be instructed is received, the data held in the second latch circuit is transferred to the outside via the bank switching circuit by the control signal during a period when data transfer from the other bank to the outside is not performed.

  Preferably, the information processing device further includes a status notification pin, and the notification pin becomes busy in response to an input of the reservation command, and becomes ready in response to execution of the internal processing in at least one of the banks.

  Preferably, the control circuit waits for the reservation to the flag register by the command input when the data is read from the cell array in any bank but the flag register is not reserved. The above internal processing is executed.

  Preferably, it has a status register that is accessible from the outside and stores the current operation status.

A signal processing system according to a second aspect of the present invention includes a first semiconductor memory device, a second semiconductor memory device from which stored data of the first semiconductor memory device is read, and the first and second semiconductors. A host device that controls access to the storage device and performs predetermined signal processing in accordance with data stored in the second semiconductor storage device; and a controller that controls an access request from the host device to the first semiconductor storage device. The first semiconductor memory device includes a cell array in which memory cells are arranged in a matrix, data is read according to an address, and a first latch that holds data read from the cell array The holding data of the first latch circuit is transferred to the circuit at a predetermined timing, and the second data holding the transferred data is transferred. Includes a latch circuit, the advance in accordance with the read data holding means that enables transfer of data to the external data to the second latch circuit is held, a plurality of banks including, input command value A flag register in which a flag value is set, a bank switching circuit for inputting / outputting data through a column selector selectively controlled by a column decoder from the second latch circuit, and any one of the plurality of banks When a bank is selected and the completion of access to the memory cell array is notified, a value set in the flag register is referred to, and a control circuit that outputs an access instruction for the selected bank is provided to each of the plurality of banks. Current address holding means for holding an address for reading the data of the cell array provided correspondingly, Accept even the reserved address by the access reservation command for the next read in advance from the outside without a reserved address holding portion capable of holding, the access instruction from the control circuit is supplied held in the current address holding portion When the data read from the cell array by the address and held in the data holding means can be transferred to the outside, the reserved address held in the reserved address holding means by the access reservation command is held in the current address holding means. A bank control circuit that causes the data holding means to read the data and hold the data in the data holding means, and the control circuit automatically and internally with respect to the bank that has completed the data reading from the cell array. From the reserved address holding means to the current address Address transfer to the address holding means, data transfer from the first latch circuit to the second latch circuit, and internal processing for starting the next data read from the cell array can be performed. Internal processing is set in advance when an automatic transfer processing reservation command for instructing an operation for automatically performing the internal processing is input after an address to be read next is set in the reserved address holding means by the access reservation command. Referring to those the flag value the value of the flag register and the processing is executed only when a predetermined value has.

According to the present invention, for example, by having a plurality of address holding means in the bank, the next address is held in advance in the reserved address holding means.
Data is read from the cell array according to the address held in the current address holding means and held in the data holding means.
When the read data can be transferred to the outside at a predetermined timing, the reserved address held in the reserved address holding unit is held in the current address holding unit.
This time, according to this address, data is read out and held in the data holding means.
Thereby, it becomes possible to access continuously in time series.

In addition, the flash memory has a plurality of banks, and enables high-speed data transfer by accessing in parallel. By having a plurality of address registers in each bank, it becomes possible to continuously access in time series.
Since each bank is operated in parallel, each bank can be accessed efficiently by having a ready signal / busy signal for each bank and handshaking with the outside.

According to the present invention, by having a plurality of stages of address holding means (registers) corresponding to the banks, it is possible to fetch in advance the address necessary for the next reading, and it is possible to continuously access in time series. Become.
In addition, by having a plurality of banks, high-speed reading is possible by making the random access time of reading apparently invisible.
Also, each bank can be controlled in parallel by controlling a pair of ready / busy signals corresponding to a plurality of banks.
Further, by providing a plurality of data holding means, it becomes possible to fetch data corresponding to the next address during the current reading.
Further, the read command and the read data output command can be separated, and the command can be issued to a plurality of banks.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the overall configuration of a signal processing system employing a semiconductor memory device according to the present invention.
In this embodiment, a NAND flash memory in which a memory string in which a plurality of memory cells are connected in series is connected to a bit line and a source line via a selection switch is employed as a semiconductor memory device.

  As shown in FIG. 1, the signal processing system 1 includes a NAND flash memory 2 as a first semiconductor memory device, a controller 3, a CPU 4 as a host device, a bridge circuit 5, and a second semiconductor memory device. For example, it has a DRAM 6.

In the signal processing system 1, the CPU 4 on the host side and the NAND flash memory 2 are connected via a controller 3.
An access request for reading (hereinafter referred to as reading) and writing (hereinafter referred to as writing) to the flash memory 2 from the CPU 4 is once accepted by the controller 3.
The controller 3 performs address conversion processing (mapping processing for converting a logical address designated by the CPU 4 into a physical address on the flash memory, logical / physical address conversion processing), error detection / correction processing for read data from the flash memory 2, and An error detection / correction code is added to the write data to the flash memory 2.

The signal processing system 1 utilizes the characteristics of the NAND flash memory 2, for example, and the NAND flash memory 2 is applied as a system OS program or application program storage or a storage of image or audio data.
In the signal processing system 1, the data stored in the NAND flash memory 2 is read at a high speed, for example, about 1 GB / s, at the time of power-on, forced reset, or system reset. The data is transferred to the DRAM 6 through the controller 3 and the bridge circuit 5 at high speed.
Thereafter, the CPU 3 can start the system at high speed by accessing the DRAM 6, and further performs various signal processing according to the application, such as image processing, sound processing, or display processing and sound output processing associated therewith. It can be carried out.

The flash memory 2 according to the present embodiment basically has a plurality of banks, and by issuing a unique command, the plurality of banks are accessed in parallel to enable high-speed data transfer.
By having a plurality of address registers (two in this embodiment) corresponding to each bank, continuous access in time series is realized.
Further, in order to operate each bank in parallel, a ready (RY) / busy (BY) signal, which is a signal for notifying the progress of the operation of the own bank, is issued to the controller 3 for each bank. By performing handshake with the bank, each bank is efficiently accessed.
In addition, a data register for storing data read from the cell array is provided in multiple stages (in this embodiment, two stages).
In addition, by storing the current operation status in the status register, a system that can grasp the operation status of each bank is realized.

  Hereinafter, a more specific configuration and function of the NAND flash memory 2 and the controller 3 according to the present embodiment will be mainly described.

FIG. 2 is a block diagram showing a configuration example of the NAND flash memory of FIG.
FIG. 3 is a block diagram showing a specific configuration example of the bank in FIG.

The flash memory 2 of FIG. 2 includes two address registers 203 (A-AD1) as address holding means provided corresponding to the two banks 201 (A) and 202 (B) including the cell array and the bank (A) 201. ), 204 (A-AD2), two address registers 205 (B-AD1), 206 (B-AD2) as address holding means provided corresponding to the bank (B) 202, a control system signal input / output unit 207, a data input / output unit 208, a command register 209, a control circuit 210 that controls access to the two banks 201 and 202, a first bank control circuit 211 that controls the bank (A) 201, and a bank (B) 202. Second bank control circuit 212 for controlling, status register 21 And a booster circuit 214, as principal components.
Of the address registers provided in a two-stage configuration, the subsequent address registers 204 and 206 constitute the current address holding means of the present invention, and the preceding address registers 203 and 205 constitute the reserved address holding means of the present invention. is doing.

As shown in FIG. 3, a bank (A, B) 220 (201, 202) includes a cell array 221 in which memory cells are arranged in a matrix, a row (row, page) decoder 222, a block address decoder 223, a word The first data latch circuit (DT1) 225 including the line decoder 224, the sense amplifier (S / A) and the data register arranged in a two-stage configuration on the data input / output side of the cell array 221, and the second data including the data register A latch circuit (DT2) 226, a column selector (Y selector) 227, and a column (column) decoder 228 are included.
Note that the first data latch circuit 225 and the second data latch circuit 226 constitute the data holding means of the present invention.

As shown in FIG. 4, the cell array 221 includes a memory string composed of a plurality of, for example, 16 memory transistors M0 to M15 connected in series and two select transistors ST0 and ST1 connected in series at both ends thereof. STRG00, STRG01, and STRG04223 are arranged in a matrix.
4 shows only one block BLK0 in which 4224 memory strings STRG00 to STRG04223 in 1 row 4224 columns are arranged for simplification of the drawing. A plurality (m) of blocks BLK1 to BLKm having the same configuration as that of the block BLK0 are further arranged.
In the example of FIG. 4, the number of bit lines is normally 528 bytes obtained by adding 16 spare bytes to 512 bytes, that is, 4224 lines.

The select transistor ST0 connected to the drain of the memory transistor M0 of the memory string STRG00 is connected to the bit line BL0, the drain of the memory transistor M0 of the memory string STRG01 is connected to the bit line BL1, and similarly the memory of the memory string STRG04223. The drain of the transistor M0 is connected to the bit line BL4223.
In addition, the select transistor ST1 to which the source of the memory transistor M15 of each memory string STRG00 to 04223 is connected is connected to a common source line SRL.

  Further, the gate electrodes of the memory transistors of the memory strings STRG00, STRG01 to STRG04223 arranged in the same row are connected to the common word lines WL0 to WL15, and the gate electrode of the selection transistor ST0 is connected to the common selection gate line DSG. The gate electrode of the selection transistor ST1 is connected to the common selection gate line SSG.

The row decoder 222 includes a transfer gate group 2221 whose conduction state is controlled by the block address decoder 223, word lines supplied from the word line decoder 224, and selection gate line drive voltage supply lines VCG0 to VCG15, VDSG, and VSSG. ing.
4 shows a block address decoder portion and a transfer gate group corresponding to the block BLK0 for simplification of the drawing, but actually, a block address decoder corresponding to a plurality of blocks (not shown) arranged. Partial and transfer gate groups are provided.

The transfer gate group 2221 includes transfer gates TW0 to TW15, TD0, and TS0.
The transfer gate group 2221 is generated in response to the block address decoded by the block address decoder 223, and is kept conductive by a signal BSEL for driving the selection gate line and the word line of the corresponding block.
Specifically, when the block BLK0 is addressed, the transfer gates TW0 to TW15 connect the word lines WL0 to WL15 and the drive voltage supply lines VCG0 to VCG15 according to the output signal BSEL0 of the block address decoder 223, respectively. Similarly, the transfer gates TD0 and TS0 operatively connect the selection gate lines DSG and SSG and the drive voltage supply lines VDSG and VSSG according to the output signal BSEL0 of the block address decoder 223.

  The block address decoder 223 responds to the control signals of the bank control circuits 211 and 212, and the addresses held in the subsequent address registers 204 and 206 among the address registers 203 and 204 and the address registers 205 and 206 connected in two stages. Then, in response to the decoded block address, the transfer gate group 2221 for driving the selection gate line and the word line of the corresponding block of the row decoder 222 is held in the conductive state by the signal BSEL.

  The word line decoder 224 is boosted by the booster circuit 214 according to the operation from the address held in the address registers 204 and 206 in response to a control signal indicating the read, write or erase operation of the bank control circuits 211 and 212. The generated drive voltages are generated on the drive voltage supply lines VCG0 to VCG15, VDSG, and VSSG, and supplied to the row decoder 222.

In the bank 220 (201, 202), the two-stage first data latch circuit 225 and second data latch circuit 226 are arranged between the cell array 221 and the column selector 227 as described above.
In the first data latch circuit 225 and the second data latch circuit 226, data holding and data transfer are controlled by bank control circuits 211 and 212 provided corresponding to each bank.
Specifically, reading of data from the cell array 221 is performed using the first data latch circuit 225 which is the previous stage at the time of reading. The data that has been read is temporarily input and held in the first data latch circuit 225 in the previous stage. Soon (at a predetermined timing), the data is transferred to and held by the second data latch circuit 226 at the subsequent stage under the control of the bank control circuits 211 and 212.
The data output transfer to the outside (controller 3) is a ready indicating that the bank control circuits 211 and 212 can transfer the read data of the own bank when the data is held in the second data latch circuit 226. When a signal is transferred to the controller 3 and an external transfer command issued by the controller 3 is received as a response, the second data latch circuit 226 follows the instructions of the bank control circuits 211 and 212 (in accordance with the control signal). The data is transferred to the outside through the column selector 227 selectively controlled by the column decoder 228 and through the bank switching circuit (multiplexer / demultiplexer) of the data input / output unit 208 of FIG.
Therefore, during the transfer period of the data held by the second data latch circuit 226, the first read operation from the cell array 221 is controlled using the first data latch circuit 225 in the previous stage.

At the time of data write, the second data latch circuit 226 functions as a preceding stage and the first data latch circuit 225 functions as a succeeding stage latch circuit, and the data of the second data latch circuit 226 is used as the succeeding first data latch circuit. The column control circuits 211 and 212 are continuously operated so that the next data is latched in the second data latch circuit 226 during the period in which the data transferred to and held in the cell array 221 is written in the cell array 221. This controls the data write of its own column.

FIG. 5 is a diagram illustrating a configuration example of a data transfer path between the bit line of the cell array 221 and the column selector 227 in the bank.
In the bank 220 (201, 202), as shown in FIG. 5, between each bit line BL (0-4223) and the first data latch circuit (DT1) 225, the first data latch circuit 225 and the second data. Switches SW1, SW2, and SW3 including MOS transistors that are turned on and off by a control signal are disposed between the latch circuits 226 and between the second data latch circuit 226 and the column selector 227.
By performing on / off control of these switches SW1, SW2, and SW3 at predetermined timings by the column control circuits 211 and 212, data transfer at the time of reading and writing described above is performed.

In the circuit shown in FIG. 5 , the source / drain of an n-channel MOS transistor (NMOS) NT1 is connected between the bit line BL and the switch SW1, and a p-channel MOS (between the connection node ND1 and the power supply potential Vcc is connected. The PMOS transistor PT1 has its drain and source connected, the NMOS transistor NT1 is supplied with a high level active signal RDC, and the PMOS transistor PT1 has a low level active signal / PRE (/ is a level). Is shown).
The switches SW1 to SW3 are constituted by, for example, PMOS transistors, and are turned on / off by low level active signals / SEN1 to / SEN3 supplied at a predetermined timing.

6A to 6D are timing charts of the circuit of FIG. 5 at the time of reading.
In the circuit of FIG. 5, when data is read, first, as shown in FIG. 6A, the precharge signal / PRE is supplied to the gate of the PMOS transistor PT1 at a low level for a predetermined period. As a result, the PMOS transistor PT1 becomes conductive, and the node ND1 is precharged to the power supply potential Vcc.
As shown in FIGS. 6B and 6C, the read control signal RDC is supplied to the gate of the NMOS transistor NT1 at a high level for a predetermined period, and the first switch control signal / SEN1 is active at a low level for a predetermined period. Is supplied to the switch SW1. As a result, the NMOS transistor NT1 is turned on, the switch SW1 is turned on, and the read data of the bit line BL is transferred to the first data latch circuit 225. Thereafter, the read control signal RDC is switched to the low level, the first switch control signal / SEN1 is switched to the high level, and the NMOS transistor NT1 and the switch SW1 are turned off.
After the read data is transferred to the first data latch circuit 225 in this way, the second switch control signal / SEN2 is supplied to the switch SW2 at a low level for a predetermined period as shown in FIG. 6D. . As a result, the switch SW2 is turned on, and the read data held in the first data latch circuit 225 is transferred to the second data latch circuit 226.
As described above, when the data is held in the second data latch circuit 226, the bank control circuits 211 and 212 transfer a ready signal indicating that the read data of the own bank can be transferred to the controller 3. When the external transfer command issued by the controller 3 is received as a response, the third switch control signal / SEN3 is supplied to the low-level switch SW3 for a predetermined period as shown in FIG. From the second data latch circuit 226 to the second data latch circuit 226 through the column selector 227 selectively controlled by the column decoder 228, through the bank switching circuit (multiplexer / demultiplexer) of the data input / output unit 208 of FIG. It is transferred to the controller 3.
During the transfer period of the data held by the second data latch circuit 226, as shown in FIG. 6A, the precharge signal / PRE is supplied to the gate of the PMOS transistor PT1 at a low level for a predetermined period. As a result, the PMOS transistor PT1 becomes conductive, and the node ND1 is precharged to the power supply potential Vcc.
As shown in FIGS. 6B and 6C, the read control signal RDC is supplied to the gate of the NMOS transistor NT1 at a high level for a predetermined period, and the first switch control signal / SEN1 is active at a low level for a predetermined period. Is supplied to the switch SW1. In other words, during the period in which data is transferred from the second data latch circuit 226 to the outside, the first read operation from the cell array 221 is controlled using the first data latch circuit 225 in the previous stage.

FIG. 7 is a diagram illustrating another configuration example of the data transfer path between the bit line of the cell array 221 and the column selector 227 in the bank.
While the example of FIG. 5 is configured to provide a latch circuit for each bit line, the data transfer path system of FIG. 7 is configured to share two types of latches for each bit line.
The first data latch circuit 225A includes a sense amplifier S / A, and the second data latch circuit 226A functions as a write buffer and a read buffer.
.. Are connected in series between one end of the even bit lines BL0, BL2,... And connected to one end of the odd bit lines BL1, BL3,. The switches SW13 and SW14 are connected in series, and the connection point between the switch SW11 and the switch SW12 in the even column and the connection point between the switch SW13 and the switch SW14 in the odd column are directly connected. A switch SW15 is arranged between the connection point between the switch SW14 and the input / output terminal of the second data latch circuit 226A and the transfer line on the column selector 227 side.

In the circuit of FIG. 7, for example, in the even column data read, the switches SW11 and SW12 are turned on to be transferred and held in the first data latch circuit 225A, the switch SW11 is turned off, and the switches SW12 and SW14 are turned on. As described above, data is transferred from the first data latch circuit 225A to the second latch circuit 226A.
Then, turning off the switch SW14, a switch SW13, SW12 ON, and turns on the switch SW 15, is held by transferring data of the odd columns to the first data latch circuit 225A, the second latch circuit 226A The read data of the even-numbered column transferred previously is transferred (output) to the column selector 227 side.
By controlling as described above, the number of data latch circuits can be reduced, and the time lag at the time of page switching can be minimized.

  In the bank 220 having such a configuration, for example, data reading from the memory transistor M14 in the memory string STRG00 (to TRG04223) of the block BLK0 in the first row and data writing to the memory transistor M14 are performed as follows. .

At the time of reading, as shown in FIG. 8, the ground voltage GND (0 V) is supplied to the drive voltage supply line VCG14 by the word line decoder 224, and the drive voltage supply lines VCG0 to VCG13, VCG15 and the drive voltage supply lines VDSG, VSSG 4.5 V is supplied, and the ground voltage 0 V is supplied to the source line SRL.
Then, in the block address decoder 223, an active address signal is input only to a portion corresponding to the block BLK0, and an output signal BSEL0 of the block address decoder 223 is output at a level of 4.5V + α, to the other blocks BLK1 to BLKm. Output signals BSEL1 to BSELm of the corresponding block address decoder are held at the ground voltage GND level.
Thereby, transfer gates TW0 to TW15, TD0, and TS0 of transfer gate group 2221 corresponding to block BLK0 are turned on, and transfer gates of transfer gate groups corresponding to other blocks BLK1 to BLKm are held in a non-conductive state. .
As a result, the select transistors ST0 and ST1 of the memory string STRG00 are turned on, and data is read to the bit line BL0.

At the time of writing, as shown in FIG. 9, a high voltage, for example, 20V is supplied to the drive voltage supply line VCG14 selected by the word line decoder 224, and an intermediate voltage (for example, 10V) is supplied to the drive voltage supply lines VCG0 to VCG13, VCG15. The power supply voltage V _CC (for example, 3.3 V) of the drive voltage supply line VDSG and the ground voltage GND (0 V) are supplied to the drive voltage supply line VSSG.
Further, the ground voltage GND is connected to the bit line BL0 to which the memory string STRG00 having the memory transistor M14 to be written is connected, and the bit line BL1BL04223 to which the memory strings STRG01 to STRG04223 having the memory transistor M14 to be prohibited from writing are connected to the power source. A voltage V _CC is applied.
The output signal BSEL0 of the block address decoder 223 is output at a level of 20V + α only in the portion corresponding to the block BLK0 of the row decoder 222, and the output signals BSEL1 to BSELm of the block address decoders corresponding to the other blocks BLK1 to BLKm are It is output at the ground voltage GND level.
Thereby, transfer gates TW0 to TW15, TD0, and TS0 of transfer gate group 2221 corresponding to block BLK0 are turned on, and transfer gates of transfer gate groups corresponding to other blocks BLK1 to BLKm are held in a non-conductive state. .
As a result, the write voltage 20V is applied to the selected word line WL14, and the pass voltage (intermediate voltage) Vpass (for example, 10V) is applied to the unselected word lines WL0 to WL13, WL15.

As a result, the select transistor ST0 of the memory strings STRG01 to STRG04223 is cut off, and the channel portions of the memory strings STRG01 to STRG04223 to which the memory transistors to be inhibited from writing are connected are in a floating state. As a result, the potentials of these channel portions are boosted mainly by capacitor coupling with the pass voltage Vpass applied to the non-selected word lines, rise to the write inhibit voltage, and are applied to the memory transistor M14 of the memory strings STRG01 to STRG04223. Data writing is prohibited.
On the other hand, the channel portion of the memory string STRG00 to which the memory transistor to be written is connected is set to the ground voltage GND (0V), and due to the potential difference with the write voltage 20V applied to the selected word line WL14, the channel to the memory transistor M14 is set. Data is written and the threshold voltage shifts in the positive direction, for example, from -3V to 2V in the erased state.

  As described above, the NAND flash memory 2 according to this embodiment corresponds to the address stored in the subsequent stage address register 204 or the address register 206 among the address registers connected in two stages. Data is read from the cell array 221 of the banks 201 and 202 in units of rows (pages).

That is, one set of address registers 203 and 204 and one set of address registers 205 and 206 are arranged corresponding to each bank 201 and 202.
The address value by the external controller 3 input through the control signal input / output unit 207 is first held in the previous address registers 203 and 205, and then transferred and stored in the subsequent address registers 204 and 206. One is decoded and used to read the cell array.
That is, the flash memory 2 according to the present embodiment is configured such that in addition to the current read address, an address for the next read is previously received from the outside and held.
In writing, data transferred and stored in the subsequent address registers 204 and 206 are decoded and used for writing the cell array. However, in the present embodiment, read processing is described, and a specific description of write processing is omitted.

  As shown in FIG. 2, the control system signal input / output unit 207 includes a ready (RY) / busy (BY) signal output unit 2071 on the bank (A) 201 side and a ready (RY) / on the bank (B) 202 side. It has a busy (BY) signal output unit 2072, a command / address control (CMD / ADR) unit 2073 for inputting a command / address, and an operation logic control unit 2074 for inputting a control signal.

The flash memory 2 according to the present embodiment includes a plurality of (for example, two) banks 201 and 202, and the output units 2071 and 2072 assigned one-to-one to the banks 201 and 202 are ready (RY). / Busy (BY) signal output pins (terminals) P2071 and P2072 are connected.
The RY / BY pins P2071 and 2072 corresponding to the banks 201 and 202 reflect the progress status of the command requested to the bank, and the status of the bank is set to be ready or busy. It shows.
For example, ready is defined as a high potential (power supply potential Vcc), and busy is defined as a low potential (ground potential).
In particular, in the flash memory 2 of the present embodiment, in the read operation, when the preparation of the data requested to be read is completed and the transfer command for outputting the data is accepted, the RY / BY pin P2071. , P2072 is set to high level, and the ready signal RY is transferred to the external controller 3.
In the read operation, while the preparation of the data requested to be read is not completed and the transfer command for outputting the data is not accepted, the RY / BY pins P2071 and P2072 are set to the low level, The busy signal BY is transferred to the external controller 3.

A command / address control (CMD / ADR) unit 2073 for inputting a command / address inputs a command such as a read command RD, a write command WR, and an address to be read or written, and inputs the command into a command register 209 and a control circuit. 210, the address is supplied to the address registers 203 and 205 and the control circuit 210 in the previous stage.
The command / address control unit 2073 is connected with a plurality of input pins PCA 2073 for inputting a command CMD transferred from the controller 3 and an address.
As described above, only the input pin is connected to the command / address control unit 2073.

An operation logic control unit 2074 for inputting a control signal supplies a control system signal such as a chip enable signal / CE, a read enable signal / RD, or a write enable signal / WE to the control circuit 210 and the command / address control unit 2073. To do.
A plurality of input pins PL 2074 for inputting control system signals transferred from the controller 3 are connected to the operation logic control unit 2074.
As described above, only the input pin is connected to the operation logic control unit 2074.

  In the control system signal input / output unit 207 of this embodiment, no data input / output system is arranged, and the output system is also a 1-bit ready (RY) / busy (BY) signal output pins (terminals) P2071 and P2072. Only.

The data input / output unit 208 includes a multiplexer (MPX) / demultiplexer (DeMPX) 2081 and an input / output (I / O) buffer 2082.
The I / O buffer 2082 is connected to a plurality of data pins PD 2082 for outputting read data to the controller 3 and inputting write data from the controller 3.
The plurality of data pins PD2082 are connected to a data line shared with the controller 3 by a plurality of banks, in this embodiment, the bank (A) 201 and the bank (B) 202.
The multiplexer / demultiplexer 2081 reads the read data transferred from the second data latch circuit 226 of the bank (A) 201 through the column selector 227 and the column from the second data latch circuit 226 of the bank (B) 202 at the time of reading. The read data transferred through the selector 227 is switched at a predetermined timing, for example, under the control of the control circuit 210 or the column control circuits 211 and 212, and selectively input to the I / O buffer 2082.

As described above, in the control system signal input / output unit 207 and the data input / output unit 208, which are interfaces (I / F) with the controller 3, the data lines and other signal lines (command / address and control system signals). Etc.).
This enables the next command / address exchange, etc., even during the data transmission / reception period. In addition, an I / F having high-speed physical characteristics can be employed only for the data line.

  The command register 209 holds the command supplied from the command / address control unit 2073 and supplies it to the control circuit 210.

The control circuit 210 decodes the control signal supplied from the operation logic control unit 2073 and the command supplied from the command register 209, performs processing such as enabling the entire flash memory 2, and is instructed by the command. It is determined whether the access (for example, read) is to access the bank (A) 201 or the bank (B) 202, and the bank control circuit 211 or 212 in charge is instructed.
In addition, the control circuit 210, depending on the command, specifically, as described above, the voltage to be supplied to the drive line at the time of reading or writing is different, so the voltage to be boosted to become the voltage according to the command To the booster circuit 214.

When the control circuit 210 notifies the bank (A) 201 that the bank control circuit 211 is, for example, a read, the bank control circuit 211 performs predetermined control of the block address decoder 223, the word line decoder 224, and the column decoder 228 of the bank 201, and The data transfer timing of the first data latch circuit 225 and the second data latch circuit 226 is controlled.
The bank control circuit 211 generates a ready (RY) / busy (BY) signal reflecting the command progress state of the bank 201 and notifies the external controller 3 of the ready (RY) / busy (BY) signal.

When the control circuit 210 informs the bank (B) 202 of, for example, a read, the bank control circuit 212 performs predetermined control of the block address decoder 223, word line decoder 224, column decoder 228 of the bank 202, and The data transfer timing of the first data latch circuit 225 and the second data latch circuit 226 is controlled.
Further, the bank control circuit 212 generates a ready (RY) / busy (BY) signal reflecting the command progress state of the bank 202 and notifies the external controller 3 of the ready (RY) / busy (BY) signal.

As described above, the control circuits 210, 211, and 212 for controlling the banks 201 and 202 exist in the flash memory 2 of the present embodiment.
Then, the command, bank address, block address, and page address specified by the external controller 3 can be decoded under the control of the control circuits 210, 211, and 212, and the respective banks can be operated simultaneously in parallel. Also, a ready (RY) / busy (BY) signal reflecting the command progress status of each bank 201, 202 can be generated and notified to the outside.

In addition, the bank control circuits 211 and 212 store in the status register 213 information that collectively reflects the operation status of the banks 201 and 202.
For example, if the controller 3 accesses the status register 213, the status of the entire chip of the flash memory 2 can be grasped.

In accordance with an instruction from the control circuit 210, the booster circuit 214 generates a voltage by boosting the power supply voltage VCC in accordance with, for example, a read command and supplies it to the row decoder 222, the word line decoder 224, etc. of the bank 201 or 202.
For example, at the time of reading, as described above, since a voltage of 4.5V is necessary, the voltage is increased from 3.3V to 4.5V.
Further, at the time of writing, as described above, 20V and an intermediate voltage of 10V are necessary, so that the voltage is boosted to 20V and 10V.

Next, a more specific configuration and function of the controller 3 will be mainly described.
FIG. 10 is a block diagram illustrating a specific configuration example of the controller 3 according to the present embodiment.

  The controller 3 includes an I / F unit 301 compliant with a communication protocol on the flash memory 2 side, an I / F unit 302 compliant with a communication protocol on the host (bridge) side, a memory access control circuit 303, and an error detection / correction circuit 304. , A flash I / F side FIFO 305, and a host (bridge) side FIFO 306 as main components.

  The flash side I / F unit 301 includes an I / O buffer 3011 for inputting / outputting data, an output buffer 3012 for outputting a control signal and a command / address to the flash memory 2, and RY (ready) by the flash memory 2. An input buffer 3013 for inputting a signal / BY (busy) signal is provided.

A plurality of data pins PD3011 for inputting read data transferred from the flash memory 2 and outputting write data from the controller 3 are connected to the I / O buffer 3011.
The plurality of data pins PD3011 are connected to the plurality of data pins PD2082 of the data input / output unit 208 of the flash memory 2 via data lines shared by the bank (A) 201 and the bank (B) 202.
In the controller 3, the I / O buffer 3011 exchanges data with the flash I / F side FIFO 305.

The output buffer 3012 outputs a control signal and command / address from the memory access and control circuit 303, and is connected to a plurality of control pins PL3012 for outputting the control signal and command / address, and a command / address pin PCA3012. ing.
The plurality of control pins PL 3012 are connected to the plurality of control pins PL 2074 of the operation logic control unit 2074 in the control system signal input / output unit 207 of the flash memory 2.
The plurality of command / address pins PCA 3012 are connected to the command / address pins PCA 2073 of the command / address logic control unit 2073 in the control system signal input / output unit 207 of the flash memory 2.

The input buffer 3013 inputs a ready (RY) / busy (BY) signal from the flash memory 2 to the memory access control circuit 303, and the input buffer 3013 has an input pin for a ready (RY) / busy (BY) signal ( Terminals) P3013A and P3013B are connected.
These ready (RY) / busy (BY) signal input pins (terminals) P3013A and P3013B are used for the ready (RY) / busy (BY) signal of the output unit 207 in the control system signal input / output unit 207 of the flash memory 2. It is connected to output pins (terminals) P2071 and P2072.

  The I / O buffer 302 includes a high-speed I / F corresponding to the CPU side, that is, the host (bridge) side, a plurality of data input / output pins PD302 for inputting / outputting data to / from the bridge circuit 5, and a command / address Are connected to an input pin PCA302 for inputting the control signal and an input / output pin PL302 for inputting / outputting a control signal.

  The memory access / control circuit 303 performs interleave control, command control, and address designation (bank block page), and outputs control signals, commands and addresses to the flash memory 2 by the output buffer 3012, and the flash I / F side FIFO. The flash I / F controller 3031 that controls the data I / O of the host, the host I / F controller 3032 that performs the request processing with the host and controls the data I / O of the host I / F FIFO, and the address conversion It has an address conversion table 3033 for performing processing (mapping processing for converting a logical address designated by the host into a physical address on the flash memory, logical / physical address conversion processing).

  The error detection / correction circuit 304 performs error detection / correction processing for read data from the flash memory 2 and addition of error detection / correction codes for write data to the flash memory 2.

The flash I / F side FIFO 305 and the host (bridge) I / F side FIFO 306 are arranged on the flash memory side I / F and the host (bridge) side 1 / F, respectively, in order to ensure the consistency of data flow timing. is doing.
The flash I / F side FIFO 305 and the host (bridge) I / F side FIFO 306 are constituted by, for example, an SRAM or the like.

Here, the read operation sequence of the flash memory 2 according to the present embodiment will be described with reference to FIGS.
Here, an operation sequence between the controller 3 and the flash memory 2 will be described.

<Read operation sequence of flash memory>
As shown in FIG. 11A, the controller 3 issues a command for internal reading of the bank (A) 201 and address 0 through the control system pin PL 3012. This address value is stored in the address register (A-AD2) 204 via the input pin PCA 2073 via the address register (A-AD1) 203 as shown in FIGS.
The address value stored in the address register (A-AD2) 204 is decoded, and the internal read of the address 0 of the cell array 221 in the bank (A) 201 is started.
In parallel with this, as shown in FIG. 11C, the RY / BY-A signal is changed to a busy state by the bank controller 211.

This “busy” indicates a state where preparation for transferring data 0 stored in the cell array: bank (A) 201, address 0 to the outside is not yet completed.
Here, as shown in FIG. 11A, even when the internal read of the bank A is being executed, the command for reserving the bank (A) and address 2 as the location of the next internal read is Can be issued from 3.
When this is issued, the address value is stored in the address register (A-AD1) 203 for the time being as shown in FIG.
Here, since the internal reads of the bank (A) 201 and the bank (B) 202 can operate simultaneously in parallel, a command for performing an internal read of the bank (B) 202 and address 1 is issued.
Interleave operation is possible between different banks.

This address value is stored in the address register (B-AD2) 206 via the address register (B-AD1) 205 as shown in FIGS.
The address value stored in the address register (B-AD2) 206 is decoded, and the internal read of the address 1 of the cell array 221 in the bank (B) 202 is started.
In parallel with this, as shown in FIG. 11D, the RY / BY-B signal is changed to the busy state by the bank controller 212.
This “busy” indicates a state in which data 1 stored in the cell array: bank B, address 1 is not yet ready to be transferred to the outside.
Similarly, as shown in FIG. 11A, even if the internal read of the bank (B) 202 is being executed, the bank (B) 202, which is the location of the next internal read, and the address 3 are set. A command to reserve can be issued from the controller 3.
When this is issued, the address value is stored in the address register B-AD1 for the time being.

  If the internal read of the bank (A) 201 and address 0 is determined by the operation of the sense amplifier (S / A), as shown in FIG. 1 is stored in the data latch circuit (A-DT1) 225, and the process ends.

Shortly thereafter, as shown in FIGS. 11G and 11H, the data stored in the first data latch circuit (A-DT1) 225 is transferred to the second data latch circuit (A-DT2). 226.
Then, as shown in FIG. 11C, the RY / BY-A signal is changed to a ready state by the bank controller 211.
This “ready” indicates that the data 0 stored in the cell array: bank (A) 201 and address 0 is stored in the second data latch circuit (A-DT2) 226, and is ready to be transferred to the outside. It shows that it became the state.

In parallel with this, the address value stored in the address register (A-AD1) 203: address 2 (value reserved for the next read of the bank A) is transferred to the address register (A-AD2) 204. This value is decoded, and the internal read of the address 2 of the cell array 221 of the bank (A) 201 is started again.
Interleave operation is possible in the same bank.

  In response to the RY / BY-A signal becoming ready, the controller 3 performs external transfer of data stored in the bank (A) 201 and the second data latch circuit (A-DT2) 226. Issue the command to be performed.

In response to this command, the flash memory 2 switches the bank 0: the data stored in the bank (A) 201 and the second data latch circuit (A-DT2) 226: data 0 after a certain short delay time (latency). The data is transferred to the controller 3 through the circuit and the data line.

  Even during the data transfer through this data line, the address register (A-AD1) 203 is in an “empty” state, and the control system pins are also in an “empty” state. As shown in FIG. 4, a command for reserving the bank (A) 201 and address 4 as the location of the next internal read can be issued from the controller 3 to the flash memory 2.

  If the internal read operation of bank (B) 202 and address 1 during this time is completed (data 1 is confirmed and stored in data register (B-DT1) 205), bank (B ) 202, the same internal operation and access from the controller 3 are executed as in the case of the bank (A) 201.

  Similarly, interleave operation between banks and interleave operation within banks can be combined to continuously extract data stored in the cell array to the outside without interruption.

  12A shows a transfer sequence of the flash memory of the present invention provided with two address registers, and FIG. 12B shows a transfer sequence of the flash memory provided with only one address register.

In a flash memory having only one address register, the host side receives a ready signal, makes a determination thereof, then issues an address, and the flash memory performs an internal read accordingly, in other words, Since an internal operation is started with a user command accompanied by an address input as an event, the host-side determination, latency, and command transmission cycle are forced to lengthen the transfer cycle.
In contrast, the flash memory according to the present invention has a function of starting an internal operation by fetching address data from the address reservation registers 203 and 205 using an internal signal as an event. As shown, data stored in the cell array can be continuously extracted to the outside without interruption.

The following can be adopted as a method for terminating a series of internal reads and external transfers.
-Instead of entering the address of the next lead reservation, enter an end code or an end command.
-If the address of the next read reservation is not entered, the data will be transferred automatically and then terminated automatically.
・ Even if the address of the next read reservation is set, it is forcibly returned to the initial state by inputting a reset command.

  As described above, according to the present embodiment, the current address registers 204 and 206 that are provided corresponding to each of the plurality of banks 201 and 202 and hold the address for reading the data of the cell array, and the next time A reserved address for reading is received from the outside in advance, and is read from the cell array of the bank by the addresses held in the reserved address registers 203 and 205 and the current address registers 204 and 206, and held in the data latch circuit. When the transferred data can be transferred to the outside, the bank control circuit 211 causes the reserved address held in the reserved address registers 203 and 205 to be held in the current address registers 204 and 206 to be read out and held in the data latch circuit. , 212 and the following Effect can be obtained.

By having a plurality of banks, high-speed reading is possible by making the random access time of reading apparently invisible.
Further, by controlling the RY / BY signal for each bank, the banks can be controlled in parallel.
Further, by providing a plurality of address registers for each bank, an address necessary for the next read can be fetched in advance.
Further, by providing a plurality of data latches, it is possible to fetch data corresponding to the next address during the current reading.
Further, by separating the read command and the read data output command, it is possible to issue a command to a plurality of banks.

Further, since the controller 3 has an error detection / correction processing circuit, it is possible to reduce the host-side processing by performing error detection / correction processing of read data from the flash memory.
In addition, by having a FIFO in the controller 3, it is possible to maintain consistency in data flow timing between the flash memory side and the host side.

In the above description, in the read operation, the flash memory 2 completes the preparation of the data requested to be read and when the transfer command for outputting the data is accepted, the RY / BY pin P2071, P2072 in the high level, to transfer the ready signal RY to the external controller 3, the read operation, without preparing the data for which the read request is completed, in order to output the data transfer instruction Is not accepted, the RY / BY pins P2071 and P2072 are set to low level so that the busy signal BY is transferred to the external controller 3 so that the banks are connected in parallel. it is controllable, but the present invention is not limited to this control method.

  For example, as shown in FIG. 13, in the flash memory 2A in which the data transfer and the internal memory cell array access operation are pipelined, when the access operation is completed, the stage is automatically shifted and the next access operation is started. The stage is automatically transferred by referring to the value of the flag register set by the reservation command, and the external notification pin is changed to the first state by the reservation command and changed to the second state when the stage transition processing is completed. It is also possible to configure.

  FIG. 13 is a block diagram showing a configuration example of a flash memory 2A provided with this stage automatic transition mechanism.

  In FIG. 13, the flag register 230 is connected to a command register 209, a control circuit 210A, and an output unit 2071 for a ready (RY) / busy (BY) signal.

When notified of the completion of access to the memory cell array 221 from the first bank control circuit 211 or the second bank control circuit 212 as the access controller, the control circuit 210A refers to the reserved value set in the flag register 230, If the value is “1”, the following processing is performed to return the value to “0”.
That is, when data is read, the data group stored in the data register 224 in FIG. 3 is transferred to the output data register 226.
Further, the column address value in the address stored in the address register 204, 206 is stored in the column address register, and then the address value of the reservation address register 203, 205 is transferred to the address register 204, 206.
Further, as an access controller, an access instruction is sent to the first bank control circuit 211 or the second bank control circuit 212 to start the next load operation of the memory cell array 221.
Further, the ready (RY) / busy (BY) signal output unit 2071 including the register connected to the external notification pin P2071 is set to “1”, and the notification pin P2071 is set to the ready (REDY) state.

  On the other hand, if the flag register 230 is in an unreserved state, that is, “0”, the control circuit 210A does not perform stage transition processing and waits while maintaining the current state where access has been completed. Then, for example, after waiting for the flag register reservation setting, the stage transition is executed.

The flag register 230 is reserved as follows.
That is, according to the command value input to the command register 209, it is set to “1” when it is a specific value. At the same time, the ready (RY) / busy (BY) signal output unit 2071 including the register is set to "0", and the notification pin P2071 enters the BUSY state.

14A to 14D are diagrams showing an example of a data read operation from a single bank of such a flash memory 2A.
14A to 14C, hatched lines indicate the stage transition period in the pipeline operation. 14A shows a command and address input (R1), FIG. 14B shows an internal memory cell array read (R2), FIG. 14C shows a data output (R3), and FIG. ) Indicates a ready (RY) / busy (BY) signal, respectively.

1. When the read command and address input (21) for the first access <1> are completed, the access <1> immediately shifts to the read stage (R2) of the memory cell array.
That is, address transfer (22) from the reservation address register 203 (or 205) to the address register 204 (or 206) is performed, and reading (23) of the internal memory cell array 221 is started.

2. Here, during the internal read operation, the reservation command is input (24) for the next access <2>, and the page address to be read next is set in the address register 203 (or 205).

3. Further, when the reservation command (25) for the stage automatic transition processing is input, the external notification signal (26) transitions to the busy (BUSY) state accordingly. Further, “1” is set in the flag register 230. A command serving both as the access reservation command (24) and the automatic migration process reservation command (25) may be provided. In this case, both can be reserved by a single command input.

4). When the internal reading (23) of the access <1> is completed, automatic stage transition (27) is performed. That is, the value of the address register 203 (or 205) is transferred to the address register 204 (or 206), the data of the data register 225 is transferred to the data register 226, and the internal reading (28) of the access <2> is automatically started. The Further, the external notification signal (26) transitions to the REDY state.

5). The controller 3 or the host device 4 detects and determines the ready (REDY) state, and starts the data output (29) of the access <1>.

6). At the end of access, only the command (30) for automatic migration processing is input. Accordingly, the external notification signal (26) transits to the busy (BUSY) state, and “1” is set in the flag register 230.

7). When the internal reading of the access <2> is completed, automatic stage shift (31) is performed. That is, the value of the address register 203 (or 205) is transferred to the address register 204 (or 206), and the data of the data register 225 is transferred to the data register 226. However, when no access reservation is made, the next internal read is not performed based on a separately set register or the like. The external notification signal (26) transitions to the ready (REDY) state.

8). The controller 3 or the host device 4 detects and determines the ready (REDY) state, and starts the data output (32) of the access <2>.

  In the above processing, continuous processing is continuously performed in the internal memory access stage (R2). However, this stage is still a bottleneck of the entire processing. For example, the data transfer stage (R3) is only intermittent. Not working.

  In the following, description will be made with reference to FIGS. 15A to 15D, in which the internal memory access stage is branched into a plurality of stages and parallel processing is performed to enable faster data access.

In this example, it is assumed that each bank performs the same operation by changing only the address and data, and a memory access controller and a control circuit as a stage transition circuit are shared by a plurality of banks. In this case, the processing of each branched stage and the transition to the next stage are performed at the same timing for all banks.
This is one of the simplest embodiments in which a multi-bank configuration is introduced in the present invention, and various other variations may exist in the operation of a plurality of banks, as will be described later.
In this case, when the controller 210A is notified by the first bank control circuit 211 or the second bank control circuit 212 as an access controller that the memory cell arrays 221 of all banks have been accessed, the controller 210A sets the flag register 230. The reserved value is referred to, and if the value is “1”, the following processing is performed to return the value to “0”.

That is, at the time of data reading, for example, the following operation performed on the bank 201 is similarly performed on each bank.
Transfer the data group stored in the data register 225 to the output data register 226.
Further, the column address value in the address stored in the address register 204 is stored in the column address register, and then the address value of the reservation address register 203 is transferred to the address register 204.
When the above operations are completed for each bank unit,
Further, an access instruction is sent to the first bank control circuit 211 as an access controller to start the next read operation for the memory cell array 221 in each bank.
Further, the ready (RY) / busy (BY) signal output unit 2071 including the register connected to the external notification pin P2071 is set to “1”, and the notification pin P2071 is set to the ready (REDY) state.

  On the other hand, when the flag register 230 is in an unreserved state, that is, “0”, the control circuit 210A does not perform stage transition processing and waits while maintaining the current state where the access is completed. Then, for example, after waiting for the reservation setting of the flag register 230, the transition of the above stage is executed.

The flag register 230 is reserved as follows.
That is, according to the command value input to the command register 209, it is set to “1” when it is a specific value. At the same time, the ready (RY) / busy (BY) signal output unit 2071 including the register is set to "0", and the notification pin P2071 is set to the busy (BUSY) state.

FIGS. 15A to 15D are diagrams showing examples of data read operations from a plurality of banks of such a flash memory 2A.
15A to 15C, hatched lines indicate the stage transition period in the pipeline operation. Further, FIG. 15 (A) input of a command and address (R1), FIG. 15 (B) is in the internal memory cell array read (R2), FIG. 15 (C) data output (R3), FIG. 15 (D ) Indicates a ready (RY) / busy (BY) signal, respectively.
In this example, a two-bank configuration is assumed as shown in FIG. 13, and access <1> and <3> are processed by bank 201 and access <2> and <4> are processed by bank 202, respectively.

1. When the read command and address input (41) for the first access <1> and <2> are completed, the access <1> and <2> immediately shift to the read stage (R2) of the memory cell arrays 201 and 202.
That is, in each bank, address transfer (42) from the reservation address registers 203 and 205 to the address registers 204 and 206 is performed, and reading (43) and (44) of the internal memory cell array 221 is started.

2. Here, during the internal read operation, a reservation command is input (45) for the next access <3>, <4>, and the page address to be read next is stored in the reservation address registers 203, 205 of each bank. Set.

3. Further, when a reservation command (46) for automatic stage transition processing is input, the external notification signal (56) transitions to a busy (BUSY) state accordingly. Further, “1” is set in the flag register 230. Note that a command serving both as the access reservation command (45) and the automatic migration process reservation command (46) may be provided. In this case, both can be reserved by a single command input.

4). When the internal leads (43) and (44) for the accesses <1> and <2> are both completed, automatic stage transition (47) is performed. That is, in each of the banks 201 and 202, transfer is performed between the address registers 203 and 204, between 205 and 206, and between the data registers 225 and 226, and internal reads (48) (48) ( 49) starts automatically. Further, the external notification signal (56) transits to the ready (REDY) state.

5). The controller 3 or the host device 4 detects and determines the ready (REDY) state, and sequentially executes the data output (50) and (51) of the access <1> and <2>.

6). At the end of access, only the reservation command (52) for automatic migration processing is input. Accordingly, the external notification signal (56) transits to a busy (BUSY) state, and “1” is set in the flag register 230.

7. When the internal readings (48) and (49) of the accesses <3> and <4> are both completed, automatic stage transition (53) is performed. That is, in each of the banks 201 and 202, transfer is performed between the address registers 203 and 204, between 205 and 206, and between the data registers 225 and 226. However, when no access reservation is made, the next internal read is not performed based on a separately set register or the like. The external notification signal (56) transitions to the REDY state.

8). The host detects and determines the REDY state, and starts data output (54) and (55) for accesses <3> and <4>.

In this way, especially for multi-bank operation, a wide variety of combinations can be considered. However, the above-described embodiment is accompanied by the pipelined memory access.
・ Command reservation for the above stage transition,
・ External notification when the above stage transition occurs,
・ Combination with multi-bank processing
The specific utilization example regarding the configuration requirements of the present invention is described together with the effect on the efficiency of data access at that time, and the present invention does not depend on the variation of the achievement means described here.

Further, the present invention is not limited to a flash memory, and can be applied to any semiconductor memory having a slow random access at the memory cell level.
In recent years, inexpensive new material semiconductor memories such as non-volatile memories using organic ferroelectric materials have been proposed, but some of them have a low memory cell access speed and are similar to NAND flash memories. Attempts have been made to cover it with parallel processing. The present invention can be effectively applied to such a semiconductor memory.

As described above, in the case of a storage device adopting the configurations and functions shown in FIGS. 13 to 15, the pipeline operation of data input / output and internal memory array access can be efficiently and appropriately performed in reading and writing. it can. As a result, the effective data transfer rate can be greatly improved.
That is, the pipeline operation can be smoothly performed by providing a register for storing a reserved address and an output-only data register separately from the memory array access.
In addition, by providing a mechanism that automatically shifts the pipeline stage upon completion of memory array access and starts the next memory access, the memory access process that is the bottleneck of transfer is continuously processed without interruption. And maximum transfer efficiency can be obtained.
Further, by performing such automatic processing with reference to a flag set in advance by a reservation command, both safe and flexible data access and efficient data transfer can be achieved.
In addition, the host can easily determine the data input / output timing by providing a notification pin to the outside, and providing a mechanism to change it to the BUSY state by the reservation command and to the REDY state by the stage shift by the automatic processing. Smooth data transfer can be performed.

  In this embodiment, the case where there are two banks has been described as an example. However, it goes without saying that the present invention can be applied to a semiconductor memory device having a larger number of banks, for example, four or eight banks. Absent.

1 is a block diagram showing an overall configuration of a signal processing system employing a semiconductor memory device according to the present invention. FIG. 2 is a block diagram illustrating a configuration example of a NAND flash memory in FIG. 1. FIG. 3 is a block diagram illustrating a specific configuration example of a bank in FIG. 2. It is a figure for demonstrating the specific structural example of the bank of FIG. 3, and a row decoder. It is a figure which shows the structural example of the data transfer path | route between the bit line of the cell array in a bank, and a column selector. 6 is a timing chart of the circuit of FIG. 5 at the time of reading. It is a figure which shows the other structural example of the data transfer path | route between the bit line of the cell array in a bank, and a column selector. FIG. 3 is a diagram showing bias conditions of each drive line at the time of data reading in the bank of FIG. 2. FIG. 3 is a diagram showing bias conditions for each drive line during data write in the bank of FIG. 2. It is a block diagram which shows the specific structural example of the controller which concerns on this embodiment. 6 is a timing chart for explaining a read operation sequence of the flash memory 2 according to the present embodiment. It is a figure for demonstrating the effect which provided the address reservation register. FIG. 3 is a block diagram showing another configuration example of the NAND flash memory in FIG. 1. It is a figure which shows the example of the data read operation | movement from the single bank of the flash memory which provided the flag register. It is a figure which shows the example of the data read operation | movement from the some bank of the flash memory which provided the flag register.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Signal processing system, 2, 2A ... NAND type flash memory, 201 (A), 202 (B) ... Bank, 203 (A-AD1) ... Previous stage address registers 203, 204 (A-AD2) ... Back stage address Register, 205 (B-AD1)... Previous address register, 206 (B-AD2)... Later address register, 207... Control system signal input / output unit, 208... Data input / output unit, 209. ... Control circuit 211 211 first bank control circuit 212 second bank control circuit 213 status register 214 booster circuit 220 bank (A, B) (201, 202) 221 cell array 222: Row (row, page) decoder, 223: Block address decoder, 2 4 ... Word line decoder, 225 ... First data latch circuit (DT1), 226 ... Second data latch circuit (DT2), 227 ... Column selector (Y selector), 228 ... Column (column) decoder, 230 ... Flag Register, 3... Controller, 4... CPU (host device), 5... Bridge circuit, 6.

Claims (11)

A cell array in which memory cells are arranged in a matrix and reads data according to an address;
A first latch circuit that holds data read from the cell array, a second latch circuit that holds data held in the first latch circuit at a predetermined timing, and holds the transferred data; Data holding means that can transfer read data to the outside when data is held in the second latch circuit;
And a plurality of banks, including,
A flag register in which a flag value is set in advance according to an input command value;
A bank switching circuit for inputting / outputting data from the second latch circuit through a column selector selectively controlled by a column decoder;
When any one of the plurality of banks is selected and the completion of access to the memory cell array is notified, the value set in the flag register is referred to and an access instruction for the selected bank is output. A control circuit ;
Provided corresponding to each of the plurality of banks,
Current address holding means for holding an address for reading data of the cell array;
Reservation address holding means capable of receiving and holding a reservation address in advance by an access reservation command at least for the next reading,
When the access instruction is supplied from the control circuit and read from the cell array by the address held in the current address holding means, and the data held in the data holding means can be transferred to the outside, the access reservation command a bank control circuit to be held in the data holding means a reserved address held in the reserved address holding means is held in the current address holding portion to perform the reading of the data by,
Have
The control circuit automatically and internally transfers the address from the reserved address holding means to the current address holding means, and from the first latch circuit to the first bank to the bank from which data has been read from the cell array. It is possible to perform internal processing for executing data transfer to the latch circuit 2 and starting reading of the next data from the cell array. The internal processing is then performed by the access reservation command to the reserved address holding means. after the address to be read is set, the internal processing of the automatic shift processing reservation command for instructing an operation to automatically perform is inputted preset reference value of the flag register those the flag value is a predetermined value A semiconductor memory device that executes processing only in the case of. The bank control circuit corresponding to each bank, when the data held in the data holding means can be transferred to the outside, the data holding means according to a control signal during a period in which data transfer from other banks is not performed to the outside The semiconductor memory device according to claim 1 , wherein held data is transferred to the outside via the bank switching circuit . The bank control circuit corresponding to each bank reads data from the address held in the current address holding unit, and externally transfers the held data to the outside by the data holding unit. Outputs a busy signal indicating a busy state in which the read data is not ready for transfer,
2. The semiconductor memory device according to claim 1, wherein said reserved address holding means corresponding to each bank can receive and hold said reserved address from outside even in said busy state. The bank control circuit corresponding to each bank reads data from the address held in the current address holding means, and when the data held in the data holding means can be transferred to the outside, the semiconductor memory device according to claim 3, wherein outputting the ready over signal indicating a ready state that could transfer preparation of the read data. The bank control circuit corresponding to each bank can transfer the data held in the data holding means to the outside, and after receiving the command to instruct the external transfer of data by the outside after outputting the ready signal, The semiconductor memory device according to claim 1 , wherein held data is transferred from the data holding means to the outside via the bank switching circuit by a control signal during a period in which data transfer from the bank to the outside is not performed. 5. The semiconductor memory device according to claim 4 , wherein the bank control circuit corresponding to each bank outputs the ready signal to the outside when read data is held in the second latch circuit and can be transferred to the outside. When the read data is held in the second latch circuit and can be transferred to the outside, the bank control circuit corresponding to each bank outputs the ready signal to the outside, and issues a command for instructing external transfer of data by the outside. 6. The semiconductor memory according to claim 5 , wherein when the data is received, data held in the second latch circuit is transferred to the outside via the bank switching circuit by a control signal during a period in which data transfer from another bank is not performed to the outside. apparatus. Further comprises a status notification pin, and the notification pin enters the busy state in response to an input of a reservation command and enters a ready state-depending on execution of the internal processing in at least one of the banks claims 1 semiconductor according Storage device. The control circuit may be data finishes being read from the cell array at any bank, if the reservation to the flag register is not such, the above internal processing waits for reservation to the flag register by the command input The semiconductor memory device according to claim 1 . The semiconductor memory device according to claim 1, further comprising a status register that is accessible from outside and stores a current operation state. A first semiconductor memory device;
A second semiconductor memory device from which stored data of the first semiconductor memory device is read;
A host device that controls access to the first and second semiconductor memory devices and performs predetermined signal processing in accordance with data stored in the second semiconductor memory device;
A controller for controlling an access request from the host device to the first semiconductor memory device,
The first semiconductor memory device includes:
A cell array in which memory cells are arranged in a matrix and reads data according to an address;
A first latch circuit that holds data read from the cell array, a second latch circuit that holds data held in the first latch circuit at a predetermined timing, and holds the transferred data; Data holding means that can transfer read data to the outside when data is held in the second latch circuit;
And a plurality of banks, including,
A flag register in which a flag value is set in advance according to an input command value;
A bank switching circuit for inputting / outputting data from the second latch circuit through a column selector selectively controlled by a column decoder;
When any one of the plurality of banks is selected and the completion of access to the memory cell array is notified, the value set in the flag register is referred to and an access instruction for the selected bank is output. A control circuit ;
Provided corresponding to each of the plurality of banks,
Current address holding means for holding an address for reading data of the cell array;
Reservation address holding means capable of receiving and holding a reservation address in advance by an access reservation command at least for the next reading,
When the access instruction is supplied from the control circuit and read from the cell array by the address held in the current address holding means, and the data held in the data holding means can be transferred to the outside, the access reservation command a bank control circuit to be held in the data holding means a reserved address held in the reserved address holding means is held in the current address holding portion to perform the reading of the data by,
Have
The control circuit automatically and internally transfers the address from the reserved address holding means to the current address holding means, and from the first latch circuit to the first bank to the bank from which data has been read from the cell array. It is possible to perform internal processing for executing data transfer to the latch circuit 2 and starting reading of the next data from the cell array. The internal processing is then performed by the access reservation command to the reserved address holding means. after the address to be read is set, the internal processing of the automatic shift processing reservation command for instructing an operation to automatically perform is inputted preset reference value of the flag register those the flag value is a predetermined value A signal processing system that performs processing only in the case of.

Images