JP4230243B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device including a ferroelectric capacitor and a manufacturing method thereof.
[0002]
[Prior art]
There are several types of nonvolatile memories in which information remains even when the power is turned off. Among them, FeRAM (Ferroelectric Random Access Memory) has attracted attention in recent years due to its high-speed operation and low-voltage operation.
[0003]
FeRAM has a ferroelectric capacitor in which the lower electrode, capacitor ferroelectric film, and upper electrode are stacked in this order, and the two polarization directions of the capacitor ferroelectric film correspond to "0" and "1", respectively. To store information. The separation of “0” and “1” becomes easier as the polarization amount of the capacitor ferroelectric film is larger. For this purpose, good crystallinity is required for the capacitor ferroelectric film.
[0004]
Generally used capacitor ferroelectric film is PZT (Pb (Zr_x, Ti_1-x) O_Three) Film, and this PZT film is polarized in the (001) direction. Therefore, in the PZT film, spontaneous polarization can be maximized by aligning its orientation in the (001) direction, but it is usually not possible to align the orientation in the (001) direction, but instead align it in the (111) direction. It is common to earn spontaneous polarization.
[0005]
Since the film quality of the PZT film greatly depends on the film formation method and the constituent material of the lower electrode, it is important to find a lower electrode that is compatible with the PZT film formation method. For example, when a PZT film is formed by sputtering, a Pt / Ti film in which a Ti film and a Pt film are stacked in this order is employed as the lower electrode. In this case, the Pt film is formed so as to be oriented in the (111) direction.
[0006]
According to such a Pt / Ti lower electrode, when crystallization annealing is performed on a PZT film formed by sputtering, Ti atoms in the Ti film are moved along the Pt grain boundaries in the Pt film by the heat of annealing. Diffuses to reach the surface of the Pt film, and the Ti atoms are oxidized by oxygen in the PZT film, and TiO₂Become the nucleus.
[0007]
This TiO₂The nuclei serve as initial growth nuclei of the PZT film and also serve to align the orientation of the PZT film in the (111) direction, so that the obtained PZT is a film suitable for FeRAM oriented in the (111) direction. Moreover, since the lattice constants of the Pt film and the PZT film both oriented in the (111) direction are close to each other, almost no lattice mismatch occurs between these films, and the orientation in the (111) direction is likely to appear in the PZT film. .
[0008]
In the above, the PZT film is formed by the sputtering method. In addition to this, a method of forming the PZT film by the MOCVD (Metal Organic Chemical Vapor Deposition) method is also currently being studied. The PZT film formed by the MOCVD method has a higher-density crystal than that formed by the sputtering method. Therefore, even if the ferroelectric capacitor is miniaturized, a large amount of residual polarization can be secured, and FeRAM is highly integrated. It becomes possible to push forward.
[0009]
However, when a PZT film is formed on the Pt / Ti lower electrode by the MOCVD method, the Pt of the lower electrode and Pb in the MOCVD atmosphere react to obtain only a PZT film having a large leakage current. Surface roughening occurs in the electrode.
[0010]
In order to eliminate such inconvenience, it has been studied to use Ir, which is the same platinum group element as Pt, instead of Pt and to form the lower electrode with an Ir / Ti film.
[0011]
However, since Ir is denser and smaller in grain size than Pt, the underlying Ti cannot diffuse into the Ir film and reach the surface of the Ir film, and TiO should be the growth nucleus of PZT.₂Cannot form nuclei. Furthermore, even if the orientation of the Ir film is aligned with the (111) direction so that the orientation of the PZT film is in the (111) direction, the lattice constant of the Ir film oriented in the (111) direction is oriented in the (111) direction. Therefore, a lattice constant mismatch occurs between the two films, and the PZT film grows in the (100) direction or a random direction.
[0012]
As another lower electrode structure, IrO is sputtered on the Ir film.₂IrO obtained by forming a film₂Patent Document 1 proposes to use / Ir as the lower electrode.
[0013]
Although not disclosed, in Japanese Patent Application No. 2001-252974, an Ir layer oriented in the (111) direction and an IrO oriented in the (200) direction.₂Have been proposed to be used as a lower electrode.
[0014]
Further, according to Patent Document 2, it is disclosed that in an electrode composed of a single metal element, the metal becomes crystalline and irregularities are generated on the surface of the electrode, which prevents the capacitor dielectric film from being thinned. In order to avoid this inconvenience, Patent Document 2 discloses that an electrode is formed of an alloy made of a plurality of metals, thereby making the electrode amorphous to reduce the surface unevenness.
[0015]
[Patent Document 1]
JP 2002-151656 A
[Patent Document 2]
Japanese Patent Laid-Open No. 11-330388
[0016]
[Problems to be solved by the invention]
However, in Patent Document 1, IrO formed by sputtering is used.₂Because the film is oriented in the (110) direction, IrO₂The lattice mismatch between the film and the PZT film oriented in the (111) direction is large, the PZT film is oriented in the (101) direction, (110) direction, or randomly, and the residual polarization amount of the PZT film is reduced. End up.
[0017]
In Japanese Patent Application No. 2001-252974, IrO₂IrO on the bottom electrode₂By orienting the film to (200), the (111) -oriented PZT film and IrO₂Although the lattice constant difference with the film is reduced, IrO₂It is very difficult to control the orientation of the film in this way. Therefore, orientations other than (200), such as orientation in the (110) direction, are IrO.₂Even if the orientation of the PZT film is dominant in the (111) direction, an orientation in another direction is formed in the PZT film, resulting in a decrease in the spontaneous polarization value of the PZT film. End up.
[0018]
An object of the present invention is to provide a semiconductor device capable of forming a ferroelectric film having a spontaneous polarization value larger than the conventional one by MOCVD and a method for manufacturing the same.
[0019]
[Means for Solving the Problems]
  According to one aspect of the present invention, a semiconductor substrate, an insulating film formed above the semiconductor substrate, a lower electrode, a ferroelectric film, and an upper electrode are sequentially formed on the insulating film. The lower electrode has an iridium layer whose surface layer is amorphous in the uppermost layer.The ferroelectric film is Pb (Zr _x , Ti _1-x ) O _Three (However, x Is 0 ≦ x ≦ 1 Real number), PLZT ,as well as PCSLZT Consisting of any of its X Light diffracted light (111) Has a peak in the directionA semiconductor device is provided.
[0020]
  According to another aspect of the present invention, a step of forming an insulating film above a semiconductor substrate, a step of forming an iridium layer on the insulating film, and oxidizing the surface layer of the iridium layerTo form an iridium oxide layerAnd a MOCVD method on the oxidized iridium layer.Pb (Zr _x , Ti _1-x ) O _Three (However, x Is 0 ≦ x ≦ 1 Real number), PLZT ,as well as PCSLZT Composed of eitherForming a ferroelectric film; forming an upper electrode conductive layer on the ferroelectric film; and patterning the iridium layer, the ferroelectric film, and the upper electrode conductive layer. The iridium layer as a lower electrode, the ferroelectric film as a capacitor ferroelectric film, and the upper electrode conductive layer as an upper electrode.By forming the ferroelectric film, the iridium oxide layer becomes an amorphous iridium layer, and the X-ray diffracted light of the ferroelectric film is (111) Has a peak in the directionA method for manufacturing a semiconductor device is provided.
[0021]
Next, the operation of the present invention will be described.
[0022]
According to the present invention, the surface layer of the iridium layer is oxidized to form the iridium dioxide layer, and the ferroelectric film is formed thereon by the MOCVD method, so that the metal element contained in the MOCVD filming atmosphere is iridium dioxide. The metal oxide is oxidized by oxygen supplied from the layer to generate a metal oxide, and the orientation in a specific direction is induced in the ferroelectric film by the metal oxide.
[0023]
Moreover, the iridium dioxide layer is transformed into an amorphous iridium layer when all of the oxygen in the ferroelectric film is formed, and this amorphous iridium layer changes the lattice mismatch between the ferroelectric film and the iridium layer. Since it functions as a buffer layer for buffering, orientation other than a specific direction is prevented from appearing in the ferroelectric film, and the spontaneous polarization of the ferroelectric film increases.
[0024]
Note that Pb (Zr_x, Ti_1-x) O_Three(Where x is a real number satisfying 0 ≦ x ≦ 1), when forming a film composed of any of PLZT and PCSLZT, TiO as the above metal oxide₂Produces this TiO₂As a result, orientation in the (111) direction is induced in the ferroelectric film.
[0025]
In addition, if the iridium layer is oxidized by thermal oxidation, the oxidation rate becomes slow when oxidation is performed to a certain depth from the surface of the iridium layer, so that the film thickness of the iridium dioxide layer can be easily controlled by time. It becomes.
[0026]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings.
[0027]
1 to 6 are cross-sectional views showing a process for forming a semiconductor device according to an embodiment of the present invention. In the following, a stack type FeRAM in which a conductive plug is formed immediately below a ferroelectric capacitor will be described as an example. However, the present invention is not limited to this and can be applied to a planar type FeRAM.
[0028]
First, steps required until a sectional structure shown in FIG.
[0029]
As shown in FIG. 1A, after an element isolation trench is formed around the transistor formation region of the n-type or p-type silicon (semiconductor) substrate 1 by photolithography, oxidation is performed in the element isolation trench. Silicon (SiO₂) Are embedded to form the element isolation insulating film 2. The element isolation insulating film 2 having such a structure is called STI (Shallow Trench Isolation). Note that an insulating film formed by a LOCOS (Local Oxidation of Silicon) method may be employed as the element isolation insulating film.
[0030]
Subsequently, a p-type impurity is introduced into the transistor formation region of the silicon substrate 1 to form a p-well 1a. Further, the surface of the transistor formation region of the silicon substrate 1 is thermally oxidized to form a silicon oxide film that becomes the gate insulating film 3.
[0031]
Next, an amorphous or polycrystal silicon film and a tungsten silicide film are sequentially formed on the entire upper surface of the silicon substrate 1, and the silicon film and the tungsten silicide film are patterned by a photolithography method to form gate electrodes 4a, 4b is formed.
[0032]
Two gate electrodes 4a and 4b are formed in parallel on one p-well 1a, and these gate electrodes 4a and 4b constitute part of the word line.
[0033]
Next, n-type impurities are ion-implanted on both sides of the gate electrodes 4a and 4b in the p-well 1a to form first to third n-type impurity diffusion regions 5a to 5c to be sources / drains.
[0034]
Further, an insulating film such as silicon oxide (SiO 2) is formed by CVD.₂) After the film is formed on the entire surface of the silicon substrate 1, the insulating film is etched back to leave insulating side wall spacers 6 on both sides of the gate electrodes 4a and 4b.
[0035]
Subsequently, n-type impurities are ion-implanted again into the first to third n-type impurity diffusion regions 5a to 5c using the gate electrodes 4a and 4b and the sidewall spacers 6 as a mask, whereby the first to first n-type impurities are implanted. 3 n-type impurity diffusion regions 5a to 5c are made to have an LDD (Lightly Doped Drain) structure.
[0036]
Note that the first n-type impurity diffusion region 5a between the two gate electrodes 4a and 4b in one transistor formation region is electrically connected to the bit line, and the second and third regions on both ends of the transistor formation region. N-type impurity diffusion regions 5b and 5c are electrically connected to the lower electrode of the capacitor.
[0037]
Through the above steps, the two MOS transistors T having the gate electrodes 4a and 4b and the n-type impurity diffusion layers 5a to 5c having the LDD structure are formed in the p well 1a.₁, T₂Is formed.
[0038]
Next, MOS transistor T₁, T₂A silicon oxynitride (SiON) film having a thickness of about 200 nm is formed on the entire surface of the silicon substrate 1 by plasma CVD as a cover insulating film 7 covering the substrate. Thereafter, a silicon oxide (SiO 2 film having a thickness of about 1.0 μm is formed by plasma CVD using TEOS gas.₂) Is formed as a first interlayer insulating film 8 on the cover film 7.
[0039]
Subsequently, as a densification process of the first interlayer insulating film 8, the first interlayer insulating film 8 is heat-treated at a temperature of 700 ° C. for 30 minutes, for example, in a normal-pressure nitrogen atmosphere. Thereafter, the upper surface of the first interlayer insulating film 8 is planarized by a chemical mechanical polishing (CMP) method.
[0040]
Next, steps required until a structure shown in FIG.
[0041]
First, the cover insulating film 7 and the first interlayer insulating film 8 are patterned by a photolithography method to form a first contact hole 8a having a depth reaching the first impurity diffusion region 5a. Thereafter, a titanium (Ti) film having a thickness of 30 nm and a titanium nitride (TiN) film having a thickness of 50 nm are sequentially formed as a glue film on the upper surface of the first interlayer insulating film 8 and the inner surface of the contact hole 8a by a sputtering method. In addition, WF₆A tungsten (W) film is grown on the TiN film by a CVD method using, thereby completely filling the first contact hole 8a.
[0042]
Subsequently, the W film, the TiN film, and the Ti film are polished by a CMP method and removed from the upper surface of the first interlayer insulating film 8. The tungsten film, TiN film, and Ti film left in the first contact hole 8 a are used as the first conductive plug 9.
[0043]
Thereafter, as shown in FIG. 1 (c), on the first interlayer insulating film 8 and the first conductive plug 9, a silicon nitride (Si film having a thickness of 100 nm is formed._ThreeN_Four) Anti-oxidation insulating film 10a and 100 nm thick SiO₂The underlying insulating film 10b is formed in order by plasma CVD. Its SiO₂The film is grown by plasma CVD using TEOS. The anti-oxidation insulating film 10a is formed in order to prevent the plug 9 from being abnormally oxidized during the heat treatment by annealing or the like later and causing a contact failure, and it is desirable that the film thickness be 70 nm or more, for example.
[0044]
Next, as shown in FIG. 2A, the anti-oxidation insulating film 10a, the base insulating film 10b, and the first interlayer insulating film 8 are etched by using a resist pattern (not shown), whereby the second and third insulating films are etched. Second and third contact holes 8b and 8c are formed on the impurity diffusion regions 5b and 5c.
[0045]
Further, a Ti film with a thickness of 30 nm and a TiN film with a thickness of 50 nm are sequentially formed as a glue film on the upper surface of the base insulating film 10b and the inner surfaces of the second and third contact holes 8b and 8c by sputtering. After that, a W film is grown on the TiN film by CVD to completely fill the second and third contact holes 8b and 8c.
[0046]
Subsequently, as shown in FIG. 2B, the W film, the TiN film, and the Ti film are polished by the CMP method and removed from the upper surface of the base insulating film 10b. As a result, the tungsten film, TiN film, and Ti film remaining in the second and third contact holes 8b and 8c are defined as second and third conductive plugs 11a and 11b, respectively.
[0047]
Next, steps required until a structure shown in FIG.
[0048]
First, the silicon substrate 1 is placed in a sputter chamber (not shown), the substrate temperature is maintained at 550 ° C., Ar gas having a flow rate of 199 sccm is introduced into the chamber as a sputter gas, and the chamber is filled with a vacuum pump (not shown). And the pressure in the chamber is reduced to about 7.5 × 10^-FourHold in Torr. Thereafter, a DC power of 0.3 kW is applied to an iridium (Ir) target (not shown) for 350 seconds, whereby a thickness of about 150 nm is formed on the second and third conductive plugs 11a and 11b and the underlying insulating film 10b. The iridium layer 15 is formed. The iridium layer 15 has a polycrystalline structure, and the orientation of each grain on the surface of the iridium layer 15 is the (111) direction.
[0049]
The method of forming the iridium layer 15 is not limited to the sputtering method, and the iridium layer 15 may be formed by a MOD (Metal Organic Deposition) method, a sol-gel method, or a CVD method.
[0050]
Thereafter, as shown in FIG. 3 (a), the silicon substrate 1 is placed in a horizontal electric furnace (not shown) and the substrate temperature is kept at 500 ° C. to 650 ° C., for example, 650 ° C., and 100% O₂The surface layer of the iridium layer 15 is thermally oxidized under normal pressure while flowing through the furnace at a flow rate of 6 slm. As a result, the surface layer portion of the iridium layer 15 having a depth of 10 nm or less from the surface is oxidized, and iridium dioxide (IrO) having a thickness of 10 nm is oxidized.₂) Layer 15b is formed. If a thicker iridium dioxide layer 15b is to be formed, it takes a long time to oxidize. Therefore, the film thickness of the iridium dioxide layer 15b is preferably kept at 10 nm.
[0051]
The upper limit of the temperature at the time of thermal oxidation was set to 650 ° C., because iridium is IrO at higher temperatures._FourThis is because it volatilizes. Further, the reason why the lower limit of the temperature is set to 500 ° C. is that if the temperature is lower than this, it takes a long time for the oxidation, which is not preferable because the throughput of the manufacturing process of FeRAM is lowered.
[0052]
According to such thermal oxidation, when the oxidation is performed from the surface of the iridium layer 15 to a certain depth, the oxidation rate becomes slow, so that the film thickness of the iridium dioxide layer 15b is easily controlled by time.
[0053]
Further, the orientation of the iridium dioxide layer 15b formed by thermal oxidation is mainly the (110) orientation, but in this embodiment, the orientation is not important and may be non-oriented.
[0054]
In addition to the horizontal electric furnace, a vertical electric furnace, a hot plate, and RTA (Rapid Thermal Annealing) may be used as the thermal oxidation treatment apparatus. Further, the oxidizing atmosphere is not limited to the above, and the iridium dioxide layer 15b may be formed in an oxygen atmosphere to which an inert gas such as argon (Ar) is added.
[0055]
Next, steps required until a structure shown in FIG.
[0056]
First, the substrate 1 is placed in a MOCVD (organic metal CVD) reactor (not shown), and the substrate temperature is maintained at 620 ° C.
[0057]
Then Pb (thd) as an organic source for lead (Pb) supply₂(Pb (C₁₁H₁₉O₂)₂) THF (Tetra Hydro Furan: C_FourH₈O) Dissolved in a liquid at a concentration of 0.3 mol / l is introduced into a vaporizer (not shown) at a flow rate of 0.32 ml / min. Zr (DMHD) as an organic source for supplying zirconium (Zr)_Four(Zr (C₉H₁₅O₂)_Four) Is dissolved in THF solution at a concentration of 0.3 mol / l, and it is introduced into the vaporizer at a flow rate of 0.2 ml / min. Furthermore, Ti (O-iPr) as a source for supplying titanium (Ti)₂(thd)₂(Ti (C_ThreeH₇O)₂(C₁₁H₁₉O₂)₂) Is dissolved in THF solution at a concentration of 0.3 mol / l, and it is introduced into the vaporizer at a flow rate of 0.2 ml / min.
[0058]
The vaporizer is heated to a temperature of about 260 ° C., and each of the organic sources described above is vaporized in the vaporizer. Each vaporized organic source is mixed with oxygen having a flow rate of 2500 sccm in the vaporizer, and then introduced into the shower head at the top of the reactor to become a uniform flow, and is applied to the silicon substrate 1 placed facing the shower head. It is sprayed uniformly toward. Note that the partial pressure of oxygen in the reactor is maintained at 5 Torr, for example.
[0059]
If such a state is maintained for 420 seconds, the iridium dioxide layer 15b changes to the amorphous iridium layer 15c, and a PZT film having a thickness of 120 nm is formed as the ferroelectric film 16 on the amorphous iridium layer 15c. The reason why the iridium dioxide layer becomes amorphous will be described later.
[0060]
The composition ratio of the PZT ferroelectric film 16 is Pb (Zr_x, Ti_1-x) O_ThreeAlthough it is determined by the value of x in (0 ≦ x ≦ 1), this value can be controlled by the mixing ratio of each organic source and is not particularly limited.
[0061]
Next, steps required until a structure shown in FIG.
[0062]
First, for example, iridium dioxide having a film thickness of 200 nm is formed on the ferroelectric film 16 as the upper electrode conductive layer 17 by sputtering.
[0063]
Thereafter, a TiN film and SiO as a hard mask 18 on the upper electrode conductive layer 17.₂A film is formed in order. The hard mask 18 is patterned by photolithography so as to have a capacitor planar shape above the second and third conductive plugs 11a and 11b.
[0064]
Next, as shown in FIG. 4B, the upper electrode conductive layer 17, the ferroelectric film 16, the amorphous iridium layer 15c, and the iridium layer 15 in a region not covered with the hard mask 18 are sequentially etched. In this case, the ferroelectric film 16 is etched by a sputtering reaction in an atmosphere containing chlorine and argon. The conductive layer 17 for the upper electrode, the amorphous iridium layer 15c, and the iridium layer 15 are made of bromine (Br₂) Etching is performed by sputtering reaction in an introduction atmosphere, in an atmosphere containing Br, or in an atmosphere in which only HBr and oxygen are introduced.
[0065]
As described above, the lower electrode 15a made of the iridium layer 15 and the amorphous iridium layer 15c, the capacitor ferroelectric film 16a made of the ferroelectric film 16, and the upper electrode conductive layer 17 are formed on the base insulating film 10b. The upper electrode 17a is formed, and the ferroelectric capacitor Q is constituted by these.
[0066]
In the transistor formation region, one lower electrode 15a is electrically connected to the second impurity diffusion region 5b via the second conductive plug 11a, and another lower electrode 15a connects the third conductive plug 11b. And is electrically connected to the third impurity diffusion region 5c.
[0067]
Thereafter, the hard mask 18 is removed.
[0068]
Subsequently, recovery annealing is performed to recover damage to the ferroelectric film 16 due to etching. In this case, the recovery annealing is performed, for example, in an oxygen atmosphere at a substrate temperature of 550 ° C. for 60 minutes.
[0069]
Next, as shown in FIG. 5 (a), a PZT film having a thickness of 50 nm is formed on the base insulating film 10b by sputtering as the protective film 19 covering the ferroelectric capacitor Q, and then 650 ° C. in an oxygen atmosphere. The capacitor Q is annealed under the conditions for 60 minutes. The protective film 19 protects the capacitor Q from process damage, and an alumina film may be formed in addition to the PZT film.
[0070]
Thereafter, a silicon oxide (SiO 2 film having a thickness of about 1.0 μm is formed as the second interlayer insulating film 20 by plasma CVD using TEOS gas.₂) Is formed on the protective film 19. Further, the upper surface of the second interlayer insulating film 20 is planarized by the CMP method. In this example, the remaining film thickness of the second interlayer insulating film 20 after CMP is set to about 300 nm on the upper electrode 17a of the capacitor Q.
[0071]
Next, as shown in FIG. 5B, the second interlayer insulating film 20, the protective film 19, the antioxidant insulating film 10a, and the base insulating film 10b are etched by using a resist mask (not shown). A hole 20 a is formed on one conductive plug 9.
[0072]
Further, a TiN film having a thickness of 50 nm is formed as a glue film in the hole 20a and on the second interlayer insulating film 20 by a sputtering method. Further, a W film is grown on the glue layer by the CVD method and the hole 20a is completely filled.
[0073]
Subsequently, the W film and the TiN film are polished by a CMP method and removed from the upper surface of the second interlayer insulating film 20. Then, the tungsten film and the glue layer left in the hole 20 a are used as the fourth conductive plug 21. The fourth conductive plug 21 is electrically connected to the first impurity diffusion region 5 a through the first conductive plug 9.
[0074]
Next, steps required until a structure shown in FIG.
[0075]
First, a SiON film is formed as a second antioxidant film (not shown) on the fourth conductive plug 21 and the second interlayer insulating film 20 by the CVD method. Further, the second antioxidant film and the second interlayer insulating film 20 are patterned by photolithography to form a contact hole 20b on the upper electrode 17a of the capacitor Q.
[0076]
The ferroelectric capacitor Q damaged by forming the contact hole 20b is recovered by annealing. The annealing is performed, for example, in an oxygen atmosphere at a substrate temperature of 550 ° C. for 60 minutes.
[0077]
Thereafter, the antioxidant film formed on the second interlayer insulating film 20 is removed by etch back, and the surface of the fourth conductive plug 21 is exposed.
[0078]
Next, a multilayer metal film is formed in the contact hole 20 b on the upper electrode 17 a of the ferroelectric capacitor Q and on the second interlayer insulating film 20. Thereafter, by patterning the multilayer metal film, a first layer metal wiring 21a connected to the upper electrode 17a through the contact hole 20b and a conductive pad 21b connected to the fourth conductive plug 21 are formed. As the multilayer metal film, for example, a structure in which Ti with a film thickness of 60 nm, TiN with a film thickness of 30 nm, Al—Cu with a film thickness of 400 nm, Ti with a film thickness of 5 nm, and TiN with a film thickness of 70 nm are sequentially formed.
[0079]
As a method for patterning a multilayer metal film, an antireflection film is formed on the multilayer metal film, and after applying a resist on the antireflection film, the resist is exposed and developed to form a resist pattern such as a wiring shape. Then, a method of etching the antireflection film and the multilayer metal film using the registration pattern is adopted.
[0080]
Thereafter, a third interlayer insulating film (not shown) is formed on the second interlayer insulating film 20, the first layer metal wiring 21a, and the conductive pad 21b, and is electrically connected to the fourth conductive plug 21. The fifth conductive plug is formed in the hole of the third interlayer insulating film, but its details are omitted.
[0081]
According to the above-described embodiment, after the surface of the iridium layer 15 is oxidized to form the iridium dioxide layer 15b, the step of forming the PZT ferroelectric film 16 thereon by the MOCVD method is employed. The present inventor conducted the following experiment in order to clarify the film formation mechanism and the characteristics of the PZT ferroelectric film 16. 7 to 8 are cross-sectional views showing a process for forming a sample of the PZT ferroelectric film used in the experiment.
[0082]
In this experiment, as shown in FIG. 7A, a silicon substrate 30 is placed in a sputtering chamber (not shown), the substrate temperature is maintained at 550 ° C., and Ar gas with a flow rate of 199 sccm is used as a sputtering gas in the chamber. And the inside of the chamber is evacuated by a vacuum pump (not shown) to reduce the pressure in the chamber to about 7.5 × 10^-FourHeld in Torr. Thereafter, an iridium layer 31 having a thickness of 150 nm was formed on the silicon substrate 30 by applying a DC power of 0.3 kW to an iridium (Ir) target (not shown) for 350 seconds. The iridium layer 31 has a polycrystalline structure, and the orientation of each grain is the (111) direction.
[0083]
Thereafter, as shown in FIG. 7 (b), the silicon substrate 30 is placed in a horizontal electric furnace (not shown) and the substrate temperature is kept at 650 ° C.₂The surface of the iridium layer 31 was thermally oxidized in a 100% atmospheric pressure atmosphere to form an iridium dioxide layer 31a having a thickness of 10 nm.
[0084]
Subsequently, the silicon substrate 30 was placed in a MOCVD reactor (not shown) and the substrate temperature was maintained at 620 ° C. And Pb (thd)₂Dissolved in THF solution is 0.32ml / min, Zr (DMHD)_FourIs dissolved in THF solution, 0.2 ml / min, and Ti (O-iPr)₂(thd)₂Was dissolved in a THF solution and introduced into a vaporizer (not shown) heated to 260 ° C. at a flow rate of 0.2 ml / min. The concentration of these organic sources is the same as described above.
[0085]
Each of the organic sources vaporized by the vaporizer is mixed with oxygen having a flow rate of 2500 sccm in the vaporizer, and then introduced into the shower head at the top of the reactor to form a uniform flow. It sprayed uniformly toward the placed silicon substrate 30. The partial pressure of oxygen in the reactor was maintained at 5 Torr.
[0086]
As a result, a PZT film-forming atmosphere is formed in the reactor, but titanium (Ti) contained in the atmosphere is more easily oxidized than other elements in the atmosphere.
[0087]
Therefore, as shown in FIG. 7 (c), titanium in the atmosphere is oxidized by oxygen in the iridium dioxide layer 31a at the initial stage of the PZT film formation, and the TiO2 on the iridium dioxide layer 31a.₂Precipitate as nuclei 33.
[0088]
In the initial stage, crystallized PZT does not grow, only a very thin amorphous PZT film 32 is formed on the iridium dioxide layer 31a, and oxygen still remains in the iridium dioxide layer 31a. To do.
[0089]
However, when a certain amount of time elapses, the thickness of the iridium dioxide layer 31a, which was an oxygen supply source, is as thin as 10 nm, so that oxygen is completely removed from the layer. As a result, as shown in FIG. 8A, the iridium dioxide layer 31a is changed to the amorphous iridium layer 31b, and the lower electrode 31c composed of the amorphous iridium layer 31b and the iridium layer 31 is obtained. Along with this, TiO₂The nuclei 33 become crystal growth nuclei, and crystallization of the uncrystallized PZT film 32 starts, and PZT crystal grains 32a grow on the amorphous iridium layer 31b.
[0090]
This PZT crystal grain 32a has TiO₂Since the orientation of the (111) direction is induced by the action of the nucleus 33, the orientation of the PZT film 32b in FIG. 8B obtained by further progressing the growth of the PZT crystal grain 32a is also dominant in the (111) direction. Become. Moreover, since the amorphous iridium layer 31b functions as a buffer layer, the lattice mismatch between the (111) iridium layer 31 and the (111) PZT film 32b is relaxed, and orientations other than (111) appear in the PZT film 32b. Is prevented.
[0091]
FIG. 9 is a graph obtained by examining the crystal structure of the iridium dioxide layer 31a before and after the formation of the PZT film 32b by XRD (X Ray Diffraction). In FIG. 9, θ on the horizontal axis indicates the incidence of X-rays on the sample surface, and the vertical axis indicates X-ray diffracted light in arbitrary units.
[0092]
As shown in this figure, since the peak appears in the diffraction intensity in the (110) direction before the formation of the PZT film 32b, it is understood that the orientation of the iridium dioxide layer 31a is in the (110) direction.
[0093]
On the other hand, no peak in the (110) direction is observed after the formation of the PZT film 32b. This indicates that oxygen has escaped from the iridium dioxide layer 31a, and the iridium dioxide layer 31a has all changed to an amorphous iridium layer 31b.
[0094]
The fact that the iridium dioxide layer 31a has changed to an amorphous state can also be understood by comparing FIGS. 12 (a) and 12 (b). 12 (a) and 12 (b) are cross-sectional views drawn on the basis of an electron micrograph in the vicinity of the interface between the iridium layer 31 and the PZT film 32b, and FIG. 12 (a) does not form the iridium dioxide layer 31a. FIG. 12B shows a case where it is formed by thermal oxidation.
[0095]
Comparing the two, when the iridium dioxide layer 31a is not formed (FIG. 12 (a)), the interface between the iridium layer 31 and the PZT film 32b is clear, and there is no amorphous layer on the surface layer of the iridium layer 31. However, when the iridium dioxide layer 31a is formed (FIG. 12B), the interface is blurred, and it is understood that the amorphous iridium layer 31b is formed on the surface layer of the iridium layer 31. The
[0096]
FIG. 10 is a graph obtained by examining the crystal structures of the PZT film 32b and the PZT film formed on the lower electrode according to the conventional example by XRD. The meanings of the vertical and horizontal axes in FIG. 10 are the same as those in FIG.
[0097]
In FIG. 10, Conventional Example 1 shows a case where a PZT film similar to the above is formed on the lower electrode made of a single iridium layer formed by sputtering, and Conventional Example 2 shows that The case where the same PZT film as in Conventional Example 1 is formed by the MOCVD method on the lower electrode formed by forming the iridium dioxide layer on the iridium layer by the sputtering method is shown.
[0098]
As shown in FIG. 10, since the PZT film 32b of this embodiment is oriented in the (111) direction, a large spontaneous polarization value can be expected.
[0099]
On the other hand, since the PZT film of Conventional Example 1 is oriented in the (100) direction perpendicular to the (001) direction which is the polarization direction of PZT, a large spontaneous polarization value cannot be expected.
[0100]
Further, the PZT film of Conventional Example 2 does not have even an orientation in a specific direction, and has a random orientation.
[0101]
FIG. 11 shows an example in which an upper electrode made of an iridium dioxide layer is formed on each PZT film of the three samples of FIG. 10, and the spontaneous polarization of a ferroelectric capacitor composed of the upper electrode, the PZT film, and the lower electrode is measured. It is the graph obtained by doing. The horizontal axis in FIG. 11 indicates the potential difference between the upper electrode and the lower electrode, and the vertical axis indicates the spontaneous polarization of the capacitor when the potential difference is given.
[0102]
As shown in FIG. 11, in the range where the voltage is 1 V or more, the spontaneous polarization of the ferroelectric capacitor of the present invention becomes much larger than that of the conventional example. This is because the PZT polarization direction is the (001) direction, and the PZT film 32b of the present invention is oriented in the (111) direction having a non-zero component in this polarization direction.
[0103]
From these experimental results, by forming a PZT ferroelectric film by MOCVD on the iridium dioxide layer obtained by oxidizing the surface of the iridium layer, the orientation intensity of the PZT ferroelectric film in the (111) direction is As a result, it was confirmed that the spontaneous polarization of the ferroelectric capacitor was larger than before.
[0104]
Since the PZT film formed by MOCVD method has a higher density than PZT films formed by other methods such as sputtering, the present invention is applied to the stack type FeRAM as described above. Therefore, the high integration of FeRAM can be further promoted.
[0105]
As mentioned above, although embodiment of this invention was described in detail, this invention is not limited above. For example, instead of the above PZT, PLZT ((Pb, La) (Zr, Ti) O_Three) And PCSLZT to which Ca (calcium) and Sr (strontium) are added may be used to form the ferroelectric film.
The features of the present invention are added below.
[0106]
(Appendix 1) a semiconductor substrate;
An insulating film formed above the semiconductor substrate;
A ferroelectric capacitor formed by sequentially forming a lower electrode, a ferroelectric film, and an upper electrode on the insulating film;
Have
The lower electrode has an iridium layer whose surface layer portion is amorphous in the uppermost layer.
[0107]
(Supplementary note 2) The semiconductor device according to supplementary note 1, wherein the iridium layer has polycrystalline iridium under the amorphous portion.
[0108]
(Supplementary note 3) The semiconductor device according to Supplementary note 1 or 2, wherein the amorphous portion of the iridium layer is formed to a depth within 10 nm from the surface of the iridium layer.
[0109]
(Supplementary Note 4) The ferroelectric film is made of Pb (Zr_x, Ti_1-x) O_Three(Wherein x is a real number satisfying 0 ≦ x ≦ 1), PLZT, and PCSLZT, the semiconductor device according to any one of appendix 1 to appendix 3,
[0110]
(Supplementary note 5) The semiconductor device according to supplementary note 4, wherein the X-ray diffracted light of the ferroelectric film has a peak in a (111) direction.
[0111]
(Additional remark 6) The impurity diffusion area | region formed in the surface layer of the said semiconductor substrate,
A hole formed in the insulating film above the impurity diffusion region and below the lower electrode;
Any one of appendix 1 to appendix 5, further comprising a conductive plug formed in the hole and electrically connected to the impurity diffusion region and electrically connected to the lower electrode. The semiconductor device described.
[0112]
(Appendix 7) Forming an insulating film above the semiconductor substrate;
Forming an iridium layer on the insulating film;
Oxidizing the surface layer of the iridium layer;
Forming a ferroelectric film by MOCVD on the oxidized iridium layer;
Forming an upper electrode conductive layer on the ferroelectric film;
By patterning the iridium layer, the ferroelectric film, and the upper electrode conductive layer, the iridium layer is used as a lower electrode, the ferroelectric film is used as a capacitor ferroelectric film, and the upper electrode conductive layer is used. Using the upper electrode as a top electrode;
A method for manufacturing a semiconductor device, comprising:
[0113]
(Additional remark 8) The manufacturing method of the semiconductor device of Additional remark 7 characterized by forming an iridium dioxide layer in the surface layer part of this iridium layer by oxidation of the said iridium layer.
[0114]
(Additional remark 9) The film thickness of the said iridium dioxide layer is 10 nm or less, The manufacturing method of the semiconductor device of Additional remark 8 characterized by the above-mentioned.
[0115]
(Supplementary note 10) The method for manufacturing a semiconductor device according to supplementary note 8 or 9, wherein the X-ray diffracted light of the iridium dioxide layer has a peak in the (110) direction.
[0116]
(Additional remark 11) By forming the ferroelectric film, the peak in the (110) direction disappears, and the entire iridium dioxide layer becomes an amorphous iridium layer. Production method.
[0117]
(Additional remark 12) The said amorphous iridium layer does not contain oxygen, The manufacturing method of the semiconductor device of Additional remark 11 characterized by the above-mentioned.
[0118]
(Supplementary note 13) The method of manufacturing a semiconductor device according to any one of supplementary notes 7 to 12, wherein the iridium layer is oxidized by thermal oxidation.
[0119]
(Additional remark 14) The said thermal oxidation is performed in the atmospheric pressure atmosphere containing oxygen, The manufacturing method of the semiconductor device of Additional remark 13 characterized by the above-mentioned.
[0120]
(Supplementary note 15) The method for manufacturing a semiconductor device according to supplementary note 14, wherein the thermal oxidation is performed while maintaining a substrate temperature at 500C to 650C.
[0121]
(Supplementary Note 16) As the ferroelectric film, Pb (Zr_x, Ti_1-x) O_Three(Wherein x is a real number satisfying 0 ≦ x ≦ 1), a film composed of any one of PLZT and PCSLZT is formed; Method.
[0122]
(Supplementary Note 17) A step of forming an impurity diffusion region in a surface layer of the semiconductor substrate;
Forming a hole in the insulating film above the impurity diffusion region and below the lower electrode;
Forming a conductive plug in the hole to be electrically connected to the impurity diffusion region and the lower electrode;
The method of manufacturing a semiconductor device according to any one of appendix 7 to appendix 16, further comprising:
[0123]
【The invention's effect】
As described above, according to the present invention, the surface layer of the iridium layer is oxidized to form the iridium dioxide layer, and the ferroelectric film is formed thereon by the MOCVD method. Can be induced in the film.
[0124]
Moreover, at the end of the formation of the ferroelectric film, the iridium dioxide layer changes to an amorphous iridium layer, and this amorphous iridium layer functions as a buffer layer that buffers lattice mismatch between the ferroelectric film and the iridium layer. An orientation other than the specific direction is prevented from appearing in the ferroelectric film, and the spontaneous polarization of the ferroelectric film is increased.
[0125]
Furthermore, since the iridium layer is oxidized by thermal oxidation, the film thickness of the iridium dioxide layer can be easily controlled by time.
[Brief description of the drawings]
FIGS. 1A to 1C are cross-sectional views (part 1) showing a process for forming a semiconductor device according to an embodiment of the present invention.
FIGS. 2A to 2C are cross-sectional views (part 2) showing a process for forming a semiconductor device according to an embodiment of the present invention. FIGS.
FIGS. 3A and 3B are cross-sectional views (part 3) showing a process for forming a semiconductor device according to an embodiment of the present invention. FIGS.
FIGS. 4A and 4B are cross-sectional views (part 4) illustrating a process for forming a semiconductor device according to an embodiment of the present invention. FIGS.
FIGS. 5A and 5B are cross-sectional views (part 5) showing the process of forming the semiconductor device according to the embodiment of the invention. FIGS.
FIG. 6 is a sectional view (No. 6) showing a step of forming a semiconductor device according to the embodiment of the invention.
FIGS. 7A to 7C are cross-sectional views (No. 1) showing a process for forming a sample manufactured for examining the characteristics of the PZT film in the embodiment of the present invention. FIGS.
FIGS. 8A and 8B are cross-sectional views (part 2) showing a process for forming a sample manufactured for examining the characteristics of the PZT film in the embodiment of the present invention. FIGS.
FIG. 9 is a graph obtained by examining the crystal structure of the iridium dioxide layer before and after the formation of the PZT film by XRD in the embodiment of the present invention.
FIG. 10 is a graph obtained by examining the crystal structures of the PZT film in the embodiment of the present invention and the PZT film in the conventional example by XRD.
FIG. 11 is a graph obtained by examining the spontaneous polarization values of the ferroelectric capacitor in the embodiment of the present invention and the ferroelectric capacitor in the conventional example.
FIG. 12 (a) is a cross-sectional view based on an electron micrograph near the interface between the iridium layer and the PZT film when the surface layer of the iridium layer is not thermally oxidized, and FIG. FIG. 3 is a cross-sectional view drawn based on an electron micrograph in the vicinity of the interface between the iridium layer and the PZT film when an iridium dioxide layer is formed by thermally oxidizing the surface layer of the iridium layer.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1, 30 ... Silicon (semiconductor) substrate, 2 ... Element isolation insulating film, 3 ... Gate insulating film, 4a, 4b ... Gate electrode, 5a, 5b, 5c ... Impurity diffusion region, 6 ... Side wall spacer, 7 ... Cover insulation Membrane, 8 ... Interlayer insulating film, 9 ... Conductive plug, 10a ... Antioxidation insulating film, 10b ... Underlying insulating film, 11a, 11b ... Conductive plug, 15, 31 ... Iridium layer, 15a ... Lower electrode, 15b, 31a ... Iridium dioxide layer, 15c ... Amorphous iridium layer, 16 ... Ferroelectric film, 16a ... Dielectric film, 17 ... Conductive layer for upper electrode, 17a ... Upper electrode, 18 ... Hard mask, 19 ... Protective film, 20 ... Interlayer Insulating film, 21 ... conductive plug, 32 ... non-crystalline PZT film, 33 ... TiO₂Nuclei, 32a ... PZT crystal grains, 32b ... PZT film.

Claims (8)

A semiconductor substrate;
An insulating film formed above the semiconductor substrate;
A ferroelectric capacitor formed by sequentially forming a lower electrode, a ferroelectric film, and an upper electrode on the insulating film;
Have
The lower electrode has an iridium layer whose surface layer is amorphous in the uppermost layer ,
The ferroelectric _{film, Pb (Zr x, Ti 1} -x) O 3 ( where, x is a real number satisfying 0 ≦ x ≦ 1), is constituted by any of PLZT, and PCSLZT, its X diffraction light wherein a having a peak but (111) direction.   The semiconductor device according to claim 1, wherein the iridium layer includes polycrystalline iridium under the amorphous portion. Forming an insulating film above the semiconductor substrate;
Forming an iridium layer on the insulating film;
Oxidizing the surface layer of the iridium layer to form an iridium oxide layer ;
A strong material composed of Pb (Zr _x , Ti _1-x ) O ₃ (where x is a real number satisfying 0 ≦ x ≦ 1 ), PLZT , and PCSLZT on the oxidized iridium layer by MOCVD. Forming a dielectric film;
Forming an upper electrode conductive layer on the ferroelectric film;
By patterning the iridium layer, the ferroelectric film, and the upper electrode conductive layer, the iridium layer is used as a lower electrode, the ferroelectric film is used as a capacitor ferroelectric film, and the upper electrode conductive layer is used. Using the upper electrode as a top electrode;
I have a,
By forming the ferroelectric film, the iridium oxide layer becomes an amorphous iridium layer,
A method of manufacturing a semiconductor device, wherein the X-ray diffracted light of the ferroelectric film has a peak in the (111) direction . 4. The method of manufacturing a semiconductor device according to claim 3 , wherein the X-ray diffracted light of the iridium oxide layer has a peak in the (110) direction. The method of manufacturing a semiconductor device according to claim 4, characterized in that the peak of the (110) direction by forming the ferroelectric film disappears. The method of manufacturing a semiconductor device according to any one of claims 3 to 5, characterized in that oxidation of the iridium layer is performed by thermal oxidation. The method of manufacturing a semiconductor device according to claim 6 , wherein the thermal oxidation is performed in an atmospheric pressure atmosphere containing oxygen. 8. The method of manufacturing a semiconductor device according to claim 3, wherein an iridium dioxide layer is formed as the iridium oxide layer in the step of oxidizing the iridium layer. 9.

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