JP4382833B2 - Processor - Google Patents

Description

  The present invention relates to a processor having a debugging function for stopping execution of a program and verifying the execution result, and more particularly to a pipeline processor having a debugging function.

Microcomputer program debugging is done by CPU (central
The execution of the instruction by the processing unit) is temporarily stopped under various conditions and the value of the internal register is examined. In general, a dedicated debug circuit (also called an emulation circuit) is used for CPU control related to debugging.

The following patent documents describe inventions about a processor having a debug circuit.
JP 2000-029737 A

  When stopping execution of instructions by the CPU, the debug circuit first stops supplying instructions to the instruction register in the CPU. Usually, the CPU performs subsequent control on the assumption that the execution of the instruction of the CPU is stopped after a certain cycle has elapsed since the supply of the instruction is stopped.

  However, in the pipeline CPU, even if the supply of instructions is stopped, instructions supplied to the instruction register before the stop are sequentially executed according to the program flow. That is, even after the supply of the instruction to the instruction register is stopped, there is a period during which the instruction is executed in the CPU (hereinafter referred to as a transition period). In the transition period, if the CPU is controlled by the debug circuit on the assumption that the execution of the instruction of the CPU is stopped, various problems (pipeline hazard) described below occur.

For example, when receiving an interrupt request to the CPU, the debug circuit temporarily saves information related to debugging (such as information on an event that caused the CPU to stop) stored in a predetermined register for debugging to the stack. To do. When returning from the interrupt routine, the debugging information stored in the stack is returned to the original register.
However, if the debug circuit receives an interrupt request (interrupt request such as hardware control that is preferentially processed even when the CPU is stopped) during the transition period described above, the debug-related information is stacked according to the interrupt. In some cases, an instruction remaining in the pipeline after the data is stored in the pipeline may cause a new stop event (such as a stop event that occurs when data or an address matches a predetermined value). In this case, even though the newly generated stop event originates from the instruction supplied to the CPU instruction register before accepting the interrupt request, the debug register is effectively rewritten in the interrupt routine. End up. That is, there is a problem that the register information is rewritten as if a stop event derived from an instruction supplied before the interrupt request occurred in the interrupt routine.

  The present invention has been made in view of such circumstances, and an object of the present invention is to provide a pipeline-type processor that can eliminate a pipeline hazard caused by executing a debugging operation during a transition period when program execution is stopped. Is to provide.

A series of instructions sequentially processed by pipelining, to stop the process, as well as prohibiting the start of the process of the new instruction, already started when the disables the start of the processing of the new instruction Tei A command processing unit that outputs a status signal indicating whether or not incomplete processing has been completed, and at least the control of the operation of the command processing unit or the recording of the status of the operation according to the input command and debugging unit for debugging operation, if the status signal is the debugger in the period indicated incomplete state attempts to execute the debugging operation, suspended without executing the debug operation, wherein the status signal is not selected And a debug restriction unit that executes the suspended debug operation after the change from the complete state to the complete state .
According to the processor, when the instruction processing by the pipeline method is stopped in the instruction processing unit, the processing of a new instruction is stopped and the status signal indicating whether the already started processing is completed or not Is output. When this status signal indicates an incomplete state of processing in the instruction processing unit, execution of a debugging operation by the debug unit is restricted by the debug restriction unit. That is, the debugging operation related to the control of the operation of the instruction processing unit and the recording of the operation state is limited after the processing of the new instruction is stopped in the instruction processing unit until the processing of the remaining instructions is completed. Is done.

Preferably, the debug unit accesses at least a storage unit to be accessed by the instruction processing unit or inserts further instructions into the series of instructions according to an input command. May be included. It said instruction processing unit to stop processing the sequence of instructions, are already new in response to said access memory access section of the completion Not having been started process or when said prohibited the start of the process of the new instruction indicates whether already the insertion the already outstanding that were start processing includes processing uncompleted had been initiated in response to the instruction of the memory access unit is completed when the disables the start of processing of instructions The status signal may be output.

Preferably, the instruction processing unit includes an instruction execution unit that executes a series of input instructions in a pipeline manner, an input control unit that controls input of an instruction to the instruction execution unit, and the input control unit. A signal generation unit that generates a predetermined stop signal when input of an instruction to the instruction execution unit is stopped; In synchronization with the progression of the signal, a signal propagation unit including a plurality of delay units that sequentially propagate the input stop signal to the subsequent stage, and detecting whether the stop signal propagates through the signal propagation unit, A state signal output unit that outputs a detection result as the state signal.
According to the above configuration, when the input control unit stops the input of the instruction to the instruction execution unit, the signal generation unit generates the stop signal. The generated stop signal is input to the first stage of the plurality of delay units in the signal propagation unit, and is sequentially propagated to the subsequent delay unit in synchronization with the progress of the instruction execution stage in the instruction execution unit. While the stop signal is propagated in the signal propagation unit, the state signal output unit outputs the state signal indicating that the instruction execution in the instruction execution unit is not completed.
The signal propagation unit corresponds to, for example, a plurality of stages for executing one instruction in the instruction execution unit, and includes a plurality of delay units for propagating the stop signal, and an instruction execution by the plurality of stages An extended delay unit that further propagates the stop signal propagated by the plurality of delay units corresponding to the plurality of stages in a certain period during which the above-described processing can be performed.

The instruction processing unit includes: an instruction execution unit that executes a series of input instructions in a pipeline manner; an input control unit that controls input of an instruction to the instruction execution unit; and the input control unit When input of an instruction to the instruction execution unit is stopped, a stop instruction supply unit that supplies a predetermined stop instruction to the instruction execution unit, and whether or not the predetermined stop instruction is being executed in the instruction execution unit And a state signal output unit that outputs the detection result as the state signal.
According to the above configuration, when input of the instruction to the instruction execution unit is stopped by the input control unit, a predetermined stop instruction is supplied to the instruction execution unit by the stop instruction supply unit. While the predetermined stop instruction is being executed in the instruction execution unit, the state signal output unit outputs the state signal indicating that the instruction execution in the instruction execution unit is not completed.

Preferably, the debug unit may be able to control the instruction processing unit so as to accept an interrupt request even when instruction processing is stopped, and the debug limiting unit may indicate that the status signal is in an incomplete state. If the interrupt request occurs during the period shown, suspended without executing the acceptance of the interrupt request in the instruction processing unit according to the control of the debugger, the state signal is changed to the completion state of an uncompleted state Later, the pending interrupt request may be accepted.

Preferably, said debug limiting unit, when the status signal is the memory access section to the period indicated incomplete state attempts to execute the insertion of the access or the instruction without executing the insertion of the access or the instruction And the insertion of the reserved access or instruction may be executed after the status signal changes from the incomplete status to the completed status.
Further, when the access or the instruction insertion by the memory access unit occurs when the instruction processing unit stops the instruction processing, whether or not the processing corresponding to the access is completed or the insertion The status signal indicating whether or not the processing according to the issued command is completed may be output. When the interrupt request is generated in a period in which the status signal indicates that the processing corresponding to the access of the memory access unit is not completed or the processing corresponding to the inserted instruction is not completed, the debugging unit wherein according to a control of pending without executing the acceptance of the interrupt request in the instruction processing unit, the status signal may be executed reception of the hold the interrupt request after changing to completion state from an uncompleted state.

Preferably, the debug unit may include a state machine that indicates an execution state of an instruction in the instruction processing unit, and the debug restriction unit is configured so that the debug unit is in the state during a period in which the state signal indicates an incomplete state. If you try to perform an update of the state of the machine, pending without executing the updating of the state, the status signal may then execute the pending the state updated after changes to the completion state of an uncompleted state.

Preferably, the debug unit may include a storage unit that stores information related to a cause of stoppage of processing in the instruction processing unit, and the debug restriction unit may include the debug during a period in which the state signal indicates an incomplete state. If the part is trying to perform an update of the stored information of the storage unit, suspended without executing the updating of the stored information, said status signal of the hold the stored information after the change to the completion state of an uncompleted state An update may be performed.

Preferably, the debugging unit may control at least stop or restart of processing in the instruction processing unit as the debugging operation, and the debug limiting unit may be configured to output the debugging unit during a period when the state signal indicates an incomplete state. process but if an attempt is made to execute a process of stopping or restarting of the instruction processing unit, which reserves without running the stop or restart of the process, the status signal is the hold after having changed to the completion state of an uncompleted state May be stopped or restarted.

Preferably, the debug unit is a predetermined period related to processing of the instruction processing unit in a period in which an instruction is processed by the instruction processing unit, including a case where the state signal indicates an incomplete state. A counting unit that counts a signal indicating the occurrence of an event may be included.
In addition, the counting unit selects at least whether or not to count the counted signal in a period in which the state signal indicates an incomplete state, or the state signal is not yet determined in accordance with an input control signal. It may be possible to select whether or not to execute the initialization of the count value according to the initialization signal input during the period indicating the completion state.

  According to the present invention, from the time when the processing of a new command in the command processing unit is stopped until the processing already started before the stop is completed, the control of the operation of the command processing unit, the recording of the operation state, etc. Since the related debug operation is limited, various problems caused by executing the debug operation in the transition period in which the instruction processing unit shifts from the execution state to the stop state can be solved.

FIG. 1 is a diagram illustrating an example of a configuration of a processor according to an embodiment of the present invention.
The processor illustrated in FIG. 1 includes an instruction processing unit 10, a debug unit 20, and a debug restriction unit 30.

[Instruction processor 10]
The instruction processing unit 10 sequentially processes a series of input instructions in a pipeline manner. That is, a single instruction is processed in a plurality of stages, and a series of instructions are processed in parallel by performing the processing in each stage independently.

  The pipeline processing stage includes, for example, a stage of fetching an instruction from a program memory (not shown) (fetch stage) and a stage of decoding and executing the fetched instruction (execution stage). It is.

  In the fetch stage, for example, a stage of passing an address of an instruction to be fetched to the program memory (prefetch stage “PRE-FETCH1”), a stage of waiting for a response from the program memory (prefetch stage “PRE-FETCH2”), Stages where instructions are read from the program memory and stored in the instruction buffer queue IBQ (fetch stage “FETCH”), instructions stored in the instruction buffer queue IBQ are pre-decoded to identify instruction boundaries and pipeline protection A stage for determining whether to insert a cycle for the purpose (predecoding stage “PRE-DEC”) is included.

  In the execution stage, for example, a stage in which an instruction is read from the instruction buffer queue IBQ and decoded (decoding stage “DECODE”), and a storage address of data to be processed is generated based on the decoding result (address stage “ADDRESS”). ), Passing the generated address to a data memory (not shown) (access stage “ACCESS1”), waiting for a response from the data memory (access stage “ACCESS2”), and reading data from the data memory (Read stage “READ”), a stage for performing operations on data read from the data memory and data stored in the register (execution stage “EXE”), and a stage for writing the result data to the data memory or register (write) Stage "WRITE1", "WRITE2").

In addition, when the instruction processing unit 10 stops processing an instruction in accordance with the control of the debug unit 20 to be described later, the instruction processing unit 10 stops processing a new instruction and indicates whether or not the already started processing is completed. Is output. For example, when an event for stopping execution of a program (hereinafter referred to as a HALT event) occurs, the instruction processing unit 10 stops decoding of a new instruction and executes an instruction that has already entered the execution stage. A status signal S1 indicating whether or not it is completed is output.
In the “already started processing” whose state is indicated by the status signal S1 of the instruction processing unit 10, in addition to processing of a normal instruction started in accordance with the program flow, it starts in response to an access request from the DMA unit 23 described later. And processing started in response to an instruction inserted into a normal instruction by the DMA unit 23.

  For example, as shown in FIG. 1, the instruction processing unit 10 includes an instruction buffer / queue IBQ, an input control unit 11, a selector 12, an instruction execution unit 13, a pipeline protection unit 14, a signal generation unit 15, A signal propagation unit 16 and a state signal output unit 17 are included.

  The instruction buffer queue IBQ sequentially fetches and stores instructions from a memory (not shown) that stores programs.

  The selector 12 selects an instruction or an interrupt instruction (INTR) stored in the instruction buffer queue IBQ in accordance with a control signal SEL from a control circuit (not shown), and inputs it to the instruction execution unit 13.

  The input control unit 11 controls input of an instruction to the instruction execution unit 13 according to various control signals output from the debug unit 20. That is, when the program is being executed, the instruction stored in the instruction buffer queue IBQ is supplied to the instruction execution unit 13, and when the program execution is stopped, the instruction from the instruction buffer queue IBQ to the instruction execution unit 13 is executed. Stop supplying.

  Further, the input control unit 11 supplies an interrupt command (INTR) to the command execution unit 13 when a valid interrupt request is generated. In response to the interrupt instruction (INTR), the instruction of the interrupt routine is fetched from the memory address indicated by the interrupt vector and stored in the instruction buffer queue IBQ. The input control unit 11 supplies the instruction of the interrupt routine stored in the instruction buffer queue IBQ to the instruction execution unit 13.

  The instruction execution unit 13 executes a series of instructions input via the input control unit 11 in a pipeline manner. For example, in the “PRE-DEC” stage, the instruction execution unit 13 predecodes an instruction input from the instruction buffer queue IBQ, and “DECODE”, “ADDRESS”, “ACCESS1,“ ACCESS2 ”,“ By proceeding in stages with each process of “READ”, “EXE”, “WRITE1”, and “WRITE2”, various operations according to the command are performed. In addition, a plurality of instructions are executed in parallel by independently executing the processing of each stage for the sequentially input instructions.

The instruction execution unit 13 shown in FIG. 1 schematically shows the configuration of the pipeline, and includes registers RA1, RA2,..., RAn and processing circuits U1, U2,. The register RA1 stores data used in the first stage processing of the pipeline for the instruction input from the instruction buffer queue IBQ. The processing circuit U1 executes the first stage processing based on the data stored in the register RA1, and stores the result in the register RA2. The processing circuit U1 executes, for example, “DECODE” stage processing.
Similarly, the register RAi (i indicates an integer from 2 to n) stores the processing result of the (i−1) -th stage of the pipeline, and the processing circuit Ui stores the data stored in the register RAi. Based on this, the i-th stage process is executed.

  In order to avoid various problems (pipeline hazards) associated with two or more instructions being executed in parallel in the pipeline, the pipeline protection unit 14 advances the execution stages of the instructions in the instruction execution unit 13. Control. For example, in order to avoid that the instructions having dependency relations are executed in parallel, the order of execution of instructions is disturbed, and the same hardware is accessed by two or more instructions at the same time. Insert additional cycles (pipeline protection cycles) at each stage of the line. The pipeline protection unit 14 predicts the occurrence of a pipeline hazard based on, for example, the pre-decode result in the “PRE-DEC” stage, and determines a pipeline protection cycle for avoiding the occurrence of the pipeline hazard. Insert into the stage.

  When the input control unit 11 stops inputting an instruction, the signal generation unit 15 generates a stop signal SH indicating the input stop and inputs the stop signal SH to the signal propagation unit 16. For example, the stop signal SH is generated when a HALT event occurs to stop the execution of a program, or when returning from an interrupt that occurred during the stop of the execution of the program and then stopping again.

The signal propagation unit 16 includes a plurality of registers RB1, RB2,.
The registers RB1,..., RBn correspond to the registers RA1,..., RAn (that is, the first stage,. Connected. The first stage register RB1 receives the stop signal SH generated in the signal generation unit 15, and propagates the stop signal SH to the register RB2 in synchronization with the progress of the first stage of the pipeline in the instruction execution unit 13. Similarly, the second and subsequent registers (RB2 to RB2) propagate the stop signal input from the previous stage to the next stage in synchronization with the progress of the corresponding execution stage of the pipeline. For example, when a pipeline protection cycle is inserted at a stage of the pipeline by the pipeline protection unit 14, the propagation period of the stop signal SH in the register corresponding to the stage is also extended.
Registers RB1,..., RBn are an example of a delay unit in the present invention.

In addition to the registers RB1,..., RBn described above, the signal propagation unit 16 includes an extension delay unit 161 that further propagates the stop signal SH output from the final stage.
The extension delay unit 161 extends the propagation period of the stop signal SH for a certain period after the stop signal SH propagates through the registers RB1, RB2,. The propagation period extended by the extended delay unit 16 corresponds to a period during which an associated process can be executed after an instruction is executed by the n-stage pipeline of the instruction execution unit 13.

  For example, the debug unit 20 to be described later generates a HALT event of the instruction processing unit 10 on the condition that the value of data written to the memory and the value of the address match the preset data value and address value, respectively. (Address / data watchpoint described later). This HALT event occurs after the value of data to be written into the memory and the address value of the write destination are determined at the last “WRITE2” stage of the pipeline. That is, even after the execution of instructions in the pipeline is completed, processing such as a HALT event can be executed incidentally. The extension delay unit 16 extends the propagation period of the stop signal SH so that the period in which such ancillary processing is executed is included.

  The extended delay unit 161 may be realized, for example, by adding more registers to the subsequent stage of the registers RB1, RB2,..., RBn, or a fixed delay in the clock cycle of the registers RB1, RB2,. The entire propagation period may be extended for a certain period by providing a circuit for providing

The state signal output unit 17 detects whether or not the stop signal SH generated in the signal generation unit 15 is propagated through the signal propagation unit 16, and outputs the detection result as the state signal S1.
For example, if the stop signal SH is a 1-bit signal and its value is “1”, the status signal output unit 17 sets the value “1” in any of the registers RB1, RB2,. It is detected whether or not the stop signal SH is held. That is, a signal corresponding to the logical sum of the outputs of the registers RB1, RB2,..., RBn and the extended delay unit 161 is output as the status signal S1. Here, as an example, when the status signal S1 is “1”, it indicates that the instruction execution unit 13 has not completed the execution of the pipeline instruction.

[Debug unit 20]
The debugging unit 20 executes a debugging operation related to verification of a program executed by the instruction processing unit 10 in accordance with a command input from a debugging host device (not shown). For example, as a debugging operation, the operation of the instruction processing unit 10 is controlled and the operation state is recorded. An example of a command executed in the debug unit 20 is shown below.

<HALT command>
The instruction processing in the instruction processing unit 10 is stopped.
<STEP command>
The instruction processing unit 10 executes background code (instructions that can be stopped for debugging) one by one.
<RUNC (Conditional Run) command>
The instruction processing unit 10 executes a predetermined number of foreground codes (interrupt routine instructions that are executed even when the background code is stopped during debugging) and background codes. Execute until a HALT event occurs.
<RUNF (Free Run) command>
In the instruction processing unit 10, the foreground code and the background code are executed regardless of the presence or absence of the HALT event.

  In addition to the above-described execution commands, for example, there are the following HALT events generated by the control of the debug unit 20.

<Software Breakpoint>
The debug unit 20 replaces a desired instruction stored in the memory with a debug instruction (such as a stop instruction (ESTOP)) by a DMA function described later. When the instruction processing unit 10 predecodes the stop instruction, the instruction processing unit 10 stops the execution of the program.
<Hardware breakpoint>
When the debug unit 20 monitors the address bus of the program memory and detects that a desired instruction stored in the memory is fetched by the instruction processing unit 10, the debug unit 20 adds a predetermined tag to the instruction. When the instruction processing unit 10 predecodes the tag, the instruction processing unit 10 stops the execution of the program. Hardware breakpoints can be used even when the program memory is a ROM (read only memory) because it is not necessary to rewrite the program on the memory.
<Address / Data Watch Point>
The debug unit 20 monitors the address bus or data bus of the data memory, and when detecting a data value or address value designated in advance, requests the instruction processing unit 10 to stop execution of the program. This HALT event can also be generated when both a desired address value and a data value are detected.
<External trigger watchpoint>
The debug unit 20 monitors an external trigger signal (not shown) designated in advance, and when detecting the trigger signal, requests the instruction processing unit 10 to stop the execution of the program.

  For example, as shown in FIG. 1, the debug unit 20 includes an execution control unit 21, an analysis unit 22, a DMA unit 23, and a debug status register 24 (DBGSTAT).

The execution control unit 21 controls the execution state of the program in the instruction processing unit 10 in accordance with a command input from a host device (not shown) or a watchpoint detection result in the analysis unit 22.
For example, when a command (“HALT”, “RUNC”, etc.) is input from the host device, the execution control unit 21 outputs a request signal EXE_RQ requesting the instruction processing unit 10 to execute the command.
When the analysis unit 22 detects an event that matches the watchpoint condition, the execution control unit 21 refers to the debug status register 24 (DBGSTAT) or the like and executes the execution according to the command input from the host device. It is determined whether the execution condition of the condition and the current instruction satisfies the stop condition of the watchpoint. If the stop condition is satisfied, a request signal WP-RQ that requests the instruction processing unit 10 to stop the execution of the program is sent. Output.
Furthermore, the execution control unit 21 controls the instruction processing unit 10 to accept a predetermined interrupt request even when execution of the program is stopped for debugging. For example, it may not be allowed to stop processing in hardware interrupt control, etc. In debugging a program having such an interrupt processing routine, the interrupt enable signal INT_ENM must be set to an effective state when the program execution is stopped. The interrupt request can be accepted.

On the other hand, the execution control unit 21 accesses the debug state register 24 (DBGSTAT) in which the state of operation of the instruction processing unit 10 (information about the cause of the stop of processing) is stored, and updates the stored information as appropriate.
For example, the execution control unit 21 responds to a HALT event (HALT_ACK).
Is output from the instruction processing unit 10, predetermined flag data (HALT event flag) indicating the cause of program execution stoppage is set in the debug status register 24 (DBGSTAT).

  Further, the execution control unit 21 includes a state machine 211 (EXSM) that indicates an instruction execution state in the instruction processing unit 10. The execution control unit 21 receives various signals (a signal indicating start / stop of instruction decoding, a response signal for a HALT event, a response signal for an interrupt instruction or a return instruction, etc.) output from the instruction processing unit 10 regarding the execution state of the instruction. In response, the state of the state machine 211 (EXSM) is updated.

  The analysis unit 22 monitors access to the memory by the instruction processing unit 10 and a trigger signal from the outside according to preset conditions. For example, in response to a request from the instruction processing unit 10, the analysis unit 22 monitors whether a predetermined value of data has been output to the memory address bus or data bus, or whether a predetermined trigger signal has been input from the outside. Monitor whether.

The analysis unit 22 includes a benchmark counter 221 that counts the counted signal according to the conditions set by the execution control unit 21.
The benchmark counter 221 corresponds to an example of a counter unit in the present invention, and counts various counted signals in accordance with a control signal input from the execution control unit 21 or the like. For example, it indicates the occurrence of various events related to the processing of the instruction processing unit 10 (internal events of the instruction processing unit 10, events such as watchpoints detected by the analysis unit 22, external events such as memory cache misses). A signal, a signal indicating execution of each instruction in the instruction processing unit 10 (for example, execution of decoding of each instruction), a clock signal indicating a reference of operation timing of the instruction processing unit 10, and the like are counted.
The benchmark counter 221 also has a function of initializing a count value when a signal indicating the occurrence of the event described above is input as an initialization signal.
Further, the benchmark counter 221 can select whether or not to execute the count operation or the initialization operation in the transition period in which the state signal S1 indicates the incomplete state of the pipeline processing of the instruction processing unit 10. That is, the benchmark counter 221 determines whether or not to execute the counting of the counted signal described above and whether or not to initialize the count value according to the initialization signal in the transition period when the execution of the program is stopped. Each can be selected. For example, when counting events such as watchpoints, the benchmark counter 221 can count events that occur in the transition period after the occurrence of the HALT event in addition to the normal period in which the HALT event has not occurred. It is. In addition, when counting clock signals, it is possible to stop counting during the transition period. That is, the benchmark counter 221 can select the presence or absence of a counting operation or an initialization operation during the transition period according to the signal to be counted.

A DMA (direct memory access) unit 23 accesses a storage unit to be accessed by the instruction processing unit 10 in accordance with a command input from a host device (not shown), and reads and writes the data. The memory to be accessed by the instruction processing unit 10 includes an internal or external memory, a register group used for instruction processing in the instruction processing unit 10, and the like.
For example, the DMA unit 23 causes the instruction execution unit 13 to execute the debug instruction by replacing a desired instruction stored in the memory with a debug instruction (such as a program stop instruction).
The DMA unit 23 accesses the register group by using the pipeline processing of the instruction execution unit 13 by directly inserting a register read / write request into the decoding pipeline of the instruction execution unit 13.
The DMA unit 23 can also cause the instruction processing unit 10 to execute an arbitrary instruction by inserting further instructions into a series of instructions input to the instruction processing unit 10. In this case, for example, the DMA unit 23 directly writes a desired instruction specified by a command input from the host device to the instruction register of the instruction execution unit 13 (a register for storing the fetched instruction).
Access by the DMA unit 23 may be performed, for example, between accesses by the instruction processing unit 10 or may be performed by stopping access by the instruction processing unit 10.
The DMA unit 23 outputs a request signal DMA_RQ to the instruction processing unit 10 when enabling the DMA access. When a response signal to this request signal is returned from the instruction processing unit 10, the DMA unit 23 validates the access.

  The debug state register 24 (DBGSTAT) stores information on the operation state of the instruction processing unit 10 related to debugging. For example, flag data (HALT event flag) indicating the HALT event that causes the instruction processing unit 10 to stop execution of the program is stored.

  The debug status register 24 (DBGSTAT) stores, for example, the following information.

<HPI (high priority interrupt)>
Flag data indicating that interrupt execution itself is regarded as the highest priority, and other interrupt duplication and debugging operations are limited.
<IDS (interrupt during suspend) _ACT>
Flag data indicating that the previous background code was suspended when an interrupt was accepted.
<DFC (debug frame counter)>
5-bit data indicating the hierarchy of interrupts from the background code. The initial value is “0x1F” (“0x” indicates a hexadecimal number), and is incremented by 1 each time the interrupt hierarchy increases. The debug unit 20 controls the debug request for each interrupt hierarchy by referring to “DFC”.

[Debug restriction unit 30]
When the state signal S1 output from the instruction processing unit 10 indicates an incomplete state of pipeline processing (that is, when the value is “1”), the debug limiting unit 30 continues until the state signal S1 indicates a completed state (that is, the value). The debug operation by the debug unit 20 is limited (until it changes to “0”).

  For example, when the status signal S1 becomes the value “1” due to the occurrence of the HALT event, the debug limiting unit 30 receives an interrupt request or accesses the DMA unit 23 until the status signal S1 changes to “0”. The update of the state of the state machine 211 indicating the execution state of the instruction, the update of the storage information of the debug state register 24 (DBGSTAT), and the execution of commands of the debug unit 20 (HALT, RUNC command, etc.) are restricted.

  The debug restriction unit 30 includes AND circuits 31, 32, 33, and 36, an edge detection circuit 34, and an ACK signal holding circuit 35, for example, as shown in FIG.

  The AND circuit 31 receives the interrupt enable signal INT_EN and the status signal S1 of the execution control unit 21, has a value “0” when the status signal S1 is “1”, and interrupts when the status signal S1 is “0”. An interrupt enable signal INT_ENM having the same value as the enable signal INT_EN is output. The instruction processing unit 10 can accept an interrupt request when the interrupt enable signal INT_ENM output from the AND circuit 31 is “1”, and does not accept an interrupt request when the interrupt enable signal INT_ENM is “0”. . Accordingly, during the period in which the status signal S1 becomes “1” due to the occurrence of the HALT event (the period in which the instruction remaining in the pipeline is not completed), the reception of interrupt requests in the instruction processing unit 10 is limited.

  The AND circuit 32 receives the request signal EXE_RQ and the status signal S1 from the execution control unit 21, has a value “0” when the status signal S1 is “1”, and a request signal when the status signal S1 is “0”. A request signal EXE_RQM having the same value as EXE_RQ is output. When the request signal EXE_RQM output from the AND circuit 32 is “1”, the instruction processing unit 10 receives a request from the execution control unit 21 and executes a command (HALT command, RUNC command, etc.), and the request signal EXE_RQM is If “0”, the command is not executed. Therefore, during the period in which the status signal S1 is “1” due to the occurrence of the HALT event, the stop and restart of the processing of the instruction processing unit 10 under the control of the debugging unit 20 is restricted.

  The AND circuit 33 receives the request signal DMA_RQ and the status signal S1 of the DMA unit 23, has a value “0” when the status signal S1 is “1”, and has a request signal DMA_RQ when the status signal S1 is “0”. A request signal DMA_RQM having the same value as is output. When the request signal DMA_RQM output from the AND circuit 33 is “1”, the instruction processing unit 10 returns a response signal permitting DMA access (access to the memory, etc.), and when the request signal DMA_RQM is “0”. This response signal is not returned. Therefore, access by the DMA unit 23 is restricted during a period in which the status signal S1 is “1” due to the occurrence of the HALT event.

  The edge detection circuit 34 sets the state of the state machine 211 (EXSM) of the execution control unit 21 to “stop state (DSUSP)” at the falling edge where the state signal S1 changes from “1” to “0”. DSUSP_SET is output. That is, when the processing of the instruction remaining in the pipeline of the instruction processing unit 10 is completed, the state of the state machine 211 is updated to “stopped state (DSUSP)”. Therefore, after the HALT event occurs, state update of the state machine 211 (EXSM) indicating the execution state is restricted until the state signal S1 changes from “1” to “0”.

The ACK signal holding circuit 35 holds the response signal HALT_ACK of the HALT event output from the instruction processing unit 10 during the period in which the status signal S1 is “1”. For example, when a HALT event occurs, the command processing unit 10 outputs a pulse “1” as a response signal HALT_ACK. When the status signal S1 is “1”, the ACK signal holding circuit 35 holds the response signal HALT_ACK and outputs “1”. Thereafter, when the status signal S1 becomes “0”, the ACK signal holding circuit 35 releases the holding of the response signal HALT_ACK and outputs “0”.
On the other hand, the AND circuit 36 receives the output signal of the ACK signal holding circuit 35 and the status signal S1, has a value “0” when the status signal S1 is “1”, and the status signal S1 is “0”. In this case, a flag set signal FLG_SET having the same value as the output signal of the ACK signal holding circuit 35 is output.

When the response signal HALT_ACK is held in the ACK signal holding circuit 35 (when the output signal of the ACK signal holding circuit 35 is “1”), when the state signal S1 changes from “1” to “0”, the AND circuit 36 Outputs a flag set signal FLG_SET of “1”. When the ACK signal holding circuit 35 releases the holding of the response signal HALT_ACK by changing the state signal S1 to “0” (when the output signal of the ACK signal holding circuit 35 becomes “0”), the AND circuit 36 outputs a flag set signal. Set FLG_SET to “0”. As a result, the flag set signal FLG_SET once rises from “0” to “1” and returns from “1” to “0” again after one cycle. That is, the flag set signal FLG_SET corresponds to a signal obtained by delaying the pulse of the response signal HALT_ACK only during a period in which the state signal S1 is “1”.
When the flag set signal FLG_SET rises from “0” to “1”, the debug state register 24 (DBGSTAT) updates the storage information (such as the HALT event flag) to reflect the operation state of the instruction processing unit 10 at that time. To do.
Therefore, during the period in which the status signal S1 is “1” due to the occurrence of the HALT event, the update of the stored information in the debug status register 24 (DBGSTAT) is restricted.

Here, an operation at the time of debugging of the processor according to the present embodiment having the above-described configuration will be described.
First, problems when the debug operation is not limited when stopping the execution of the program will be described with reference to FIGS. 2 to 7, and then the operation of the processor according to the present embodiment will be described with reference to FIGS. Will be described with reference to FIG.

FIG. 2 is a diagram illustrating a configuration example of a processor that does not have a function of limiting a debugging operation in a transition period when program execution is stopped.
The processor shown in FIG. 2 includes an instruction processing unit 10X and a debugging unit 20X. The instruction processing unit 10X is obtained by omitting the signal generation unit 15, the signal propagation unit 16, and the state signal output unit 17 in the instruction processing unit 10 described above, and the other configurations are the same as those of the instruction processing unit 10. The debug unit 20X has a logic circuit that updates the state machine 211 and the debug state register 24 (DBGSTAT) after a certain cycle (that is, regardless of completion of pipeline processing) after the response signal HALT_ACK to the HALT event is output. The other configuration is the same as that of the debug unit 20 described above.

<1-1> When a HALT event occurs during the transition period when program execution is stopped

FIG. 3 is a timing chart showing an example of operation when a HALT event (watchpoint) occurs in the transition period when program execution is stopped in the processor shown in FIG.
FIG. 3A shows the clock CLK of the instruction processing unit 10X.
FIG. 3B shows information stored in the debug status register 24 (DBGSTAT).
FIG. 3C shows a state of the state machine 211 (EXSM) (execution state of the instruction processing unit 10X).
FIG. 3D shows a DFC (interrupt hierarchy) stored in the debug status register 24 (DBGSTAT).
3 (E), (F), (G), (H), (I), (J), (K), (L), and (M) respectively represent predecode stages “PRE−” in the pipeline. DEC ", decode stage" DECODE ", address stage" ADDRESS ", access stage" ACCESS1 ", access stage" ACCESS2 ", read stage" READ ", execution stage" EXE ", write stage" WRITE1 ", write stage" WRITE2 " Indicates the instruction to be processed.

  When the instruction processing unit 10X predecodes the software breakpoint stop instruction (ESTOP) (cycle C1), it stops decoding a new instruction and generates a response signal HALT_ACK for this HALT event (cycle C2). Upon receiving this response signal HALT_ACK, the debugging unit 20 sets the HALT event flag of the debug state register 24 (DBGSTAT) and changes the state of the state machine 211 (EXSM) from “execution state (EXE)” to “stop state ( DSUSP) "(cycle C3). At this time, the instruction (N to N-5) decoded before the stop instruction (ESTOP) remains in the instruction execution unit 13 that processes the execution stage of the pipeline. The instruction execution unit 13 executes these instructions sequentially (cycles C3 to C8).

  On the other hand, the analysis unit 22 monitors the access to the memory by the instruction processing unit 10 according to preset conditions. Then, when the state shifts to the “stop state (DSUSP)”, it is detected that an access that matches the condition of the watchpoint is generated by executing the instruction remaining in the pipeline (cycle C9).

  The analysis unit 22 notifies the execution control unit 21X that a watchpoint HALT event has occurred. However, at this time, since the state machine 211 (EXSM) already indicates the “stop state (DSUSP)”, the execution control unit 21X does not output the request signal WP-RQ requesting the program execution stop, and the analysis unit 22 Ignore notifications from. As a result, since the response signal (HALT_ACK) to the HALT event is not output from the instruction processing unit 10X, this HALT event is not set in the debug status register 24 (DBGSTAT). That is, there is a problem that despite the occurrence of a HALT event derived from an instruction decoded before the stop instruction (ESTOP), the fact is not correctly reflected in the debug status register 24 (DBGSTAT).

<1-2> When a HALT event and interrupt occur during the transition period when program execution is stopped

FIG. 4 is a timing diagram showing a first operation example when a HALT event (watchpoint) and an interrupt occur in the transition period when the execution of the program is stopped in the processor shown in FIG.
FIG. 4A shows the clock CLK of the instruction processing unit 10X.
FIGS. 4B and 4C respectively show buses FDBUS and EDBUS for saving information (status information) on the operation state of the instruction processing unit 10X to the stack at the time of an interrupt.
FIG. 4D shows the bus DBGSBUS to which the stored information of the debug status register 24 (DBGSTAT) is output.
FIG. 4E shows a signal SAVEESTS that becomes “1” when the information stored in the debug status register 24 (DBGSTAT) is saved in the stack.
FIG. 4F shows a response signal RINTACK output from the instruction processing unit 10X when an interrupt is accepted in the stopped state.
FIG. 4G shows a signal PUSHSTRT that becomes “1” at the start of the operation of saving the status information of the instruction processing unit 10X in the stack.
FIG. 4H shows information stored in the debug status register 24 (DBGSTAT).
FIG. 4I shows flag data DBGM that becomes “1” when the debugging operation during program execution is limited.
FIG. 4J shows flag data HPI that becomes “1” when another interrupt is overlapped or a debug operation is restricted by a high-priority interrupt.
FIG. 4K shows flag data IDS_ACT that becomes “1” when the immediately preceding background code is suspended when an interrupt is accepted.
FIG. 4L shows a state of the state machine 211 (EXSM) (execution state of the instruction processing unit 10X).
4 (M) shows 5-bit data (DFC) indicating the hierarchy of interrupts from the background code. FIG. 4 (N), (O), (P), (Q), (R), ( S), (T), (U), and (V) are pipeline stages “PRE-DEC”, “DECODE”, “ADDRESS”, “ACCESS1”, “ACCESS2”, “READ”, “EXE, respectively. ”,“ WRITE1 ”, and“ WRITE2 ”indicate instructions to be processed.

  When the instruction processing unit 10X predecodes the software breakpoint stop instruction (ESTOP) (cycle C51), it stops decoding a new instruction and generates a response signal HALT_ACK for this HALT event (cycle C52). The debug unit 20X receives the response signal HALT_ACK, sets the HALT event flag of the debug state register 24 (DBGSTAT), and changes the state of the state machine 211 (EXSM) from “execution state (EXE)” to “stop state ( DSUSP) "(cycle C53). At this time, the instruction (N to N-5) decoded before the stop instruction (ESTOP) remains in the instruction execution unit 13 that processes the execution stage of the pipeline. The instruction execution unit 13 executes these instructions sequentially (cycles C53 to C58).

  When executing the instruction remaining in the pipeline, the instruction processing unit 10X receives an interrupt request that has priority over the debug operation (cycle C53). In response to this interrupt request, the instruction processing unit 10X outputs a response signal RINTACK (cycle C54). Upon receiving this response signal RINTACK, the debugging unit 20X updates the state machine 211 (EXSM) from “suspended state (DSUSP)” to “interrupt state suspended (IDS)” (cycle C55).

The instruction processing unit 10X starts processing for storing information such as the status registers (ST0 to ST2) in the stack in response to acceptance of the interrupt. That is, when receiving an interrupt request, the instruction processing unit 10X outputs information on a predetermined register stored in the stack to the bus (cycles C60 to C62). In the example of FIG. 4, information stored in the status registers ST0 to ST2 indicating the operating state of the instruction processing unit 10X, the program counters PCH and PCL (not shown), and the debug status register 24 (DBGSTAT) of the debugging unit 20X are respectively buses. Output to. Further, the instruction processing unit 10X sets storage information (such as status register flag data DBGM) in each register to an initial value before starting an interrupt routine.
The debugging unit 20X increases the data (DFC) of the interrupt hierarchy by “1” when the above-described storage process is started in the instruction processing unit 10X (cycle C59). Then, at the time when the save processing of the debug status register 24 (DBGSTAT) is performed (cycle C61), all the HALT event flags are cleared, and the flag data HPI and IDS_ACT are set to “1”, respectively.

  On the other hand, the analysis unit 22 monitors the access to the memory by the instruction processing unit 10 according to preset conditions. Then, when a transition to the “suspended interrupt state (IDS)” state occurs due to the above-described interrupt, it is detected that an access that matches the watchpoint condition has occurred due to the execution of the instruction remaining in the pipeline (cycle) C57).

  When the execution control unit 21X is notified of the watchpoint HALT event from the analysis unit 22, the execution control unit 21X is not in the “stop state (DSUSP)” state at this time, and therefore issues a request signal WP-RQ requesting the program execution stop. The data is output to the processing unit 10X (cycle C57). The instruction processing unit 10X that has received the request signal WP-RQ outputs a response signal HALT_ACK to the debugging unit 20X (cycle C58). Receiving the response signal HALT_ACK from the instruction processing unit 10X, the debug unit 20X sets the HALT event flag of the debug state register 24 (DBGSTAT) and sets the state of the state machine 211 (EXSM) to “stopped interrupt state (IDS). ) ”Again to“ stop state (DSUSP) ”(cycle C59).

As described above, the state of the state machine 211 (EXSM) is “stopped” when the interrupt instruction (foreground code) is moved as a result of the overlap of the interrupt instruction and the HALT event in the transition period when the program execution is stopped. State (DSUSP) "(cycle C59-). The instruction processing unit 10X stops instruction processing from the beginning of the interrupt routine according to this state (cycle C63). That is, there arises a problem that a HALT event derived from an instruction (background code) decoded before accepting an interrupt request stops execution of the instruction in the interrupt routine (foreground code).
In this case, since the HALT event flag of the debug status register 24 (DBGSTAT) is all cleared at the same time as the saving process associated with the interrupt is performed, the execution of the program is stopped in response to the HALT event. Information indicating the cause is not recorded in the debug status register 24 (DBGSTAT). As a result, there arises a problem that the cause of the program execution stoppage cannot be grasped in the host device.

  FIG. 5 is a timing chart showing a second operation example when a HALT event (watchpoint) and an interrupt are generated in the transition period when program execution is stopped in the processor shown in FIG. FIGS. 5A to 5V correspond to FIGS. 4A to 4V, respectively.

  In the second operation example shown in FIG. 5, the generation time point of the HALT event by the watchpoint is delayed by three cycles compared to the first operation example shown in FIG. 4. The operations from the cycles C101 to C106 are the same as the cycles C51 to C56 in FIG.

The execution control unit 21X first increases the interrupt hierarchy data (DFC) stored in the debug status register 24 (DBGSTAT) by “1” in response to the interrupt instruction received in cycle C103 (cycle C109).
Next, the instruction processing unit 10X outputs information on a predetermined register stored in the stack to the bus (cycles C110 to 112).
Thereafter, the instruction processing unit 10X clears the storage information of each register in order to start the interrupt routine (cycle C111). At this time, the debug unit 20X clears all the HALT event flags in the debug status register 24 (DBGSTAT), and sets the flag data HPI and IDS_ACT to “1”, respectively.

  On the other hand, the analysis unit 22 monitors the access to the memory by the instruction processing unit 10 according to preset conditions. Then, when status information is stored in the stack in the “interrupt state (IDS) being stopped”, it is detected that an access that matches the condition of the watchpoint has occurred due to execution of an instruction remaining in the pipeline ( Cycle C110).

When notified of the watchpoint HALT event from the analysis unit 22, the execution control unit 21X outputs a request signal WP-RQ requesting the instruction processing unit 10X to stop executing the program (cycle C110). Upon receiving the request signal WP-RQ, the instruction processing unit 10X outputs a response signal HALT_ACK to the request processing unit 10X (cycle C111). Receiving the response signal HALT_ACK from the instruction processing unit 10X, the debug unit 20X sets the HALT event flag of the debug state register 24 (DBGSTAT) and sets the state of the state machine 211 (EXSM) to “stopped interrupt state (IDS). ) "To" stop state (DSUSP) "(cycle C112).

  At the time of cycle C111, the information stored in the debug status register 24 (DBGSTAT) is cleared in preparation for the interrupt routine, but the debug unit 20X has cleared the information in response to the HALT event that occurred during the transition period. The debug status register 24 (DBGSTAT) is rewritten. That is, there arises a problem that information stored in the debug status register 24 (DBGSTAT) is rewritten as if the HALT event that occurred before the occurrence of the interrupt occurred in the interrupt routine.

<1-3> When a HALT event occurs during the transition period when returning from the interrupt routine and stopping the program

FIG. 6 is a timing chart showing an example of operation when a HALT event occurs in the transition period when returning from the interrupt routine and stopping the program in the processor shown in FIG.
FIG. 6A shows the clock CLK of the instruction processing unit 10X.
FIGS. 6B and 6C respectively show buses CDBUS and DDBUS for returning the status information of the instruction processing unit 10X stored in the stack to a predetermined register when returning from the interrupt.
FIG. 6D shows a signal RE-DSTAT that becomes “1” when information is returned from the stack to the debug status register 24 (DBGSTAT).
FIG. 6E shows a response signal RETIACK output by the instruction processing unit 10X in response to a return instruction from an interrupt.
FIG. 6F shows a signal POPEND that becomes “1” at the end of the operation of returning the status information from the stack to a predetermined register.
FIG. 6G shows information stored in the debug status register 24 (DBGSTAT).
FIG. 6H shows flag data DBGM that becomes “1” when the debugging operation during program execution is limited.
FIG. 6I shows flag data HPI that is set to “1” when duplication of other interrupts or a debug operation is restricted by an interrupt having a high priority.
FIG. 6J shows flag data IDS_ACT that becomes “1” when the immediately preceding background code is suspended when an interrupt is accepted.
FIG. 6K shows the state of the state machine 211 (EXSM) (execution state of the instruction processing unit 10X).
FIG. 6 (L) shows 5-bit data (DFC) indicating the hierarchy of interrupts from the background code. FIG. 6 (M), (N), (O), (P), (Q), ( R), (S), (T), and (U) are pipeline stages “PRE-DEC”, “DECODE”, “ADDRESS”, “ACCESS1”, “ACCESS2”, “READ”, “EXE, respectively. ”,“ WRITE1 ”, and“ WRITE2 ”indicate instructions to be processed.

When the instruction processing unit 10X predecodes the return instruction (RTI-R) in the interrupt routine (cycle C152), the instruction processing unit 10X stops decoding the new instruction and outputs the response signal RETIACK (cycle C153). Then, the information stored in the stack before the execution of the interrupt routine is output to the buses CDBUS and DDBUS and returned to a predetermined register.
When the stack information is returned to the debug status register 24 (DBGSTAT), the flag data HPI and IDS_ACK stored therein return to the state before the interrupt, that is, the value “0” (cycle C159). The data (DFC) indicating the interrupt hierarchy is incremented by “1” before being stored in the stack, so that the execution control unit 21X returns “DFC” after the stack information is returned to a predetermined register. “1” is subtracted from the value of (cycle C160).
The flag data DBGM is stored in a register (for example, status register ST2) different from the debug status register 24 (DBGSTAT), and the state before the interrupt (value “0”) is delayed from the flag data HPI, IDS_ACT. (Cycle C161).

  The debug unit 20X updates the state of the state machine 211 (EXSM) to “stop state (DSUSP)” when returning the information stored in the stack to the register.

  On the other hand, the analysis unit 22 monitors the access to the memory by the instruction processing unit 10 according to preset conditions. Then, immediately before the status information is returned from the stack to the register, it is detected that an access that matches the watchpoint condition has occurred due to the execution of the instruction remaining in the pipeline of the instruction execution unit 13 (cycle C156).

  When notified of the watchpoint HALT event from the analysis unit 22, the execution control unit 21X outputs a request signal WP-RQ requesting the instruction processing unit 10X to stop the execution of the program (cycle C156). Upon receiving the request signal WP-RQ, the instruction processing unit 10X outputs a response signal HALT_ACK to the request processing unit 10X (cycle C157). Receiving the response signal HALT_ACK from the instruction processing unit 10X, the debug unit 20X sets the HALT event flag of the debug state register 24 (DBGSTAT) and sets the state of the state machine 211 (EXSM) to “stopped interrupt state (IDS). ) "To" stop state (DSUSP) "(cycle C158).

  Here, the HALT event flag set so as to indicate the occurrence of the watchpoint HALT event in cycle C158 is rewritten by the information returned from the stack in cycle C159 immediately thereafter. For this reason, there is a problem that the fact that the HALT event has occurred cannot be grasped even though the watchpoint is purposely set.

<1-4> Access to the DMA unit 23 occurs when the debug frame (interrupt hierarchy) changes due to an interrupt

When the debug frame (interrupt hierarchy) is changed by an interrupt instruction, the status information of the instruction processing unit 10X stored in the debug status register 24 (DBGSTAT) or the like is not updated all at once but is partially different. Updated with timing. Therefore, when a memory access request (for example, a register value read instruction) generated by the function of the DMA unit 23 is executed at the transition of the debug frame and the status information of the instruction processing unit 10X is read out, There is a problem that there is no correlation between information.

For example, in cycle C55 of FIG. 4, the execution state (EXSM) of the instruction processing unit 10X is “stopped interrupt state (IDS)”. In this case, the value of “DFC” indicating the interrupt hierarchy is The values of “0x00”, flag data DBGM, HPI, and IDS_ACT must be “1”. However, in actuality, as shown in FIG. 4, the value of “DFC” is “0x1F”, the values of flag data DBGM, HPI, and IDS_ACT are “0”, respectively. The state is not supported.
In such a case, when the DMA unit 23 reads the status information stored in the debug status register 24 (DBGSTAT) or the like, useless information that is meaningless in debugging work is presented to the user.

<1-5> When the command of the debug unit 20X is executed during the transition period when program execution is stopped

When, for example, a RUNC command is issued by the debug unit 20X during the transition period when program execution is stopped, the following problem occurs.
In this case, the instruction processing unit 10X resumes execution of the program in response to the RUNC command, and the state of the state machine 211 (EXSM) changes from “stopped state (DSUSP)” to “executed state (EXE)”. This state change may occur in the middle of the transition period. In this case, a HALT event (for example, an address / data watch) caused by an instruction already being processed in the instruction processing unit 10X before the state change time. Point) may occur after a state change. If such a HALT event occurs, the state of the instruction processing unit 10X returns from the “execution state (EXE)” to the “stop state (DSUSP)” again.
Here, the HALT event that has caused the processing of the instruction processing unit 10X to stop is an event derived from an instruction that has already been processed by the instruction processing unit 10X before issuing the RUNC command. Not included in the stop condition. That is, there is a problem that the instruction processing unit 10X is stopped by a stop instruction that is not included in the stop condition of the RUNC command.

Further, in the transition period when returning from the interrupt routine and stopping the program (see FIG. 6), for example, when the RUNNC command is issued by the debug unit 20X, the following problem occurs.
In the cycles C158 to C159 in the example of FIG. 6, the value of “DFC” (FIG. 6 (L)) indicating the hierarchy of the debug frame is “0x00”, indicating the foreground code, but the state machine 211 ( The state of EXSM) (FIG. 6K) is “stopped state (DSUSP)” and indicates a background code. That is, in the cycles C158 to C159, the debug frame boundaries are overlapped.
If the RUNC command is issued before cycle C158, the state of the state machine 211 (EXSM) is in the “interrupt state (IDS) being stopped”, so it is unnecessary to instruct the start of execution in the already executed state. RUNC command is ignored.
However, when the RUNC command is issued in cycles C158 to C159, since the state is in the “stop state (DSUSP)”, the request signal EXE_RQ of the RUNC command is effectively accepted by the instruction processing unit 10X. Then, when returning to the background code, the instruction processing unit 10X becomes “execution state (EXE)” and the program is executed as it is.
Here, since the RUNC command received by the instruction processing unit 10X in the cycles C158 to C159 is a command issued to the foreground code (DFC = “0x00”), the processing of the background code is inherently performed. Should not affect execution. That is, there is a problem that an execution command issued in the debug unit 20X is executed in an unintended debug frame.

<1-6> When a HALT event occurs after accepting an interrupt when program execution is stopped

For example, when performing write access to an external memory or the like with a slow access speed, when the pipeline protection unit 14 inserts a pipeline protection cycle, the instruction processing unit 10X temporarily stops the progress of the pipeline processing “stall” It becomes a state called.
If an interrupt occurs during the transition period when instruction processing in the instruction processing unit 10X is stopped, and the above stall occurs during the transition period, the interrupt is affected by the suspension of pipeline processing due to the stall. Execution of saving processing to the stack is delayed. If this delay becomes longer than a certain level, the first or second instruction of the interrupt routine is predecoded before executing the saving process to the stack.
Here, if the first or second instruction of the interrupt routine is a software breakpoint stop instruction (ESTOP), or if a hardware breakpoint is set for those instructions, it is enabled by executing predecode. A HALT event occurs. When a HALT event occurs, the HALT event flag of the debug status register 24 (DBGSTAT) corresponding to this HALT event is set.
However, if the saving process to the stack is performed after setting the HALT event flag, the HALT event flag is cleared to the initial value when the saving process is completed. When the process proceeds to the interrupt routine, the instruction processing unit 10X is correctly stopped, but the HALT event flag of the debug status register 24 (DBGSTAT) is cleared to the initial value, so why the instruction processing unit 10X is stopped? I cannot know the cause. That is, program execution is stopped in the interrupt routine, but the HALT event is considered to have occurred before accepting the interrupt, and the debug status register 24 (DBGSTAT) correctly indicates the reason for execution stop. The problem that cannot be done.

  FIG. 7 is a timing chart showing an example of operation in the processor shown in FIG. 2 when an interrupt occurs during a transition period when program execution is stopped and the top of the interrupt routine is a stop instruction (ESTOP). It is. FIGS. 7A to 7V correspond to FIGS. 4A to 4V, respectively.

When the instruction processing unit 10X predecodes a software breakpoint stop instruction (ESTOP) (cycle C175), the instruction processing unit 10X stops decoding a new instruction and generates a response signal HALT_ACK for this HALT event (cycle C176). Upon receiving this response signal HALT_ACK, the debugging unit 20X sets the HALT event flag of the debug state register 24 (DBGSTAT), and changes the state of the state machine 211 (EXSM) from “execution state (EXE)” to “stop state ( DSUSP) "(cycle C177). The instruction execution unit 13 sequentially executes instructions (N to N-5) decoded before the stop instruction (ESTOP) (cycles C177 to C187).
However, when the instruction “N” shifts to the write stage “WRITE1” in the cycle C181, the external memory has not completed the previous access, and therefore writing by the instruction “N” cannot be executed. Therefore, the pipeline protection unit 14 inserts a pipeline protection cycle and puts the pipeline into a stalled state until the write stage “WRITE1” of the instruction “N” is completed (cycles C182 to C186).

On the other hand, the instruction processing unit 10X accepts an interrupt request that has priority over the debugging operation in the transition period when the program is stopped (cycle C177). In response to this interrupt request, the instruction processing unit 10X outputs a response signal RINTACK (cycle C178). Upon receiving this response signal RINTACK, the debugging unit 20X updates the state machine 211 (EXSM) from “stop state (DSUSP)” to “stopped interrupt state (IDS)” (cycle C179).
Upon receiving the interrupt request, the instruction processing unit 10X executes processing for saving the status register (ST0 to ST2) in the stack (cycles C187 to C191). However, since the pipeline stall occurs as described above, the saving process to the stack is delayed. As can be seen by comparing FIG. 7G and FIG. 4G, when a stall occurs, the rising point of the signal PUSHSTRT is delayed by that period (5 cycles).

  While the saving process to the stack is delayed due to the occurrence of the stall, the instruction processing unit 10X predecodes the first instruction of the interrupt routine (cycle C187). Here, since the predecoded instruction is a software breakpoint stop instruction (ESTOP), the instruction processing unit 10X generates a response signal HALT_ACK for this HALT event (cycle C188). Upon receiving this response signal HALT_ACK, the debugging unit 20X sets the HALT event flag of the debug state register 24 (DBGSTAT) and changes the state of the state machine 211 (EXSM) from “suspended interrupt state (IDS)” to “ Update to “stop state (DSUSP)” (cycle C189).

  When the pipeline processing is resumed due to the removal of the stall, the instruction processing unit 10X saves the information of the debug status register 24 (DBGSTAT) rewritten according to the stop instruction (ESTOP) at the head of the interrupt routine to the stack and performs debugging. The status register 24 (DBGSTAT) is cleared to the initial value (cycles C189 to C190). When the process proceeds to the interrupt routine, the instruction processing unit 10X enters the “stop state (DSUSP)”. However, the debug status register 24 (DBGSTAT) is cleared to the initial value and does not correctly indicate the cause of the execution stop.

<1-7> When stopping execution of a program while the benchmark counter 221X is counting

  The benchmark counter 221X included in the analysis unit 22 is a variety of events related to the processing of the instruction processing unit 10X (internal events of the instruction processing unit 10X, watch detected by the analysis unit 22) according to the conditions set by the execution control unit 21X. Counts signals indicating the occurrence of events such as points and external events such as memory cache misses. However, in the processor shown in FIG. 2, when the execution of the program is stopped, even if unprocessed instructions remain in the pipeline, the benchmark is executed after a certain period from the time when the HALT event for stopping the execution of the program occurs. The counter 221X stops counting. For this reason, an event (for example, a watchpoint) derived from an instruction remaining before the occurrence of the HALT event remaining in the pipeline is excluded from the count target and is not reflected in the count result.

  Next, the debugging operation of the processor according to this embodiment shown in FIG. 1 will be described.

<2-1> When a HALT event occurs during the transition period when program execution is stopped

FIG. 8 is a timing chart showing an example of an operation when a HALT event (watchpoint) occurs in the transition period when program execution is stopped in the processor shown in FIG. 1 according to the present embodiment.
FIG. 8A shows the clock CLK.
FIG. 8B shows information stored in the debug status register 24 (DBGSTAT).
FIG. 8C shows the state of the state machine 211 (EXSM) (execution state of the instruction processing unit 10).
FIG. 8D shows a DFC (interrupt hierarchy) stored in the debug status register 24 (DBGSTAT).
8 (E), (F), (G), (H), (I), (J), (K), (L), and (M) are respectively “PRE-DEC”, The instructions processed in “DECODE”, “ADDRESS”, “ACCESS1”, “ACCESS2”, “READ”, “EXE”, “WRITE1”, and “WRITE2” are shown.
FIG. 8N shows the pipeline stage “WRITE3” added in the extended delay unit 161.
FIG. 8 (O) shows the status signal S1.

  When the instruction processing unit 10 predecodes a software breakpoint stop instruction (ESTOP) (cycle C201), the instruction processing unit 10 stops decoding of a new instruction and generates a response signal HALT_ACK for this HALT event (cycle C202).

  When the decoding of a new instruction is stopped by the stop instruction (ESTOP) (that is, the input of the instruction is stopped in the input control unit 11), the signal generation unit 15 generates a stop signal SH and sends it to the signal propagation unit 16. input. The registers RB1, RB2,... Of the signal propagation unit 16 sequentially propagate the stop signal SH to the subsequent stage in synchronization with the progress of the instruction execution stage in the instruction execution section 13 (that is, in accordance with the progress of the pipeline processing). When the signal propagation unit 16 detects that the stop signal SH is being propagated, the state signal output unit 17 outputs the state signal S1 having a value “1” (cycles C202 to C210). The status signal S1 having a value “1” indicates that the instruction execution unit 13 has not yet executed the instruction.

Since the propagation of the stop signal SH in the signal propagation unit 16 is synchronized with the progress of the pipeline processing, the stop signal SH can be regarded as one instruction. In FIG. 8, “HALT” flowing through the pipeline stage indicates the stop signal SH.
The pipeline stage through which the “HALT” (stop signal SH) passes includes a “WRITE3” stage in addition to the normal pipeline stage. The “WRITE3” stage is a stage generated by the extended delay unit 161, and the state signal S1 is “ 1 ”.

  When the status signal S <b> 1 is “1”, the response signal HALT_ACK of the HALT event output from the instruction processing unit 10 is held by the ACK signal holding circuit 35. When the status signal S1 changes from “1” to “0” (cycle C211), the response signal HALT_ACK held in the ACK signal holding circuit 35 passes through the AND circuit 36 and is input to the execution control unit 21 as the flag set signal FLG_SET. Is done. The execution control unit 21 receives this flag set signal FLG_SET, and sets the HALT event flag of the debug status register 24 (DBGSTAT) (cycle C212). That is, when a HALT event such as a software breakpoint (ESTOP) occurs, the status signal S1 becomes “1”, and the instruction execution in the instruction execution unit 13 is completed until the status signal S1 changes to “0”. Until the debug status register 24 (DBGSTAT) is updated with the HALT event.

When the state signal S1 changes from “1” to “0”, the edge detection circuit 34 outputs a signal DSUSP_SET, and the state of the state machine 211 (EXSM) of the execution control unit 21 is set to “stop state (DSUSP)”. Set to. That is, when a HALT event such as a software breakpoint (ESTOP) occurs, the state of the state machine 211 (EXSM) is not immediately updated to “stop state (DSUSP)”, and the state signal S1 changes to “0”. State updates are delayed until

  On the other hand, the analysis unit 22 monitors access to the memory by the instruction processing unit 10 and a trigger signal from the outside according to preset conditions. Then, after the decoding of a new instruction is stopped by inputting a stop instruction (ESTOP), it is detected that an access that matches the watchpoint condition is generated by executing the instruction remaining in the pipeline (cycle C209).

  When the execution control unit 21 is notified of the watchpoint HALT event from the analysis unit 22, the execution control unit 21 is not in the “stop state (DSUSP)” state at this time, and therefore issues a request signal WP-RQ requesting the program execution stop. Output to the processing unit 10. Upon receiving the request signal WP-RQ, the instruction processing unit 10 outputs a response signal HALT_ACK to the debugging unit 20 (cycle C210). However, since the status signal S1 is “1” at this time, the response signal HALT_ACK is held by the ACK signal holding circuit 35 as in the case of the previous stop instruction (ESTOP). The update of the debug status register 24 (DBGSTAT) in response to the watchpoint HALT event is also delayed until the status signal S1 becomes “0” (cycle C212). As a result, in the cycle C212, the flag of the debug status register 24 (DBGSTAT) is set for two HALT events (stop instruction (ESTOP), watchpoint).

In the processor shown in FIG. 2, updating of the debug state register 24 (DBGSTAT) and the state machine 211 (EXSM) is permitted during a transition period when program execution is stopped. Therefore, as described in <1-1>, when a HALT event such as a watchpoint occurs during the transition period, there is a problem that the information is not correctly recorded in the debug status register 24 (DBGSTAT).
On the other hand, in the processor shown in FIG. 1 according to the present embodiment, the information on the HALT event generated during the transition period is debugged by restricting the update of the debug state register 24 (DBGSTAT) and the state machine 211 (EXSM) during the transition period. It is correctly recorded in the status register 24 (DBGSTAT), and the above problem is solved.

<2-2> When a HALT event and interrupt occur during the transition period when program execution is stopped

FIG. 9 is a timing chart showing an operation example when an interrupt occurs in the transition period when the execution of the program is stopped in the processor shown in FIG. 1 according to the present embodiment.
FIG. 9A shows the clock CLK of the instruction processing unit 10.
FIG. 9B shows a response signal RINTACK output from the instruction processing unit 10 when an interrupt is accepted in the stopped state.
FIG. 9C shows the state of the state machine 211 (EXSM) (execution state of the instruction processing unit 10).
FIG. 9D shows 5-bit data (DFC) indicating the hierarchy of interrupts from the background code. FIG. 9E shows storage information in the debug status register 24 (DBGSTAT).
FIG. 9F shows the status signal S1.
9 (G), (H), (I), (J), (K), (L), (M), (N), and (O) are pipeline stages “PRE-DEC”, respectively. , “DECODE”, “ADDRESS”, “ACCESS1”, “ACCESS2”, “READ”, “EXE”, “WRITE1”, and “WRITE2”.
FIG. 9P shows the pipeline stage “WRITE3” extended in the extended delay unit 161.

  When the instruction processing unit 10 predecodes the software breakpoint stop instruction (ESTOP) (cycle C251), it stops decoding a new instruction and generates a response signal HALT_ACK for this HALT event (cycle C252).

  When the decoding of a new instruction is stopped by the stop instruction (ESTOP), the signal generation section 15 generates a stop signal SH and inputs it to the signal propagation section 16. While the stop signal SH is propagated through the signal propagation unit 16, the state signal output unit 17 outputs a state signal S1 having a value “1” indicating that the instruction execution in the instruction execution unit 13 is not completed ( Cycles C252 to C260).

  When the status signal S1 is “1”, the response signal HALT_ACK output from the instruction processing unit 10 is held by the ACK signal holding circuit 35. When the status signal S1 changes from “1” to “0” (cycle C261), the response signal HALT_ACK held in the ACK signal holding circuit 35 passes through the AND circuit 36 and is input to the execution control unit 21 as the flag set signal FLG_SET. Is done. The execution control unit 21 receives this flag set signal FLG_SET and sets the HALT event flag of the debug status register 24 (DBGSTAT) (cycle C262).

  When the state signal S1 changes from “1” to “0”, the edge detection circuit 34 outputs the signal DSUSP_SET, and the state of the state machine 211 (EXSM) of the signal execution control unit 21 is set to “stop state (DSUSP)”. ”(Cycle C262).

  The above operations are the same as those in FIG. 8, and the debug restriction unit 30 updates the debug state register 24 (DBGSTAT) and the state machine 211 (EXSM) until the instruction execution by the instruction execution unit 13 is completed. Limit.

On the other hand, unlike the case of FIG. 8, in the operation example of FIG. 9, an interrupt request is generated after transitioning to the “stop state (DSUSP)” by the HALT event of the stop instruction (ESTOP) (cycle C253). When an interrupt request is generated, the status signal S1 is set to “1”, and the interrupt enable signal INT_ENM output from the AND circuit 31 is set to “0”. Therefore, the interrupt request is not accepted by the instruction processing unit 10 and enters a standby state (cycles C253 to C261). When the status signal S1 changes from “1” to “0”, the masking of the interrupt enable signal INT_EN by the AND circuit 31 is released, so that the instruction processing unit 10 receives an interrupt request in a standby state (cycle C262).
As described above, in the processor shown in FIG. 1, the acceptance of interrupt requests is limited until the execution of instructions in the instruction execution unit 13 is completed.

FIG. 10 is a timing chart showing a first operation example when a HALT event (watchpoint) and an interrupt occur in a transition period when program execution is stopped in the processor shown in FIG. 1 according to the present embodiment. is there.
10A to 10V correspond to FIGS. 4A to 4V, respectively.
FIG. 10 (W) shows the pipeline stage “WRITE 3” extended in the extended delay unit 161.
FIG. 10X shows the status signal S1.

  The instruction processing unit 10 stops decoding of a new instruction in response to the stop instruction (ESTOP), and sets the status signal S1 to “1” (cycles C301 and C302). The debug restriction unit 30 restricts updating of the debug state register 24 (DBGSTAT) and the state machine 211 (EXSM) in response to the stop instruction (ESTOP) by the debug unit 20 while the state signal S1 is “1” (cycle C302). ~ C311). Further, an interrupt request (cycle C303) generated during this period is set to a standby state. The above operation is the same as in the case of FIG.

  On the other hand, in the operation example of FIG. 10, unlike the case of FIG. 9, a watchpoint HALT event further occurs in the transition period after the decoding of the instruction is stopped (cycle C307).

  When the analysis unit 22 detects an access that matches the watchpoint condition, the analysis unit 22 notifies the execution control unit 21 to that effect. At this time, since the state machine 211 (EXSM) does not indicate “stop state (DSUSP)”, the execution control unit 21 outputs a request signal WP-RQ requesting the program execution stop to the instruction processing unit 10 (cycle C307). ). Upon receiving the request signal WP-RQ, the instruction processing unit 10 outputs a response signal HALT_ACK to the debugging unit 20 (cycle C308). However, since the status signal S1 is “1” at this time, the response signal HALT_ACK is held by the ACK signal holding circuit 35 as in the case of the previous stop instruction (ESTOP). The update of the debug status register 24 (DBGSTAT) in response to the watchpoint HALT event is also delayed until the cycle C312 in which the status signal S1 becomes “0”. As a result, in the cycle C312, the debug status register 24 (DBGSTAT) is set for two HALT events (stop instruction (ESTOP), watchpoint).

When the status signal S1 changes from “1” to “0”, the instruction processing unit 10 releases the restriction on acceptance of interrupt requests by the AND circuit 31 of the debug restriction unit 30. Is received (cycle C312).
When receiving an interrupt request, the instruction processing unit 10 outputs a response signal RINTACK (cycle C313). Upon receiving this response signal RINTACK, the debugging unit 20 updates the state machine 211 (EXSM) from “suspended state (DSUSP)” to “interrupted state suspended (IDS)” (cycle C314).
The instruction processing unit 10 starts processing for storing information such as status registers (ST0 to ST2) in the stack in response to acceptance of an interrupt. That is, when receiving an interrupt request, the instruction processing unit 10 outputs information on a predetermined register stored in the stack to the buses FDBUS and EDBUS (cycles C319 to C321). Then, before starting the interrupt routine, the storage information of each register is cleared (cycle C320).
When the saving process to the stack is started, the debugging unit 20 increases the data (DFC) of the interrupt hierarchy by “1” (cycle C318). The flag data HPI and IDS_ACT are set to “1” at the time (cycle C320) when the debug status register 24 (DBGSTAT) is stored.

  When the process proceeds to the interrupt routine (foreground code) through the above processing, the state of the state machine 211 (EXSM) is “interrupt state (IDS) being stopped” (cycle C322). Therefore, the instruction processing unit 10 normally executes the instruction of the interrupt routine from the beginning without stopping as in the case of FIG. 4 (cycle C322).

In the processor shown in FIG. 2, the acceptance of the interrupt request is permitted in the transition period when the execution of the program is stopped. Therefore, if the interrupt request and the HALT event overlap in the transition period, as described with reference to FIG. 4 in <1-2>, an instruction (background code) decoded before accepting the interrupt request. This causes a problem that the HALT event generated from the above affects the execution of instructions in the interrupt routine (foreground code).
On the other hand, in the processor shown in FIG. 1 according to the present embodiment, by limiting the acceptance of interrupt requests during the transition period, the processing associated with the HALT event that occurred during the transition period overlaps with the processing when transitioning to the interrupt routine Is avoided. As a result, the HALT event before the transition to the interrupt routine does not affect the execution state of the process after the transition to the interrupt routine, and the above problem is solved.

  FIG. 11 is a timing chart showing a second operation example when a HALT event (watchpoint) and an interrupt occur in the transition period when program execution is stopped in the processor shown in FIG. 1 according to the present embodiment. is there. FIGS. 11A to 11X correspond to FIGS. 10A to 10X, respectively.

The second operation example shown in FIG. 11 is different from the first operation example shown in FIG. 10 in that the occurrence point of the HALT event by the watchpoint is delayed by three cycles. However, in the second operation example as well, in the same way as in the case of FIG. 10, the acceptance of interrupt requests in the transition period is limited, so that the overlap of HALT events and interrupts in this period is avoided. Therefore, the problem that the HALT event generated before the transition to the interrupt routine affects the execution state after the transition to the interrupt routine is solved.
Further, since the HALT event and the interrupt are prevented from overlapping in the transition period, the HALT event before the transition to the interrupt routine is shifted to the interrupt routine as described with reference to FIG. 5 in <1-2>. The problem of affecting the contents of the later debug status register 24 (DBGSTAT) is also solved.

<2-3> When a HALT event occurs during the transition period when returning from the interrupt routine and stopping the program

FIG. 12 is a timing chart showing an example of an operation when a HALT event occurs in the transition period when returning from the interrupt routine and stopping the program in the processor shown in FIG. 1 according to the present embodiment.
FIGS. 12A to 12U correspond to FIGS. 6A to 6U, respectively.
FIG. 12 (V) shows the pipeline stage “WRITE 3” extended in the extended delay unit 161.
FIG. 12 (W) shows the status signal S1.

When the instruction processing unit 10 predecodes the return instruction (RTI-R) in the interrupt routine (cycle C402), the instruction processing unit 10 stops decoding of a new instruction and outputs a response signal RETIACK (cycle C403). Then, the information stored in the stack before the execution of the interrupt routine is output to the buses CDBUS and DDBUS and returned to a predetermined register.
When the stack information is returned to the debug status register 24 (DBGSTAT), the flag data HPI and IDS_ACK stored therein return to the state before the interruption (value “0”) (cycle C409). Since the data indicating the interrupt hierarchy (DFC) is incremented by “1” before saving to the stack, the debug unit 20 returns the stack information to the debug status register 24 (DBGSTAT). “1” is subtracted from the value (cycle C410). The flag data DBGM stored in the status register ST2 returns to the state before interruption (value “0”) at a timing later than the flag data HPI and IDS_ACT (cycle C411).
The operation of the return instruction (RTI-R) described above is the same as in the case of FIG.

  On the other hand, in the operation example of FIG. 12, unlike the case of FIG. 6, when decoding of a new instruction is stopped by the return instruction (RTI-R), the signal generator 15 generates a stop signal SH. The stop signal SH propagates through the signal propagation unit 16 until the last stage “WRITE3” of the pipeline in synchronization with the progress of the instruction execution stage in the instruction execution unit 13. The state signal output unit 17 outputs the state signal S1 having the value “1” while the stop signal SH is propagated in the signal propagation unit 16 (cycles C403 to C411).

  When the state signal S1 changes from “1” to “0”, the state of the state machine 211 (EXSM) is updated to “stop state (DSUSP)” (cycle C413).

Further, in parallel with the processing of the return instruction (RTI-R) described above, the analysis unit 22 monitors memory access by the instruction processing unit 10 and an external trigger signal according to preset conditions. . Then, immediately before the status information is saved in the stack, it is detected that an access that matches the watchpoint condition has occurred (cycle C406).

  When notified of the watchpoint HALT event from the analysis unit 22, the execution control unit 21 outputs a request signal WP-RQ requesting the instruction processing unit 10 to stop the execution of the program (cycle C406). Upon receiving the request signal WP-RQ, the instruction processing unit 10 outputs a response signal HALT_ACK to this (cycle C407). However, since the status signal S 1 is “1” at this time, the response signal HALT_ACK is held by the ACK signal holding circuit 35. The update of the debug status register 24 (DBGSTAT) in response to the watchpoint HALT event is delayed until the status signal S1 becomes “0” (cycle C413). While the update of the debug status register 24 (DBGSTAT) is delayed, the status information saved in the stack is returned to each register.

In the processor shown in FIG. 2, as described in <1-3>, the information of the HALT event that occurred during the transition period in which the program execution is stopped by the return instruction (RTI-R) is the information saved in the stack. There is a problem that it disappears when returning.
On the other hand, in the processor shown in FIG. 1 according to the present embodiment, the update of the debug status register 24 (DBGSTAT) is restricted until the processing associated with the return instruction (RTI-R) is completed. Therefore, the information of the HALT event that occurred during the transition period is correctly recorded in the debug status register 24 (DBGSTAT), and the above problem is solved.

<2-4> When the DMA unit 23 is accessed when the debug frame (interrupt hierarchy) is changed by an interrupt

In the processor shown in FIG. 2, as described in <1-4>, when the debug frame (interrupt hierarchy) is changed by an interrupt instruction, the instruction processing unit 10X stored in the debug status register 24 (DBGSTAT) or the like. The status information is not updated all at once, but is updated at partially different timings. Therefore, when a memory access request (for example, a register value read instruction) generated by the function of the DMA unit 23 is executed at the transition of the debug frame and the status information of the instruction processing unit 10X is read, the individual information There is a problem that there is no correlation.
On the other hand, in the processor shown in FIG. 1 according to the present embodiment, the status signal S1 is set to “1” in the transition period in which the execution of the program is stopped, and the acceptance of the interrupt request is limited. Therefore, even if access to the memory or the like inserted by the DMA function (for example, reading of the debug status register 24 (DBGSTAT)) is executed in the transition period before the supply of the instruction is stopped, the transition period is in the above-described debug period.・ Do not overlap with the transition of the frame. That is, the access to the memory or the like inserted by the DMA function before the instruction supply is stopped is completed within the period in which the HALT instruction is propagated in the signal propagation unit 16, so that the acceptance of the interrupt request is delayed from this period. As a result, the access to the memory or the like by the DMA function does not overlap with the transition of the debug frame. As a result, the status information having no correlation is not read out at the transition of the debug frame when shifting to the interrupt routine, and the above problem is solved.

In the processor shown in FIG. 2, the access by the DMA unit 23 is valid in the transition period when the execution of the program is stopped. Therefore, when a command is input to the DMA unit 23 during this transition period, the DMA unit 23 executes access to a memory or the like.
If an access request to the memory or the like by the DMA unit 23 is accepted by the instruction processing unit 10X during the transition period, the instruction execution unit 13 is used to execute the process associated with the access request, and thus the process starts before that. Even after all the pipeline processing of the issued instruction is completed, the pipeline processing accompanying the access request of the DMA unit 23 continues for a while.
That is, if an access request from the DMA unit 23 is accepted during the transition period, even after the HALT instruction has been propagated through the signal propagation unit 16 (even after the status signal S1 returns from “1” to “0”). Therefore, the pipeline processing accompanying the access request of the DMA unit 23 continues. For this reason, when an interrupt is accepted when the DMA pipeline processing continues with the state signal S1 being “0”, status information having no correlation is read at the transition of the debug frame, as in the case described above. Problem arises.
On the other hand, in the processor shown in FIG. 1, the access request (that is, the request signal DMA_RQM) of the DMA unit 23 in the transition period is limited by the state signal S1. That is, the access request of the DMA unit 23 generated during the period in which the status signal S1 is “1” is delayed until the status signal S1 changes to “0”. As a result, the access request of the DMA unit 23 generated during the transition period can be handled as occurring after completion of the pipeline processing of the instruction processing unit 10 (that is, “stopped state (DSUSP)”).
Here, when an access request from the DMA unit 23 is generated in the “stop state (DSUSP)”, the execution control unit 21 limits the acceptance of interrupts until the pipeline processing associated with the access request is completed (interrupt enable signal INT_EN). To invalid state).
Then, during the access period of the DMA unit 23 executed in the “stop state (DSUSP)” after the transition period, the interrupt is not accepted and the transition of the debug frame does not occur. The aforementioned problem of being read is solved.
Further, since the debug frame does not change after the access request of the DMA unit 23 is accepted, the debug frame in which the access request of the DMA unit 23 is accepted, and the memory or the like is actually received by accepting the request. Always matches the debug frame in which the access is performed. That is, there is no problem that access by the DMA unit 23 is executed in a frame different from the desired debug frame.

  FIG. 13 is a timing chart showing an operation example when a DMA request is generated in the transition period when the execution of the program is stopped in the processor shown in FIG. 1 according to the present embodiment. FIGS. 13A to 13O correspond to FIGS. 9A and 9C, respectively.

When the instruction processing unit 10 predecodes the software breakpoint stop instruction (ESTOP) (cycle C451), the instruction processing unit 10 stops the decoding of a new instruction and sets the status signal S1 to “1” (cycle C452). When the processing of the instruction remaining in the pipeline is completed and the state signal S1 changes from “1” to “0” (cycle C461), the restriction by the debug restriction unit 30 is released, and the debug unit 20 stores the debug state register 24 (DBGSTAT). ) And the state machine 211 (EXSM) are updated (cycle C462).
In this way, during the period in which the status signal S1 is “1” (cycles C452 to C460), the DMA unit 23 inputs a command instructing access to the memory and the like, and outputs a request signal DMA_RQ corresponding to the command (cycle). C453). At this time, since the status signal S1 is “1”, the request signal DMA_RQM output from the AND circuit 33 is “0”. As a result, the request signal DMA_RQ output from the DMA unit 23 is not accepted by the instruction processing unit 10, and the DMA request by the DMA unit 23 enters a standby state.
When the status signal S1 changes from “1” to “0”, the masking of the request signal DMA_RQ by the AND circuit 33 is cancelled, and the instruction processing unit 10 accepts the DMA request in the standby state (cycle C462).
As described above, in the processor shown in FIG. 1, access by the DMA unit 23 is limited until the execution of the instruction in the instruction execution unit 13 is completed. The problem that no status information is read by the DMA function does not occur.

<2-5> When the command of the debug unit 20 is executed during the transition period when program execution is stopped

If an execution command (such as a RUNC command) is issued by the debug unit 20X during a transition period when program execution is stopped or a transition period when returning from an interrupt routine and stopping, an instruction is already issued before the execution command is issued. When a HALT event derived from an instruction processed by the processing unit 10X occurs, as described in <1-5>, the instruction processing unit 10X is stopped by an instruction not included in the original stop condition of the execution command. The problem is that the execution command is executed in an unintended debug frame.
On the other hand, in the processor according to the present embodiment, command execution (HALT, RUNC command, etc.) of the debug unit 20 is limited in a transition period when program execution is stopped.
That is, when the request signal EXE_RQ requesting execution of the command is output from the execution control unit 21 during the transition period when the program is stopped, the status signal S1 is “1” at this time, so that the request signal output from the AND circuit 32 EXE_RQM becomes “0”. As a result, the request signal EXE_RQ output from the execution control unit 21 is not accepted by the instruction processing unit 10, and the command execution request by the execution control unit 21 is in a standby state. When the status signal S1 changes from “1” to “0”, the masking of the request signal EXE_RQ by the AND circuit 32 is cancelled, and the instruction processing unit 10 receives a command execution request in a standby state.
As described above, in the processor shown in FIG. 1, command execution (HALT, RUNC command, etc.) during the transition period is limited. Therefore, the above-described control associated with instruction execution and stoppage during the transition period is performed. Such a problem is solved.

<2-6> When a HALT event occurs after accepting an interrupt when program execution is stopped

In the processor shown in FIG. 2, when the first or second instruction of the interrupt routine is a software breakpoint stop instruction (ESTOP) or the like, a HALT event is generated in the interrupt routine as described in <1-6>. However, before the status information is saved in the stack, the HALT event flag of the debug status register 24 (DBGSTAT) is set, and the content is saved in the stack.
On the other hand, in the processor shown in FIG. 1 according to the present embodiment, as shown in FIG. 9, since the acceptance of interrupts is limited in the transition period when the execution of the program is stopped, the above-described problem is solved.

<2-7> Stopping program execution while the benchmark counter 221 is counting

In the processor shown in FIG. 2, even when unprocessed instructions remain in the pipeline when the program execution is stopped, the count is stopped after a certain period from the time when the HALT event occurs. There arises a problem that an event (for example, a watchpoint) derived from an instruction before the occurrence of the event is excluded from the count target.
On the other hand, the benchmark counter 221 provided in the processor shown in FIG. 1 is not completed when the status signal S1 is “1”, that is, the pipeline processing of the instruction processing unit 10 is not completed when the execution of the program is stopped for debugging. While the state is indicated, it is possible to continue counting signals indicating the occurrence of an event related to the processing of the instruction processing unit 10. Therefore, according to the processor shown in FIG. 1, it is possible to correctly count the events in the transition period that have been excluded from the conventional counting target, and the above problem can be solved.
Further, the benchmark counter 221 initializes the count value according to the count condition in the transition period in which the pipeline processing is not completed, that is, whether to perform the counting operation of the counted signal, or the initialization signal. You can choose whether or not to run. That is, by utilizing the fact that the transition period is clearly indicated by the status signal S1, the count operation and the count value initialization operation in the transition period can be controlled with a very simple circuit. As a result, various count functions related to debugging can be realized with a very simple circuit configuration.
Furthermore, if the benchmark counter 221 is configured so that the count operation and the count value initialization operation in the transition period can be arbitrarily controlled according to the command, it becomes possible to count the counted signal under various conditions. User convenience can be improved.

  As described above, according to the processor shown in FIG. 1 according to the present embodiment, when the instruction processing unit 10 that processes an instruction in the pipeline system stops processing the instruction, a new instruction is processed. In addition to being stopped, a status signal S1 indicating whether or not the already started processing is completed is output. When the status signal S1 indicates an incomplete state of processing in the instruction processing unit 10, execution of the debug operation by the debug unit 20 is restricted by the debug restriction unit 30. That is, for the control of the operation of the instruction processing unit 10 and the recording of its operation state after the input of the instruction to the instruction processing unit 10 is stopped until the processing already started before the stop is completed. Related debugging behavior is limited.

In the conventional pipeline processor, the change in the debug state due to a HALT event or the like is constant after stopping the decoding of a new instruction regardless of whether or not the execution of the previously decoded instruction has been completed. Is happening after a clock cycle. This is simply because when the supply of a new instruction to the instruction register (a register for storing a fetched instruction) is stopped, it is considered that the execution of the program has been stopped. In other words, the boundary line indicating whether or not the execution of the program is stopped is set at the time when the instruction supply to the instruction register is stopped.
However, when instructions are still being executed in the pipeline, a debug command that controls the operating state of the processor is executed, status information is updated in response to a HALT event, an interrupt request is received, Furthermore, if access to a memory or the like by the DMA function for debugging is made effective, various problems (pipeline hazard) on debugging occur. In order to solve this problem, for example, if it is attempted to obtain only the matching of the operation results for each condition causing a problem, the control becomes very complicated. Also, it is difficult to extract all conditions that cause problems.
The cause of these problems is that the debug state change due to the HALT event, or the debugging operation before and after that, is not synchronized with the program flow of the processor. In the processor according to the present embodiment, the HALT event situation is regarded as one instruction (“HALT”: stop signal SH), and the problem is solved by explicitly placing it on the processing flow synchronized with the pipeline. Yes. That is, by detecting whether or not the virtual instruction “HALT” has passed through the pipeline stage, the instruction already supplied before the instruction supply to the instruction execution unit 11 is stopped is pipelined. It is possible to easily tell the debug unit 20 when the processing is completed after passing through all the stages. As a result, the boundary between the stop and start of program execution becomes very clear for the debug operation, and various problems (pipe) due to the debug operation being performed in a state where the instruction being executed remains in the instruction execution unit 13. Line hazards can be eliminated.

  Further, in the processor according to the present embodiment, by using the state signal S1 indicating whether or not the instruction processing in the instruction processing unit 10 is in an incomplete state, execution of a debug command and status information corresponding to the HALT event Control of whether to enter standby mode, ignore it, or execute it as it is, for each of various debugging operations, such as update of data, acceptance of interrupt request, access to memory by DMA function, etc. is realized with a very simple circuit it can.

  In the processor according to the present embodiment, the expansion delay unit 161 is configured so that the HALT event instruction “HALT” (that is, the stop signal SH) passes through the normal pipeline stage and then passes through the expansion stage (WRITE3). Is provided. As a result, even if processing associated with execution of the instruction (such as processing of a HALT event) occurs after the instruction has passed through all stages of the pipeline, the associated processing is performed in the above-described expansion stage (WRITE 3). By generating it, it is possible to appropriately limit the debugging operation in a period in which the accompanying process occurs.

  Next, a modification of the processor according to the present embodiment will be described.

FIG. 14 is a diagram illustrating a first modification of the processor according to the present embodiment.
The processor illustrated in FIG. 14 includes an instruction processing unit 10A, a debugging unit 20, and a debugging restriction unit 30. 14 and FIG. 1 indicate the same components.

  When the instruction processing unit 10A stops the processing of the instruction and the DMA unit 23 accesses or inserts an instruction, the instruction processing unit 10A displays a status signal S1 indicating whether or not the processing of the instruction associated with the access is completed. Output. The operation of outputting the status signal S1 when the instruction processing is stopped is the same as that of the instruction processing unit 10 in FIG.

The instruction processing unit 10A includes a signal generation unit 15A as shown in FIG. 14, for example.

In addition to the case where the input of the instruction by the input control unit 11 is stopped in response to the HALT event or the like, the signal generating unit 15A is used when the access or the like by the DMA unit 23 occurs while the instruction processing is stopped. Also generates a stop signal SH. The signal generator 15A receives the signal EXSM_STAT indicating the state in the state machine 211 (EXSM) and the request signal DMA_RQM from the DMA unit 23. The state of the state machine 211 is “stopped (DSUSP)” and the request signal DMA_RQM is In the case of “1”, a stop signal SH is generated.

  When the status signal S1 indicates that the instruction processing accompanying the DMA unit 23 access or the like is not completed, the debug limiting unit 30 determines whether the interrupt request in the instruction processing unit 10A is output until the status signal S1 indicates the completion status of the processing. Restrict reception.

When instruction processing is stopped in the instruction processing unit 10A, the DMA unit 23 starts accessing the memory and registers and inserting instructions, and immediately after that, an interrupt request is accepted and the transition to the interrupt routine is started. In this case, the debug frame (interrupt hierarchy) when the DMA unit 23 request is issued may not match the debug frame when the DMA unit 23 actually performs access. In this case, there arises a problem that access by the DMA unit 23 is executed in a frame different from a desired debug frame.
Therefore, in the processor shown in FIG. 14, if an access or the like by the DMA unit 23 occurs while the instruction processing is stopped, the instruction processing unit 10A accepts an interrupt request until the processing associated with the access or the like is completed. Limit.
FIG. 15 is a timing diagram showing an example of the operation, and FIGS. 15A to 15P correspond to FIGS. 9A to 9P, respectively. When a request signal DMA_RQM of “1” is input from the DMA unit 23 in the “stop state (DSUSP)” state in which execution of the program is stopped, the signal generation unit 15A outputs a stop signal SH (cycle C501). The signal propagation unit 16 to which the stop signal SH is input propagates the stop signal SH step by step by the delay units (RB1,..., RBn, 161) in accordance with the progress of the pipeline stage in the instruction execution unit 13. When the state signal output unit 17 detects that the stop signal SH is propagated in the signal propagation unit 18, the state signal output unit 17 sets the state signal S1 to “1” (cycles C502 to C510). During the period in which the status signal S1 is “1”, access by the DMA unit 23 is performed. For example, the DMA unit 23 causes a register read / write request to be executed by using the pipeline processing of the instruction execution unit 13 by directly inserting a register read / write request into the decode stage pipeline of the instruction execution unit 13. While the pipeline processing by DMA access is not completed, the status signal S1 becomes “1”. If an interrupt request is generated when the status signal S1 is “1” (cycle C503), the interrupt request is in a standby state until the status signal S1 becomes “0”, as in FIG.
As described above, the processor shown in FIG. 14 restricts acceptance of an interrupt request when an access or the like of the DMA unit 23 occurs when program execution is stopped. As a result, it is possible to solve the problem that the access of the DMA unit 23 is executed in a frame different from the desired debug frame.

FIG. 16 is a diagram illustrating a second modification of the processor according to the present embodiment.
The processor illustrated in FIG. 16 includes an instruction processing unit 10B, a debug unit 20, and a debug restriction unit 30. The same reference numerals in FIG. 16 and FIG. 1 denote the same components.

  The instruction processing unit 10B includes an instruction buffer / queue IBQ, an input control unit 11, a selector 12, an instruction execution unit 13, a pipeline protection unit 14, a status signal output unit 17B, and a stop instruction supply unit 18. Have. 16 and FIG. 1 indicate the same components.

  The stop command supply unit 18 supplies a predetermined stop command to the command execution unit 13 when the input control unit 11 stops the input of the command to the command execution unit 13. For example, a predetermined stop instruction is generated when a HALT event occurs to stop the execution of a program, or when returning from an interrupt that occurred during the stop of the execution of the program and then stopping again.

  The stop command supply unit 18 also generates a predetermined stop command when access by the DMA unit 23 or insertion of a command occurs while processing of the command is stopped. That is, the signal EXSM_STAT indicating the state in the state machine 211 (EXSM) and the request signal DMA_RQM from the DMA unit 23 are input, the state of the state machine 211 is “stopped (DSUSP)”, and the request signal DMA_RQM is “1”. A predetermined stop command is generated.

The status signal output unit 17B detects whether or not the predetermined stop instruction supplied from the stop instruction supply unit 18 is being executed in the instruction execution unit 13 (that is, whether it is passing through the pipeline stage), The detection result is output as the status signal S1. For example, a status signal S1 of “1” is output if a predetermined stop instruction is being executed, and “0” if it is not being executed.
Note that the instruction execution unit 13 may perform a formal process without an execution result (for example, access to a memory or output of an operation result) for the predetermined stop instruction, or a specific execution result may be generated. May be performed.

According to the configuration described above, when the input of an instruction to the instruction execution unit 13 is stopped in response to the occurrence of a HALT event, or when the DMA unit 23 is accessed when the execution of the program is stopped, the instruction execution unit A predetermined stop command is supplied to 13. While the stop instruction is being executed in the instruction execution unit 13, the state signal output unit 17 outputs a state signal S1 indicating that the instruction execution in the instruction execution unit 13 has not been completed. When this status signal S1 is output, a debugging operation by the debug unit 20 (acceptance of an interrupt request, access by the DMA unit 23, update of the state machine 211 (EXSM), update of the debug status register 24 (DBGSTAT), debug unit 20 Command execution) is limited.
Therefore, in the processor shown in FIG. 16 as well, various pipeline hazards can be prevented because the debugging operation in the transition period when the program stops executing is limited. Further, since the acceptance of an interrupt request is restricted when an access occurs in the DMA, it is possible to prevent the DMA access from being executed in a frame different from a desired debug frame (interrupt hierarchy).

  As mentioned above, although embodiment of this invention was described, this invention is not limited only to said embodiment, Various variations are included.

  The CPU peripheral module requests the processor to output a signal indicating that the instruction supply to the instruction register is stopped in order to define the operation when the CPU instruction execution is stopped during debugging. There is something. According to the present embodiment, the above signal can be generated by a simple logical operation based on the information of the state machine 211 (EXSM) indicating the operating state of the processor and the above-described state signal S1.

  The processor of the present invention is widely applicable to any processor that processes instructions in a pipeline manner.

It is a figure which shows an example of a structure of the processor which concerns on embodiment of this invention. It is a figure which shows the example of 1 structure of the processor which does not have a function which restrict | limits debug operation | movement in the transition period at the time of stopping execution of a program. FIG. 3 is a timing chart showing an example of an operation when a HALT event (watchpoint) occurs in a transition period when program execution is stopped in the processor shown in FIG. 2. FIG. 3 is a timing chart showing a first operation example when a HALT event (watchpoint) and an interrupt occur in a transition period when program execution is stopped in the processor shown in FIG. 2. FIG. 3 is a timing diagram illustrating a second operation example when a HALT event (watchpoint) and an interrupt occur in a transition period when program execution is stopped in the processor illustrated in FIG. 2. FIG. 3 is a timing chart showing an example of an operation when a HALT event occurs in a transition period when returning from an interrupt routine and stopping a program in the processor shown in FIG. 2. FIG. 3 is a timing chart showing an example of an operation when an interrupt occurs in a transition period when program execution is stopped in the processor shown in FIG. 2 and the top of the interrupt routine is a stop instruction. In the processor shown in FIG. 1 according to the present embodiment, it is a timing chart showing an example of an operation when a HALT event (watchpoint) occurs in a transition period when program execution is stopped. In the processor shown in FIG. 1 according to the present embodiment, it is a timing diagram showing an operation example when an interrupt occurs during a transition period when program execution is stopped. In the processor shown in FIG. 1 according to the present embodiment, it is a timing chart showing a first operation example when a HALT event (watchpoint) and an interrupt occur during a transition period when program execution is stopped. In the processor shown in FIG. 1 according to the present embodiment, it is a timing chart showing a second operation example when a HALT event (watchpoint) and an interrupt occur during a transition period when program execution is stopped. In the processor shown in FIG. 1 according to the present embodiment, it is a timing chart showing an example of an operation when a HALT event occurs in a transition period when returning from an interrupt routine and stopping a program. In the processor shown in FIG. 1 according to the present embodiment, it is a timing chart showing an operation example when a DMA request is generated in a transition period when program execution is stopped. It is a figure showing the 1st modification of a processor concerning this embodiment. FIG. 15 is a timing diagram showing an operation example when a DMA access occurs when instruction processing is stopped in the processor shown in FIG. 14 and an interrupt request further occurs during the access. It is a figure showing the 2nd modification of a processor concerning this embodiment.

Explanation of symbols

The processor illustrated in FIG. 1 includes an instruction processing unit 10, a debug unit 20, and a debug restriction unit 30.
DESCRIPTION OF SYMBOLS 10,10A, 10B ... Instruction processing part, 11 ... Input control part, 12 ... Selector, 13 ... Instruction execution part, 14 ... Pipeline protection part, 15, 15A ... Signal generation part, 16 ... Signal propagation part, 161 ... Expansion Delay unit, 17, 17B ... Status signal output unit, 20 ... Debug unit, 21 ... Execution control unit, 22 ... Analysis unit, 23 ... DMA unit, 24 ... Debug status register (DBGSTAT), 30 ... Debug limiting unit, 30, 31, 32, 33, 36 ... AND circuit, 34 ... edge detection circuit, 35 ... ACK signal holding circuit, IBQ ... instruction buffer queue

Claims (13)

A series of instructions sequentially processed by pipelining, to stop the process, as well as prohibiting the start of the process of the new instruction, already started when the disables the start of the processing of the new instruction Tei An instruction processing unit for outputting a status signal indicating whether or not incomplete processing has been completed;
In accordance with an input command, at least a debug unit that executes a debug operation related to control of operation of the instruction processing unit or recording of the state of the operation;
If the status signal is the debugger in the period indicated incomplete state attempts to execute the debugging operation, suspended without executing the debug operation, after the state signal is changed to the completion state of incompletion state A processor having a debug restriction unit for executing the suspended debug operation . The debug unit has a memory access unit that accesses at least a storage unit to be accessed by the instruction processing unit or inserts further instructions into the series of instructions according to an input command. ,
It said instruction processing unit to stop processing the sequence of instructions, are already new in response to said access memory access section of the completion Not having been started process or when said prohibited the start of the process of the new instruction indicates whether already the insertion the already outstanding that were start processing includes processing uncompleted had been initiated in response to the instruction of the memory access unit is completed when the disables the start of processing of instructions Outputting the status signal;
The processor of claim 1. The instruction processing unit
An instruction execution unit that executes a series of input instructions in a pipeline manner;
An input control unit that controls input of an instruction to the instruction execution unit;
A signal generator for generating a predetermined stop signal when the input of the instruction to the instruction execution unit is stopped by the input control unit;
The stop signal generated in the signal generation unit is input to the first stage, and includes a plurality of delay units that sequentially propagate the input stop signal to the subsequent stage in synchronization with the progress of the instruction execution stage in the instruction execution unit. A signal propagation part;
A state signal output unit that detects whether or not the stop signal propagates through the signal propagation unit, and outputs the detection result as the state signal,
The processor of claim 1. The signal propagation part is
A plurality of delay units for propagating the stop signal , corresponding to a plurality of stages for executing one command in the command execution unit;
An extended delay unit that further propagates the stop signal propagated by the plurality of delay units corresponding to the plurality of stages in a certain period during which processing associated with execution of instructions by the plurality of stages can be executed ,
The processor according to claim 3. The instruction processing unit
An instruction execution unit that executes a series of input instructions in a pipeline manner;
An input control unit that controls input of an instruction to the instruction execution unit;
A stop command supply unit that supplies a predetermined stop command to the command execution unit when input of the command to the command execution unit is stopped by the input control unit;
A state signal output unit that detects whether or not the predetermined stop instruction is being executed in the instruction execution unit, and outputs the detection result as the state signal;
The processor of claim 1. The debug unit can control the instruction processing unit to accept an interrupt request even when instruction processing is stopped,
It said debug limiting unit, when said interrupt request is generated, suspends without executing the acceptance of the interrupt request in the instruction processing unit according to the control of the debugger during a period when the state signal indicates an uncompleted state , Causing the pending interrupt request to be accepted after the status signal has changed from an incomplete state to a complete state,
The processor according to any one of claims 1, 2, 3, 4 or 5. The debug unit has a memory access unit that accesses at least a storage unit to be accessed by the instruction processing unit or inserts further instructions into the series of instructions according to an input command. ,
Said debug limiting unit, when said memory access unit tries to perform the insertion of the access or the instruction, and hold without executing the insertion of the access or the instruction during a period when the state signal indicates an uncompleted state , Causing the pending access or instruction insertion to be executed after the status signal changes from an incomplete state to a completed state,
The processor according to any one of claims 1, 2, 3, 4 or 5. The debug unit can control the instruction processing unit to accept an interrupt request even when instruction processing is stopped,
If the access by the memory access unit or the insertion of the instruction occurs while the instruction processing unit stops the processing of the instruction, whether the processing according to the access is completed or the inserted instruction Output the status signal indicating whether or not the processing according to
When the interrupt request is generated in a period in which the status signal indicates that the processing corresponding to the access of the memory access unit is not completed or the processing corresponding to the inserted instruction is not completed, the debugging unit wherein according to a control of pending without executing the acceptance of the interrupt request in the instruction processing unit, said state signal to execute the reception of the hold the interrupt request after changing to completion state from an uncompleted state,
The processor according to claim 7. The debug unit has a state machine indicating an instruction execution state in the instruction processing unit,
Said debug limiting unit, when the status signal is the debugger in the period indicated incomplete state tries to perform an update of the state of the state machine, suspended without executing the updating of the state, the state signal Causes the pending state to be updated after the changes from incomplete to complete
The processor according to any one of claims 1, 2, 3, 4 or 5. The debug unit has a storage unit that stores information related to a cause of stoppage of processing in the instruction processing unit,
Said debug limiting unit, when the status signal is the debugger in the period indicated incomplete state tries to perform an update of the stored information of the storage unit, suspended without executing the updating of the stored information, the Update the stored information after the status signal changes from the incomplete state to the complete state,
The processor according to any one of claims 1, 2, 3, 4 or 5. The debug unit controls at least stop or restart of processing in the instruction processing unit as the debugging operation,
It said debug limiting unit, when the status signal is the debugger in the period indicated incomplete state attempts to execute a process of stopping or restarting of the instruction processing unit, hold without executing the stop or restart of the process And causing the suspended processing to be stopped or resumed after the state signal changes from the incomplete state to the complete state.
The processor according to any one of claims 1, 2, 3, 4 or 5. The debugging unit generates a predetermined event related to the processing of the instruction processing unit during a period in which the instruction is processed by the instruction processing unit, including a case where the state signal indicates an incomplete state Having a counting unit for counting signals indicating
The processor according to any one of claims 1, 2, 3, 4 or 5. The counting unit selects at least whether to count the counted signal in a period in which the state signal indicates an incomplete state, or the state signal is in an incomplete state, according to an input control signal It is possible to select whether or not to execute the initialization of the count value according to the initialization signal input during the period indicating
The processor according to claim 12.