JP4405458B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device having a high dielectric constant gate insulating film suitable for miniaturization.

  Until now, LSIs have been miniaturized and highly integrated in accordance with the scaling law. The scaling law is a technique for miniaturization while maintaining normal transistor characteristics by proportionally reducing the height and lateral dimensions of the MOS transistor such as the gate insulating film thickness and the gate length. If this scaling law is applied to the next generation LSI, the thickness of the gate insulating film becomes as small as 2 nm or less.

  Conventionally, a silicon oxide film (SiO 2 film) is generally used as the gate insulating film. However, when the silicon oxide film has a thickness of 2 nm or less, the tunnel current cannot be ignored. Therefore, an attempt has been made to use a gate insulating film having a higher dielectric constant in place of the silicon oxide film. This is because if an insulating film having a high dielectric constant is used, a silicon oxide equivalent film thickness of 2 nm or less can be realized while suppressing a leakage current as a relatively thick film thickness. Specifically, metal oxides such as ZrO 2 and HfO 2 have attracted attention as gate insulating film materials that can replace silicon oxide films.

  However, since metal oxide films such as ZrO 2 and HfO 2 are composed of bonds between metal atoms having a large atomic radius and oxygen having a small atomic radius, there is a problem that defects are likely to occur and stability is lacking. In particular, in areas where a large electric field is applied, such as the overlap between the gate electrode, drain, and source diffusion layer, dielectric breakdown due to atomic vacancies or dangling bonds is likely to occur, and sufficient reliability cannot be obtained. was there.

  The present invention has been made in view of the above circumstances, and an object thereof is to provide a semiconductor device having a gate insulating film structure containing metal atoms and having high dielectric breakdown resistance.

  A semiconductor device according to an aspect of the present invention includes a semiconductor substrate, a source and drain diffusion layer formed so as to face the semiconductor substrate with a channel region interposed therebetween, and a predetermined length in the channel length direction on the semiconductor substrate. A gate insulating film formed including a metal atom exhibiting a change in concentration; and a gate electrode formed on the gate insulating film, the gate insulating film being positioned immediately above the channel region. A first gate insulating film and a second gate insulating film that covers the other region and includes metal atoms having a lower concentration than the first gate insulating film and is bonded to the first gate insulating film; The junction between the first gate insulating film and the second gate insulating film is connected to the junction end of the source diffusion layer and the channel region and the junction end of the drain diffusion layer and the channel region. And wherein the match with the channel length direction.

  According to the present invention, by using a metal oxide film in which a metal atom is introduced at a required concentration only in a portion where a high dielectric constant of the gate insulating film is required, deterioration of dielectric breakdown resistance due to defects caused by the metal atom is reduced. MIS transistor can be effectively suppressed, and miniaturization and high integration of the MIS transistor can be achieved.

  Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 illustrates an MIS transistor structure of an integrated circuit according to one embodiment. An element isolation insulating film 2 is embedded in the p-type silicon substrate 1 to define an element formation region. Source and drain diffusion layers 3 are formed on the silicon substrate 1 so as to face each other with the channel region 4 interposed therebetween. A gate electrode 6 is formed on the silicon substrate 1 via a gate insulating film 5.

  The gate insulating film 5 is composed of a first gate insulating film 5a positioned immediately above the channel region 4 and a second gate insulating film 5b covering the other regions. Both the first gate insulating film 5a and the second gate insulating film 5b are films containing metal atoms and oxygen atoms (hereinafter simply referred to as metal oxide films) and have a film thickness of about 10 nm. However, the metal atom concentration of the first gate insulating film 5a is set higher than that of the second gate insulating film 5b. In addition, the Zr concentration distribution smoothly changes between the first gate insulating film 4a and the second gate insulating film 5b by heat treatment in an appropriate process. The metal oxide film is typically a ZrOx film.

  FIG. 2 shows the Zr concentration distribution in the channel length direction when the gate insulating film 5 is a ZrOx film. Desirably, in the first gate insulating film 5a immediately above the channel region 4 (that is, in the range of y1-y2), the Zr atom concentration in ZrOx is set to 1 atm% or more and 40 atm% or less, and covers other regions. In the second gate insulating film 5b, the Zr atom concentration is lower than that of the first gate insulating film 5a and can be suppressed to 1 atm% or less. By giving such a Zr concentration distribution, the first gate insulating film 5a has a large relative dielectric constant of about 25. The second gate insulating film 5b has high resistance to dielectric breakdown caused by atomic deficiency, dangling bonds, etc. as a result of keeping the Zr concentration low.

  The substrate on which the element is formed is covered with an interlayer insulating film 7. Contact holes are formed in the interlayer insulating film 7 to form electrode wirings 8.

  A manufacturing process of such a MIS transistor will be described with reference to FIGS. A p-type silicon substrate 1 having a plane orientation (100) and a specific resistance of 4 to 6 Ωcm is used. As shown in FIG. 3, a trench is formed in the element isolation region of the silicon substrate 1 by RIE, and the element isolation insulating film 2 is embedded in this trench. The element isolation insulating film 2 is a silicon oxide film formed by low pressure CVD using organosilane (TEOS).

  Next, as shown in FIG. 4, a first gate insulating film 5a made of a metal oxide film is deposited on the entire surface of the substrate by a laser ablation film forming method by about 10 nm. Specifically, the metal oxide film is a ZrOx film. At this time, the film forming conditions are a substrate temperature of 500 to 800 ° C. in an atmosphere with an oxygen partial pressure of 1 to 100 mTorr. Thereby, a ZrOx film having a Zr concentration of 1 to 40 atm% is obtained.

Next, as shown in FIG. 5, a silicon nitride film 11 is deposited by the CVD method, and the laminated film of the silicon nitride film 11 and the first gate insulating film 5a is patterned so as to remain in the center of the channel region. Then, arsenic ions are implanted to form n ⁺ -type drain and source diffusion layers 3. The ion implantation conditions are, for example, an acceleration voltage of 10 keV and a dose of 1 × 10 ¹⁵ / cm ² .

  Next, as shown in FIG. 6, a second gate insulating film 6b made of a metal oxide is deposited by about 10 nm again by a laser ablation film forming method. Also in this case, the metal oxide film is a ZrOx film. At this time, the film forming conditions are such that the substrate temperature is lowered to 350 to 500 ° C. in an atmosphere having an oxygen partial pressure of 1 to 100 mTorr. Thereby, a ZrOx film having a Zr concentration of 1 atm% or less and a low Zr concentration is obtained.

  After the second gate insulating film 5b is formed, heat treatment is performed by raising the substrate temperature to about 700 ° C. in an atmosphere having the same oxygen partial pressure. As a result, the interface between the first gate insulating film 5a and the second gate insulating film 5b becomes a good junction without defects and the metal atoms in the first gate insulating film 5a become the second gate insulating film. It diffuses to 5b, and the change in the metal atom concentration distribution in the channel length direction becomes smooth.

  Thereafter, as shown in FIG. 7, a polycrystalline silicon film is deposited and patterned to form the gate electrode 6. The gate electrode 6 is patterned so as to cover the first gate insulating film 5a and both ends cover the second gate insulating film 5b. That is, the gate electrode 6 is in a state where both ends in the channel length direction overlap the drain and source diffusion layers 3 with the second gate insulating film 5b interposed therebetween. Thereafter, as shown in FIG. 1, an interlayer insulating film 7 is deposited, contact holes are formed therein, and electrode wiring 8 is formed.

  As described above, in this embodiment, the metal atom concentration of the gate insulating film made of metal oxide is high immediately above the channel region, and low at the portion where the drain, source diffusion layer 3 and gate electrode 6 on both sides overlap. is doing. At this time, basic electrical characteristics of the MIS transistor are determined by the first gate insulating film 5a on the channel region. The gate insulating film 5b in the portion where the gate electrode 6 to which a high electric field is applied overlaps with the drain and source diffusion layers 3 has a low dielectric breakdown resistance because the concentration of metal atoms having a large atomic radius is low. It becomes.

  FIG. 8 shows the structure of the MIS transistor portion of the integrated circuit according to another embodiment. Parts corresponding to those of the embodiment of FIG. 1 are denoted by the same reference numerals as those of FIG. Also in this embodiment, the gate insulating film 5 is composed of the first gate insulating film 5a immediately above the channel region 4 and the second gate insulating film 5b in other regions. As in the previous embodiment, the first gate insulating film 5a is made of a metal oxide such as ZrOx, while the second gate insulating film 5b is basically an insulating film containing no metal atoms, preferably Is a silicon oxide film.

  However, the metal atoms of the first gate insulating film 5a are diffused into the portion of the second gate insulating film 5b in contact with the first gate insulating film 5a. As a result, the interface between the first gate insulating film 5a and the second gate insulating film 5b is made a good junction without defects and the like, and at the same time, the change in the metal atom concentration distribution in the channel length direction in the gate insulating film is smoothed. It is supposed to be.

  The manufacturing process of this embodiment will be described with reference to FIGS. A p-type silicon substrate 1 having a plane orientation (100) and a specific resistance of 4 to 6 Ωcm is used. As shown in FIG. 9, a trench is formed in the element isolation region of the silicon substrate 1 by RIE, and the element isolation insulating film 2 is embedded in this trench. The element isolation insulating film 2 is a silicon oxide film formed by low pressure CVD using organosilane (for example, TEOS).

  Next, as shown in FIG. 10, a first gate insulating film 5a made of a metal oxide film is deposited on the entire surface of the substrate by a laser ablation film forming method by about 10 nm. Specifically, the metal oxide film is a ZrOx film. At this time, the film forming conditions are a substrate temperature of 500 to 800 ° C. in an atmosphere with an oxygen partial pressure of 1 to 100 mTorr. Thereby, a ZrOx film having a Zr concentration of 1 to 40 atm% is obtained.

Next, as shown in FIG. 11, a silicon nitride film 11 is deposited by the CVD method and patterned so that the laminated film of the silicon nitride film 11 and the first gate insulating film 5a remains in the center of the channel region. Then, arsenic ions are implanted to form n ⁺ -type drain and source diffusion layers 3. The ion implantation conditions are, for example, an acceleration voltage of 10 keV and a dose of 1 × 10 ¹⁵ / cm ² . Up to this point, it is the same as the previous embodiment.

  Thereafter, the temperature of the substrate is set to 500 to 1000 ° C. in an atmosphere containing oxygen gas, and the surface of the silicon substrate 1 is oxidized to form silicon that becomes the second gate insulating film 5b as shown in FIG. An oxide film is formed. At the same time in the thermal oxidation process, metal atoms of the first gate insulating film 5a are diffused into the junction of the silicon oxide film formed with the first gate insulating film 5a. As a result, the interface between the first gate insulating film 5a and the second gate insulating film 5b becomes a good junction without defects.

  FIG. 12 shows the case where the silicon oxide film is formed thicker than the first gate insulating film 5a, but can be arbitrarily selected within a range of about 5 to 500 nm. For example, similarly to the previous embodiment, the first gate insulating film 5a and the second gate insulating film 5b may have the same film thickness.

  Thereafter, as shown in FIG. 13, a polycrystalline silicon film is deposited and patterned to form the gate electrode 6. The gate electrode 6 is patterned so as to cover the first gate insulating film 5a and both ends cover the second gate insulating film 5b. That is, the gate electrode 6 is in a state where both ends in the channel length direction overlap the drain and source diffusion layers 3 with the second gate insulating film 5b interposed therebetween. Thereafter, as shown in FIG. 1, an interlayer insulating film 7 is deposited, contact holes are formed therein, and electrode wiring 8 is formed.

  In the case of this embodiment, the gate insulating film 5a immediately above the channel region is a metal oxide film, and the gate insulating film 5b where the drain and source diffusion layers 3 and the gate electrode 6 overlap on both sides does not contain metal atoms. It is formed of a silicon oxide film or the like, and basic electrical characteristics of the MIS transistor are determined by the first gate insulating film 5a. Since the gate insulating film 5b where the gate electrode 6 to which a high electric field is applied overlaps with the drain / source diffusion layer 3 uses a silicon oxide film as in the conventional case, the gate insulating film 5b has high dielectric breakdown resistance. .

  In each of the above embodiments, the drain and source diffusion layers 3 are formed in a self-aligned state with the first gate insulating film 5a by one ion implantation. On the other hand, in order to suppress the short channel effect in the miniaturized MIS transistor, it is preferable that the drain and the source have an LDD structure. FIG. 14 shows the MIS transistor structure of such an embodiment.

The basic structure of the transistor in FIG. 14 is the same as that in FIG. However, the drain and source diffusion layers 3 are formed by ion implantation after the low concentration n ⁻ type layer 3a formed by self-alignment with the first gate insulating film 5a and the gate electrode 6 are formed. The n ⁺ type layer 3b is used. Similar to the embodiment of FIG. 8, the same LDD structure is effective when the second gate insulating film 5b is formed of a silicon oxide film or the like not containing metal atoms. By adopting such an LDD structure, the short channel effect can be suppressed and the MIS transistor can be miniaturized.

  In the embodiment, the metal oxide film is deposited by the laser ablation film forming method, but other methods such as a sputtering method, a CVD method, a single atom sequential deposition method (Atomic Layer Deposition) method and the like can also be used. In addition to ZrOx, HfOx, TaOx, LaOx, CeOx, AlOx, or the like can be used as the metal oxide film, or a silicate film containing silicon can be used.

It is sectional drawing which shows the MIS transistor structure by embodiment of this invention. It is a figure which shows the metal atom concentration distribution of the gate insulating film of the MIS transistor of the embodiment. It is sectional drawing which wets the element isolation process of the embodiment. It is sectional drawing which shows the 1st gate insulating film formation process of the embodiment. It is sectional drawing which shows the 1st gate insulating film patterning and drain and source diffusion layer formation process of the embodiment. It is sectional drawing which shows the 2nd gate insulating film formation process of the embodiment. It is sectional drawing which shows the gate electrode formation process of the embodiment. It is sectional drawing which shows the MIS transistor structure by other Embodiment of this invention. It is sectional drawing which wets the element isolation process of the embodiment. It is sectional drawing which shows the 1st gate insulating film formation process of the embodiment. It is sectional drawing which shows the 1st gate insulating film patterning and drain and source diffusion layer formation process of the embodiment. It is sectional drawing which shows the 2nd gate insulating film formation process of the embodiment. It is sectional drawing which shows the gate electrode formation process of the embodiment. It is sectional drawing which shows the MIS transistor structure by other Embodiment of this invention.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... P-type silicon substrate, 2 ... Element isolation insulating film, 3 ... Drain, source diffusion layer, 4 ... Channel region, 5a ... 1st gate insulating film, 5b ... 2nd gate insulating film, 6 ... gate electrode, 7 ... interlayer insulating film, 8 ... electrode wiring.

Claims (2)

A semiconductor substrate;
A source and drain diffusion layer formed to face the semiconductor substrate across the channel region;
On the semiconductor substrate, a gate insulating film formed including metal atoms exhibiting a predetermined concentration change in the channel length direction;
A gate electrode formed on the gate insulating film;
Have
The gate insulating film includes a first gate insulating film located immediately above the channel region, and other regions, and includes metal atoms having a lower concentration than the first gate insulating film. A second gate insulating film joined to the film,
The junction between the first gate insulating film and the second gate insulating film is in the channel length direction with respect to the junction end of the source diffusion layer and the channel region and the junction end of the drain diffusion layer and the channel region. A semiconductor device characterized by   The semiconductor device according to claim 1, wherein the metal atom concentration of the gate insulating film smoothly changes between a portion on the channel region and a portion overlapping the source and drain diffusion layers.

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