JP4413524B2 - Multiport memory - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a multiport memory that can be accessed by a plurality of microprocessors.
[0002]
[Prior art]
Today, memory may be shared by multiple microprocessors, in which case multiport memory may be used. This multi-port memory is provided with an arbitration circuit, so that the arbitration circuit arbitrates access from each microprocessor on a first-come-first-served basis (see Patent Document 1).
[0003]
A conventional configuration of such a multi-port memory will be described with reference to FIG.
[0004]
The multi-port memory 4 mainly includes an arbitration circuit 2 that performs arbitration when data is transferred between the plurality of microprocessors 1a and 1b, and a single-port memory 3 that stores data.
[0005]
The arbitration circuit 2 includes an access right determination unit 5 and a switching unit 6, and arbitrates access contention on a first-come-first-served basis even when accesses from a plurality of microprocessors 1a and 1b occur simultaneously.
[0006]
The access right determination means 5 determines an access right based on the access signals CS-A and CS-B from the microprocessors 1a and 1b, and outputs a switching signal SEL indicating one microprocessor 1a (1b) that permits access. While outputting to the switching means 6, a wait signal WAIT-B (WAIT-A) is output to the microprocessor 1b (1a) waiting for access.
[0007]
The switching means 6 switches the signal from the microprocessor 1a and the signal from the microprocessor 1b based on the switching signal SEL, and sends the address signal ADRS, data signal DATA, write signal WR, and read signal RD to the single port memory 3. Output as.
[0008]
Signals from the microprocessor 1a are an address signal ADRS-A, a data signal DATA-A, a write signal WR-A, and a read signal RD-A. The signals from the microprocessor 1b are an address signal ADRS-B, a data signal DATA-B, a write signal WR-B, and a read signal RD-B.
[0009]
FIG. 12 is a timing chart of such a multi-port memory 4. When the microprocessor 1a accesses first, the access right determination means 5 selects the switching signal SEL on the A side, and the microprocessor 1b waits at a high level. The signal WAIT-B is output.
[0010]
[Patent Document 1]
JP 2000-57775 A
[0011]
[Problems to be solved by the invention]
However, in the multi-port memory 4, for example, when the microprocessor 1a continuously accesses, the switching signal SEL continues to be in the A-side selection state, so that the wait signal WAIT-B is continuously output to the microprocessor 1b. The following problems occur because the state continues.
[0012]
That is, for example, while the microprocessor 1a is accessing, the microprocessor 1b stops the calculation by the wait signal WAIT-B, so that there is a problem that the calculation performance of the microprocessor 1b is deteriorated.
[0013]
Further, if the microprocessor 1a continues to access and the microprocessor 1b continues to wait for access, the microprocessor 1b cannot execute emergency processing such as interrupt processing, resulting in a decrease in response performance to the emergency processing. There is a problem.
[0014]
Further, even when the microprocessor 1a performs processing with a low load and the microprocessor 1b performs processing with a high load, if the microprocessor 1a continues to access, the microprocessor 1b continues to wait for access during this time. Therefore, there is a problem that the load on the microprocessor 1b becomes larger and the performance is lowered as a result.
[0015]
SUMMARY OF THE INVENTION An object of the present invention is to provide a multi-port memory capable of suppressing a decrease in the calculation performance of a microprocessor and shortening a response time in an emergency and enabling efficient memory access.
[0016]
[Means for Solving the Problems]
In order to solve the above problems, the present invention provides: When access competition by a plurality of microprocessors occurs in a single port memory and the single port memory, access is permitted to one of the microprocessors, and a wait signal is sent to the other microprocessor. In a multi-port memory having an arbitration circuit that arbitrates access by outputting and waiting for access, The arbitration circuit counts the output duration time of the wait signal to the other microprocessor, and when the time reaches the predetermined time, a wait timer that outputs a timer signal; The microprocessor access is Once finished Later, an access right determination means for outputting a switching signal so that the other microprocessor can access the multi-port memory, and the corresponding microprocessor can access the single-port memory based on the switching signal. Switching means for switching as described above.
[0017]
According to this configuration, when one microprocessor accesses continuously, the wait timer detects that the access wait state has continued for a predetermined time or more, and outputs a timer signal to the access right determination means to determine the access right. Since the access right is switched to the side from which the wait signal is output in the means, the access waiting state of the other microprocessor can be prevented from exceeding a predetermined time.
[0018]
Thereby, it is possible to suppress a reduction in the calculation performance of the microprocessor, and to respond to an emergency process such as an interrupt process within a predetermined time.
[0019]
According to another aspect of the present invention, when access conflict between a single port memory and a plurality of microprocessors occurs in the single port memory, access is permitted to one of the microprocessors, and the other microprocessor is In the multi-port memory having an arbitration circuit that arbitrates access by outputting a wait signal and waiting for access, the arbitration circuit includes the wait signal for the other microprocessor and the one of the microprocessors. Detect a read signal or write signal from the processor, Regardless of the number of detection matches, A wait counter that outputs a count signal when the number of detection times reaches a predetermined number, and upon receipt of the count signal, once access to one of the microprocessors is completed, the other microprocessor accesses the multiport memory. Access right determination means for outputting a switching signal so that access is possible, and switching means for switching so that the corresponding microprocessor can access the single port memory based on the switching signal.
[0020]
According to this configuration, when one microprocessor accesses continuously, the wait counter detects that the access waiting state has continued for a predetermined time or more, and outputs a count signal to the access right determination means to determine the access right. Since the access right is switched to the side from which the wait signal is output, the access waiting state of the other processor can be prevented from exceeding the predetermined number of accesses. Also, the setting of the weight counter can be set for each processor.
[0021]
Thereby, it is possible to suppress a reduction in the calculation performance of the microprocessor, and to respond to an emergency process such as an interrupt process within a predetermined time. In addition, since the number of accesses in the wait counter can be set variably, the calculation performance can be improved by setting according to the priority of the microprocessor.
[0022]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described with reference to the drawings. In addition, about the same structure as the past, the same code | symbol is attached | subjected and description is abbreviate | omitted suitably.
[0023]
FIG. 1 is a block diagram showing a schematic configuration of a multi-port memory 4 applied to the description of the present embodiment, and an arbitration provided for arbitrating access contention among a plurality of microprocessors 1a and 1b. The arbitration circuit 2 is connected to the microprocessors 1a and 1b and the single port memory 3 with the circuit 2 and the single port memory 3 storing data as main components.
[0024]
The arbitration circuit 2 includes an access right determination unit 5, a switching unit 6, and wait timers 7a and 7b, and switches the access right every predetermined time even when accesses are simultaneously generated from the plurality of microprocessors 1a and 1b. It is configured as follows.
[0025]
The access right determination means 5 determines an access right based on the access signals CS-A and CS-B from the microprocessors 1a and 1b, and outputs a switching signal SEL and wait signals WAIT-A and WAIT-B.
[0026]
The switching means 6 is based on the switching signal SEL and receives address signals ADRS-A and ADRS-B, data signals DATA-A and DATA-B, write signals WR-A and WR-B, and reads from the microprocessors 1a and 1b. The signals RD-A and RD-B are switched and output to the single port memory 3 as an address signal ADRS, a data signal DATA, a write signal WR, and a read signal RD.
[0027]
The wait timers 7a and 7b output timer signals TIME-A and TIME-B when detecting that the access wait state has continued for a predetermined time or more from the wait signals WAIT-A and WAIT-B.
[0028]
FIG. 2 is a timing chart of such a configuration. When the microprocessor 1a receives the access signal CS-B of the microprocessor 1b during the access, the access right determination means 5 returns the wait signal WAIT-B on the B side to the microprocessor 1b, and by this wait signal WAIT-B, The microprocessor 1b enters an access waiting state.
[0029]
When the microprocessor 1a continues to access and the wait timer 7b exceeds the timer set time tb, the timer signal TIME-B is output to the access right determination means 5.
[0030]
When the access right determination means 5 detects the timer signal TIME-B, the switching signal SEL is changed from the A side to the B side when the read signal RD-A or the write signal WR-A from the microprocessor 1a is once terminated. Switch.
[0031]
The switching means 6 switches the read signal RD, the write signal WR, the address signal ADRS, and the data signal DATA from the read signal RD-A to the read signal RD-B when the switch signal SEL is switched from the A side to the B side. Further, the write signal WR-A is switched to the write signal WR-B, the address signal ADRS-A is switched to the address signal ADRS-B, and the data signal DATA-A is switched to the data signal DATA-B.
[0032]
Similarly, when the access signal CS-A of the microprocessor 1a is input while the microprocessor 1b is accessing, the access right determination means 5 returns the wait signal WAIT-A to the microprocessor 1a, and the micro signal 1a receives the micro signal by the wait signal WAIT-A. The processor 1a enters an access waiting state.
[0033]
When the access of the microprocessor 1b continues and the timer set time ta of the wait timer 7a is exceeded, the timer signal TIME-A is output to the access right determination means 5.
[0034]
When the access right determination means 5 detects the timer signal TIME-A, the switching signal SEL is changed from the B side to the A side when the read signal RD-B or the write signal WR-B from the microprocessor 1b is once terminated. Switch.
[0035]
The switching means 6 changes the read signal RD, the write signal WR, the address signal ADRS, and the data signal DATA from the read signal RD-B to the read signal RD-A because the switch signal SEL changes from the B side to the A side. The write signal WR-B is switched to the write signal WR-A, the address signal ADRS-B is switched to the address signal ADRS-A, and the data signal DATA-B is switched to the data signal DATA-A.
[0036]
With the configuration described above, the access waiting state of the microprocessors 1a and 1b does not exceed a predetermined time, so that the calculation performance of the microprocessors 1a and 1b can be prevented from being lowered, and emergency processing such as interrupt processing is also predetermined. You will be able to respond within hours.
[0037]
Note that the timer setting times ta and tb of the wait timer can be set individually for each microprocessor. In this case, the timer setting times ta and tb of the wait timer can be set in advance according to the priority. Calculation performance can be improved.
[0038]
Next, a second embodiment of the present invention will be described with reference to the drawings. Note that the same components as those in the above-described embodiment are denoted by the same reference numerals and description thereof is omitted as appropriate.
[0039]
FIG. 3 is a block diagram showing a schematic configuration of a multi-port memory applied to the description of the present embodiment, which is basically the same as the configuration shown in FIG. 1, but omits the wait timer 7b in FIG. The point which I did is greatly different.
[0040]
In other words, the arbitration circuit 2 has a wait timer 7a that detects that an access wait state has continued for a predetermined time or more from the wait signal WAIT-A and outputs a timer signal TIME-A, and is accessed simultaneously from a plurality of microprocessors 1a and 1b. Even if this occurs, the microprocessor 1a waits for access within a predetermined time.
[0041]
FIG. 4 is a timing chart of such a configuration. When the microprocessor 1b continues to access, the timer signal WAIT-A is output to the access right determination means 5 when the wait timer 7a counts the timer set time ta. .
[0042]
When the access right determination means 5 detects the timer signal WAIT-A, the switching signal SEL is changed from the B side to the A side when the read signal RD-B or the write signal WR-B from the microprocessor 1b is once terminated. Switch.
[0043]
The switching means 6 changes the read signal RD, the write signal WR, the address signal ADRS, and the data signal DATA from the B side read signal RD-B to the A side read signal when the switch signal SEL changes from the B side to the A side. RD-A, B-side write signal WR-B to A-side write signal WR-A, B-side address signal ADRS-B to A-side address signal ADRS-A, B-side data signal DATA-B to A Each is switched to the side data signal DATA-A.
[0044]
Similarly, when the microprocessor 1b performs access, an access signal CS-B is output to the access right determination means 5.
[0045]
The access right determining means 5 switches the switching signal SEL from the A side to the B side when the read signal RD-A or the write signal WR-A from the microprocessor 1a is once finished.
[0046]
As described above, when the access of the microprocessor 1b continues, when the wait timer 7a detects that the access continues for the timer set time ta or more, the timer signal TIME-A is output to the access right determination means 5, and the access right Since the judging means 5 switches the access right to the A side, the access waiting state of the microprocessor 1a can be prevented from exceeding a predetermined time.
[0047]
Therefore, it is possible to suppress a decrease in the calculation performance of the microprocessor 1a, and it is possible to respond to an emergency process such as an interrupt process within a predetermined time, thereby improving the calculation performance.
[0048]
Next, a third embodiment of the present invention will be described with reference to the drawings. Note that the same components as those in the above-described embodiment are denoted by the same reference numerals and description thereof is omitted as appropriate.
[0049]
FIG. 5 is a block diagram showing a schematic configuration of a multi-port memory applied to the description of the present embodiment, which is basically the same as the configuration shown in FIG. 1, but the wait timers 7a and 7b in FIG. The timer setting times ta and tb can be set from the microprocessors 1a and 1b.
[0050]
That is, when the arbitration circuit 2 detects from the wait signals WAIT-A and WAIT-B that the access waiting state has continued for a predetermined time or more, the timers in the wait timers 7a and 7b that output the timer signals TIME-A and TIME-B The set times ta and tb can be set individually.
[0051]
As a result, the timer setting times ta and tb can be set from the microprocessors 1a and 1b according to the priority of the microprocessors 1a and 1b, and the degradation of the arithmetic performance of the microprocessors 1a and 1b is suppressed, interrupt processing, and the like. It becomes possible to respond to the emergency process within a predetermined time.
[0052]
Next, a fourth embodiment of the present invention will be described with reference to the drawings. Note that the same components as those in the above-described embodiment are denoted by the same reference numerals and description thereof is omitted as appropriate.
[0053]
FIG. 6 is a block diagram showing a schematic configuration of a multiport memory applied to the description of the present embodiment. Wait signals WAIT-A and WAIT- are used in place of the wait timers 7a and 7b in the arbitration circuit 2 shown in FIG. A plurality of wait counters for detecting a read signal RD or a write signal WR more than a certain number of times from B, that is, detecting that there are more than a certain number of accesses in an access waiting state and outputting count signals CNT-A and CNT-B The difference is that 8a and 8b are provided.
[0054]
This makes it possible to switch the access right with a certain number of accesses even when accesses are made simultaneously from the plurality of microprocessors 1a and 1b.
[0055]
FIG. 7 is a timing chart of such a configuration. When the access signal CS-B of the microprocessor 1b is input while the microprocessor 1a is accessing, the access right determination means 5 sends the wait signal WAIT- on the B side to the microprocessor 1b. B is output, and the microprocessor 1b enters an access waiting state by the wait signal WAIT-B.
[0056]
When the microprocessor 1a continues to access and exceeds the counter setting number nb of the B-side wait counter 8b, the B-side count signal CNT-B is output to the access right determining means 5.
[0057]
When the access right determination means 5 detects the count signal CNT-B on the B side, when the read signal RD-A or the write signal WR-A from the microprocessor 1a is once terminated, the access right determination means 5 sends the switching signal SEL from the A side. Change to B side.
[0058]
The switching means 6 changes the read signal RD, the write signal WR, the address signal ADRS, and the data signal DATA from the read signal RD-A to the read signal RD-B by changing the switching signal SEL from the A side to the B side. The write signal WR-B is switched to the write signal WR-B, the address signal ADRS-A is switched to the address signal ADRS-B, and the data signal DATA-A is switched to the data signal DATA-B.
[0059]
Similarly, when the access signal CS-A of the microprocessor 1a is input while the microprocessor 1b is accessing, the access right determination means 5 returns a wait signal WAIT-A to the microprocessor 1a.
[0060]
When the wait signal WAIT-A becomes valid, the microprocessor 1a enters an access waiting state.
[0061]
When the microprocessor 1b continues to access and exceeds the counter set number na of the wait counter 8a, the count signal CNT-A is output to the access right determination means 5.
[0062]
When the access right determination means 5 detects the count signal CNT-A, the switching signal SEL is changed from the B side to the A side when the read signal RD-B or the write signal WR-B from the microprocessor 1b is once finished. Change.
[0063]
The switching means 6 changes the read signal RD, the write signal WR, the address signal ADRS, and the data signal DATA from the read signal RD-B to the read signal RD-A due to the change of the switch signal SEL from the B side to the A side. The write signal WR-B is switched to the write signal WR-A, the address signal ADRS-B is switched to the address signal ADRS-A, and the data signal DATA-B is switched to the data signal DATA-A.
[0064]
In this manner, when the accesses of the microprocessor 1a or the microprocessor 1b are continued, it is detected that the wait counters 8a and 8b have continued for a certain number of accesses, and the count signals CNT-A and CNT-B are used as the access right determination means 5. The access right determination means 5 switches the switching signal SEL to the side from which the wait signals WAIT-A and WAIT-B are output, so that the access waiting state of the microprocessors 1a and 1b does not exceed a predetermined time. Thus, it is possible to respond within a predetermined time even for an emergency process such as an interrupt process and the like, which suppresses a decrease in the computing performance of the microprocessors 1a and 1b.
[0065]
Further, the count setting values na and nb of the wait counter can be set in advance according to the priority, so that the calculation performance can be improved.
[0066]
It should be noted that the count settings na and nb of the wait counter can be set individually for each of the microprocessors 1a and 1b.
[0067]
Next, a fifth embodiment of the present invention will be described with reference to the drawings. Note that the same components as those in the above-described embodiment are denoted by the same reference numerals and description thereof is omitted as appropriate.
[0068]
FIG. 8 is a block diagram showing a schematic configuration of a multi-port memory applied to the description of the present embodiment. In this configuration, the weight counter 8b is omitted from the configuration shown in FIG.
[0069]
Thus, even if access is simultaneously generated from the plurality of microprocessors 1a and 1b by the wait counter 8a that detects from the wait signal WAIT-A that the access waiting state has continued for a predetermined time or more and outputs the count signal CNT-A. The access right of the microprocessor 1a can be acquired within a predetermined time.
[0070]
FIG. 9 is a timing chart of such a configuration. When the microprocessor 1b continues to access, the count signal CNT-A is output to the access right determination means 5 when the count set value na of the wait counter 8a is exceeded. .
[0071]
When the access right determination means 5 detects the count signal CNT-A, when the read signal RD-B or write signal WR-B from the microprocessor 1b is once terminated, the access right determination means 5 changes the switching signal SEL from the B side to the A side. Change.
[0072]
The switching means 6 changes the read signal RD, the write signal WR, the address signal ADRS, and the data signal DATA from the read signal RD-B to the read signal RD-A due to the change of the switch signal SEL from the B side to the A side. The write signal WR-B is switched to the write signal WR-A, the address signal ADRS-B is switched to the A-side address signal ADRS-A, and the data signal DATA-B is switched to the data signal DATA-A.
[0073]
Similarly, when the microprocessor 1b performs access, an access signal CS-B is output to the access right determination means 5.
[0074]
The access right determining means 5 switches the switching signal SEL from the A side to the B side when the read signal RD-A or the write signal WR-A from the microprocessor 1a is once finished.
[0075]
In this way, when the access of the microprocessor 1b is continued, the wait counter 8a detects that the access continues for the count set value na or more, and outputs the count signal CNT-A to the access right determination means 5 to determine the access right. Since the means 5 switches the access right to the A side, the access waiting state of the microprocessor 1a can be prevented from exceeding a predetermined time.
[0076]
Accordingly, it is possible to improve the computing performance by suppressing the computing performance of the microprocessor 1a from being lowered and responding to emergency processing such as interrupt processing within a predetermined time.
[0077]
Next, a sixth embodiment of the present invention will be described with reference to the drawings. Note that the same components as those in the above-described embodiment are denoted by the same reference numerals and description thereof is omitted as appropriate.
[0078]
FIG. 10 is a block diagram showing a schematic configuration of a multiport memory applied to the description of the present embodiment. In the arbitration circuit 2 shown in FIG. 6, the count setting values na and nb of the wait counters 8a and 8b can be set. It is what I did.
[0079]
That is, in the wait counters 8a and 8b, which detect that there has been an access from the wait signals WAIT-A and WAIT-B for a certain number of times and output the count signals CNT-A and CNT-B, nb can be varied, and the count setting values na and nb can be dynamically set from the microprocessors 1a and 1b in accordance with the priorities of the microprocessors 1a and 1b.
[0080]
As a result, as in the fourth embodiment, it becomes possible to prevent the microprocessors 1a and 1b from waiting for an access for a predetermined time or longer, and set the count setting values na and nb of the wait counters 8a and 8b individually. It is also possible to set, and the calculation performance can be improved.
[0081]
【The invention's effect】
As described above, according to the present invention, when the arbitration circuit detects that the access waiting state has continued for a predetermined time or more from the wait signal, it outputs a timer signal or a count signal, When the access signals from the processors compete, a switching signal is output so that one microprocessor can access the multi-port memory based on the timer signal or the count signal, and the other microprocessor waits for access. Since there is provided an access right judging means for outputting a signal and a switching means for switching the signal from the corresponding microprocessor based on the switching signal and outputting it to the single-port memory so that it can be accessed. If the waiting state is longer than the specified time Can be odd, operation performance of the microprocessor will be able suppressed from being lowered.
[Brief description of the drawings]
FIG. 1 is a configuration diagram of a multiport memory according to a first embodiment of the present invention.
FIG. 2 is a timing chart of the multiport memory according to the first embodiment of the present invention.
FIG. 3 is a configuration diagram of a multiport memory according to a second embodiment of the present invention.
FIG. 4 is a timing chart of the multi-port memory according to the second embodiment of the present invention.
FIG. 5 is a configuration diagram of a multiport memory according to a third embodiment of the present invention.
FIG. 6 is a configuration diagram of a multi-port memory according to a fourth embodiment of the present invention.
FIG. 7 is a timing chart of the multi-port memory according to the fourth embodiment of the present invention.
FIG. 8 is a configuration diagram of a multiport memory according to a fifth embodiment of the present invention.
FIG. 9 is a timing chart of the multiport memory according to the fifth embodiment of the present invention.
FIG. 10 is a configuration diagram of a multi-port memory according to a sixth embodiment of the present invention.
FIG. 11 is a configuration diagram of a conventional multi-port memory.
FIG. 12 is a timing chart of a conventional multiport memory.
[Explanation of symbols]
1a, 1b microprocessor
2 Arbitration circuit
3 Single port memory
4 Multiport memory
5 Access right judgment means
6 Switching means
7a, 7b Wait timer
8a, 8b Weight counter

Claims (6)

When an access conflict between a single port memory and a plurality of microprocessors occurs in the single port memory, access is permitted to one of the microprocessors, and a wait signal is sent to the other microprocessor. In a multi-port memory having an arbitration circuit that arbitrates access by outputting and waiting for access,
The arbitration circuit counts the output duration time of the wait signal to the other microprocessor, and a wait timer that outputs a timer signal when the counted time reaches a predetermined time;
When the timer signal is received, access right determination means for outputting a switching signal so that the access to the multi-port memory by the other microprocessor can be performed after the access of the one microprocessor is once completed,
A multi-port memory comprising switching means for switching so that the corresponding microprocessor can access the single-port memory based on the switching signal.   2. The multiport memory according to claim 1, wherein the wait timer is provided only in one of the microprocessors.   3. The multiport memory according to claim 1, wherein the wait time in the wait timer can be variably set. When an access conflict between a single port memory and a plurality of microprocessors occurs in the single port memory, access is permitted to one of the microprocessors, and a wait signal is sent to the other microprocessor. In a multi-port memory having an arbitration circuit that arbitrates access by outputting and waiting for access,
The arbitration circuit detects the wait signal for the other microprocessor and the read signal or write signal from the one microprocessor, and the number of detections reaches a predetermined number regardless of the coincidence or mismatch of the number of detections. Then, a wait counter that outputs a count signal,
When the count signal is received, access right determination means for outputting a switching signal so that the access to the multi-port memory by the other microprocessor can be performed after the access of the one microprocessor is once completed,
A multi-port memory comprising switching means for switching so that the corresponding microprocessor can access the single-port memory based on the switching signal.   5. The multiport memory according to claim 4, wherein the weight counter is provided only in one of the microprocessors.   6. The multiport memory according to claim 4, wherein a predetermined value in the weight counter can be set variably.

Images