JP4540958B2 - Image sensor array, computer input device and method for indicating relative differences in pixel illumination - Google Patents

Abstract

A signal generator produces multi-outbound comparison signals based on initial signal corresponding to illumination of photosensor, and internal comparison signal based on initial signal. The comparison signal is input to neighboring pixels through summing node (110). A comparator (116) outputs a signal indicating relative difference in pixel illumination based on internal comparison signal and summed input signals. Independent claims are also included for the following: (1) computer input device; (2) method for indicating relative difference in illumination of pixels within image sensor array.

Description

  The present invention relates to processing an output from a photosensor as part of an image system, and more particularly to an analog photosensor array that performs a DC removal process at a pixel level.

  With photo-sensitive electronic components, electronic imaging systems such as systems that detect and measure motion can be constructed. When such an electronic imaging system is used for motion detection, obtaining a very detailed image of an area or object means that one particular image changes compared to the previous image. It may be less important than determining whether it reflects. For this reason, higher importance may be placed on the contrast between adjacent image elements.

  One application example of motion detection is a computer position indicating device or an input device (for example, a computer mouse). For example, Patent Literature 1 and Patent Literature 2 describe using an electronic image for such a purpose. As described in these patent documents, when light from an associated illumination source (e.g., a light emitting diode) is reflected from other surfaces on the desk, the photosensitive element array displays an image on the desk (or other surface). Generate. Subsequent images can be compared and the magnitude and direction of mouse (or other device) movement can be determined based on the correlation between the images.

FIG. 1 shows a pixel in a photosensor array structure used in an existing computer input device. Each pixel of the photosensor array includes a photosensor 10 that can be a photodiode or other photosensitive component. Prior to acquiring an image, the node INT is charged to the reference voltage V _ref by a RESET signal applied to the NMOS transistor 12. When the RESET signal is not asserted, light reflected from the desk or other surface illuminates the photosensor 10 so that reverse bias current can flow through the photosensor 10 to ground. The node INT is then discharged due to the reverse bias current through the photosensor 10. The greater the light intensity in response to a more reflective object or surface feature (the brighter the light), the greater the reverse bias current through the photosensor 10, so that the node INT is faster. Discharge. Conversely, the lower the intensity of light in response to reflections from darker objects or surface features (ie, darker), the smaller the reverse bias current through photosensor 10 and the slower the discharge of node INT. become. The voltage applied to the node INT controls the gate of the NMOS transistor 14. That is, when the charge on the node INT is released, the bias applied to the NMOS 14 is reduced in response to this, whereby the voltage at the node 16 drops. At some specified time, a SELECT signal is applied to the gate of NMOS 18 so that charge is stored in storage capacitor 20. The voltage across the NMOS 14 changes according to the gate voltage of the NMOS 14. That is, it changes according to the illumination intensity hitting the photosensor 10. Therefore, the magnitude of the accumulated voltage applied to the storage capacitor 20 is related to the illumination intensity hitting the photosensor 10. Since the reflected illumination intensity will vary based on the surface features of the desk or other surface, the charge on the storage capacitor 20 is utilized (as part of the photosensor pixel array) to provide a desk or other work surface. Change in position can be detected and measured.

  The voltage across each capacitor in the array passes through the MUX (multiplexer) and reaches the ADC (analog-to-digital converter). The ADC outputs a digital value corresponding to the voltage across the storage capacitor, which represents the relative intensity of illumination that strikes the photosensors in the array. This digital value then passes through a DCR (digital direct current removal) process to enhance the contrast of the image and reduce the number of storage elements required to store the resulting image. A subsequent correlator compares the DCR processed image data with the previous DCR processed image data and generates navigation data reflecting the magnitude and direction of the device motion.

  In the example of FIG. 1, a separate storage capacitor is required to store the value for each photosensor in the array. In general, storage capacitors are placed on both sides of the array and require a relatively large area on the IC (integrated circuit). This structure is also susceptible to parasitic signal coupling, capacitor leakage and charge injection, and can only be stored for a relatively short time without destroying the image. In addition, this structure presents problems associated with digital-oriented ASIC (application specific integrated circuit) technology, which can be accompanied by large sub-threshold leakage and low supply voltage.

  In the structure shown in FIG. 1, the ADC function and the subsequent DCR processing are all performed in a bit unit serial method, that is, a method of one pixel at a time. Each pixel value from the ADC may be multiple bits long, and considerable digital circuitry may be required to DCR process all pixel values. This additional circuit requires additional IC area, which increases cost. In addition, this processing must be performed at a high speed (about 100 microseconds). In applications requiring high speed (such as computer mouse motion detection), a high-speed ADC that serially converts each pixel and a high-speed digital circuit that serially increases the contrast of each pixel are required. Considerable digital memory is also required to store multiple bits of data for each pixel. Although a plurality of ADCs and other digital circuit components can be mounted to process a plurality of pixels in parallel, the plurality of components required for the parallel processing must have matching characteristics. In such parallel processing, the required power also increases.

US Pat. No. 6,303,924 US Pat. No. 6,172,354

  Therefore, there is still a need to improve electronic image processing systems for motion detection.

  The photosensor of the present invention provides DCR (direct current removal) processing and contrast enhancement signal processing in the pixel level analog domain. By performing DCR at the pixel level, separate (ie, extra-pixel) ADC (analog-to-digital conversion) and DCR processing is no longer required. In one embodiment, each pixel cell generates 1 bit of DCR processed (“DCRed”) image data. This pixel bit value can then be stored in memory and image correlation processing can be performed at any desired time. In another embodiment, one or more additional bits may be provided for each pixel. The two-dimensional array pixels according to the present invention reduce the storage requirements of the entire image processing chip.

  With the pixel cell of the present invention, the analog and digital circuits of the pixel cell array can be reduced. Such pixel analog circuitry facilitates the incorporation of arrays of such pixels into newer digitally oriented ASIC (application specific integrated circuit) technology that utilizes low supply voltages. With the pixel cell of the present invention, chip cost and test time can also be reduced. Further, in general, as the complexity of pixel analog circuit design is reduced, it is less susceptible to sub-threshold leakage and gate leakage that may occur in connection with modern digital ASICs. The pixel cell also consumes less static supply current, thereby increasing battery life when used in battery powered devices. For example, switching current is reduced by operating at a slower clock speed than required for conventional approaches such as high-speed serial processing.

  The present invention can include a photosensor pixel cell array, where each pixel cell includes an analog circuit that generates an initial signal in response to radiation illuminating the pixel. The magnitude of the initial signal changes according to the illumination intensity. In one embodiment, the initial signal is a current. Each pixel then generates a plurality of comparison signals based on its initial signal and sends the comparison signal to each of several adjacent pixels. A plurality of pixels in the array receive comparison signals from their respective neighboring pixels. Each pixel that receives a signal sums the comparison signals received from its neighboring pixels. The summed signal is then compared to the internal comparison signal. The comparison result can then be used to store a digital data value representing the DCR processed image data for that pixel.

  Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings.

  FIG. 2 is a block diagram of an array 100 having m rows × n columns of pixels. The array 100 (which could be formed as part of an integrated circuit) can form part of an electronic imaging device. In operation, the array 100 can be configured to receive light reflected from a surface (or object), thereby generating an image of the surface (or object). Array 100 is connected to a control device (eg, additional circuitry on the same IC (not shown) and / or one or more other processors, also not shown). Except as indicated below, no details of such components are necessary to understand the present invention. Suitable hardware and software (or firmware) for implementing the photosensor array of the present invention will be apparent to those skilled in the art from the information provided herein.

Emphatically that shown in FIG. 2 is a sub-array 101 of nine contiguous pixels located at any position within the array 100, the pixel is labeled from each 100 ₀ 100 _8. Except as noted below, in general, pixels in subarray 101 are representative of other non-edge pixels in array 100. The edge pixels shown in FIG. 2 with projection lines are similar to non-edge pixels, but lack certain circuitry and functions described in more detail below. In operation, a non-edge pixel in array 100 compares its output with the output of an adjacent pixel. Based on this comparison, one (or more) data bits representing the DCR processed image data are stored for that pixel. In one embodiment, if the output of a pixel is greater than the value based on the outputs of the eight nearest neighbor pixels, the pixel latches the value “1”. Otherwise, the pixel latches the value “0”. That is, using pixels 100 ₀ to 100 ₈ as an example, the value 1 is assigned to the central pixel 100 ₀ if Equation 1 is true.

However, it is S (100 _i) is an analog output signal of the pixel 100 _i, alpha _i is the gain associated with the pixel 100 _i (or attenuation).

  Table 1 gives an example of a gain value applied to each pixel in the 3 × 3 subarray, for example, the subarray 101, when performing the DCR function according to Expression (1).

The values in Table 1 are merely examples of possible gain values that can be applied, and other values of gain (or attenuation) are within the scope of the present invention. In fact, the pixel array according to the present invention can be implemented with many combinations of desired values, thereby allowing many different DCR filter transformations to be performed. Additional examples include, but are not limited to, the values shown in Tables 2 and 3.

FIG. 3 is an enlarged block diagram of the pixels 100 _{0 to} 100 ₈ of the subarray 101. Pixel 100 ₀ at the center of the sub-array 101 is surrounded taken eight nearest neighbor pixels ₁₀₀ 1 to 100 _8. Each pixel of the subarray 101 includes a current summing node 110, an integrating circuit 112, a comparison current generator circuit 114, a comparator circuit 116, a serial scan latch 118 and a buffer 120. The components of the other pixels in subarray 101 are substantially the same and do not label all of the pixel components in FIG. 3 so as not to unnecessarily obscure the drawing. However, the input to the current addition node of each pixel is different. As shown in FIG. 3, the current summing node 110 of the pixel 100 ₀ includes eight each one by one out to have eight inputs from the nearest neighbor pixels. More specifically, the input "1" is input from the pixel 100 _1, inputs "2" input from the pixel 100 _2, and so on. Similarly, when the pixels immediately above the pixels 100 ₁ to 100 ₃ are referred to as “100 _a ”, “100 _b ”, and “100 _c ”, the input to the current addition node of the pixel 100 ₂ is the pixels 100 _a , 100 _b. , 100 _c , 100 ₁ , 100 ₃ , 100 ₄ , 100 ₀ and 100 ₅ (or a, b, c ₁ , ₃ , ₄ , ₀ and ₅ as shown in FIG. 3). Inputs to the current summing nodes of other pixels should be able to follow a similar pattern. The large thick arrows in FIG. 3 simply represent possible paths through which the output from a pixel can be sent to its neighboring pixels, not to represent the connection from one pixel to another in the array. As will be described in more detail below, the edge pixels in array 100 may not perform all the functions performed by non-edge pixels, such as those in sub-array 101, and thus certain components shown in FIG. May be missing.

Figure 4 is a more detailed schematic diagram of the pixel 100 _0. As in the block diagram of FIG. 3, the schematic of the other non-edge pixels in the array 100 should be approximately the same, but the input to the current summing node 110 for each pixel should be different. is there. Components corresponding to the integration circuit 112 in FIG. 3 are surrounded by a dashed box labeled 112 in FIG. Similarly, components corresponding to the comparison current generator circuit 114, the comparator circuit 116, and the current summing node 110 of FIG. 3 are also surrounded by boxes labeled with corresponding numbers in FIG. Details of serial scan output latch 118 and buffer 120 are not shown. Since the configuration of the circuits and components for the latch and buffer are within the knowledge of those skilled in the art, these details will not be described. The integrating circuit 112 includes PMOS devices 132 and 134 and a photodiode 136. Devices 132 and 134 form charge cancellation switches to charge node A to reference voltage V _ref in advance. As will be described in more detail below, the light striking the photodiode 136 causes a reverse current to flow through the photodiode 136, thereby discharging node A and reducing the integrated voltage (V _int ) at node A. The amount that node A discharges (and V _ref decreases) during the integration phase modulates the initial current I ₀ through the initial current generator formed by NMOS devices 138 and 140 and PMOS device 142. The maximum value of the current I ₀ is adjusted by the NMOS device 140. The NMOS device 140 can be a device with a long channel length that emulates a linear resistance. By using the current I ₀ as a reference, the comparison current generator formed by the PMOS reference device 142 and the PMOS mirroring devices 143 to 151 allows a plurality of comparison currents (which may each have a different magnitude). Generated. As shown in FIG. 4, by appropriately sizing the device in the PMOS comparison current generator, I ₀ is multiplied by 1 (× 1) in size (corresponding to α ₁ to α ₈ ) 8 one of the comparison current is generated (corresponding to alpha ₀₎ multiplied by 8 to I ₀ (× 8) in size one comparison current is generated. Table 1 and Equation 1 As can be seen by comparison with FIG. 4, the values of these comparative current gain value of the pixel 100 ₀ in Table 1 is obtained. Alternatively, it should be possible to size the device in the pixel to obtain the gain values shown in Table 2 or Table 3, or other desired values. The gain value and attenuation value may be the same for each pixel or may vary between pixels of the array. By selecting the appropriate component, a comparative threshold with many options is available.

As shown in FIGS. 3 and 4, the 1 × comparison current is input to one current summing node of adjacent pixels 100 ₁ , 100 ₂ , 100 ₃ , 100 ₄ , 100 ₅ , 100 ₆ , 100 ₇ and 100 ₈ , respectively. Is done. "Internal" from PMOS device 147 compares current (i.e., emitted from the pixels 100 within ₀₎ 8 times is input to the current-mode comparator circuit 116 of the pixel 100 _0. Comparator circuit 116 includes a composite charge cancellation device 158 (shown as one NMOS in FIG. 4) and NMOS devices 154 and 156 matched to each other. When the STROBE signal is high, the STROBE signal keeps the comparator 116 in equilibrium. "External" 1 times from the comparison current generator of each neighboring pixel (i.e., originating from the adjacent pixels) comparing current is input to the current summing node 110 of the pixel 100 ₀ where summed. Current summing node 110 is also coupled to latch 118 (also not shown) via buffer 120 (not shown). When the STROBE signal goes from high to low, the comparator 116 compares the internal 8 × comparison current with the sum of the external 1 × comparison current from each of the 8 adjacent pixels. If the internal 8x comparison current is greater than the sum of the 8 external comparison currents, the external comparison current is grounded through NMOS device 156 and the signal to latch 118 goes low. However, if the internal 8x comparison current is less than the sum of the external comparison currents, the summed current is not completely grounded and the signal to the latch 118 goes high.

  In the above embodiment, the m × n pixel array is reduced to an array having (m−2) × (n−2) pixel data values. The pixels at the outer edge of the array 100 (see FIG. 2) provide a 1 × comparison current to adjacent pixels that are not on the edge, but the edge pixel has a comparison current of 8 × its own initial current. And the image data is not stored for the edge pixels. As an example, if n = 20 and m = 20, the array 100 is a 400 pixel array, but only 324 (ie, (20-2) × (20-2)) data bits are generated for each image. do not do. Since edge pixels do not perform comparison or latching functions, circuitry for these functions can be omitted. In an alternative embodiment, it would be possible to configure the edge pixels to perform comparison and latching functions by using a modified version of the comparison representation for non-edge pixels. Table 4 shows examples of possible gain values in the case of such a modified expression.

In the example of Table 4, α ₀ corresponds to a pixel located in the middle of the left edge (ie, not a corner) in FIG. Since there is no pixel on the left side of the pixel, α ₁ , α _4, and α ₆ are 0.

  3 and 4 show at least one advantage of the present invention in construction compared to that shown in FIG. Instead of converting each pixel value into a multi-bit digital value and then performing a DCR process on the digital value, DC component removal is now achieved in the analog domain of each pixel. Each pixel performs its DCR processing in parallel, thereby eliminating the need for high speed digital signal processing on each pixel in a serial fashion. Each non-edge pixel generates a high or low signal, which is latched when the STROBE signal is low. This latching operation can occur in each pixel, but is also performed for all non-edge pixels in the array simultaneously. When the STROBE signal is low, the voltage at node C in each non-edge pixel is maintained at a high or low value based on a comparison with the current received from adjacent pixels. This high or low voltage passes through each pixel's buffer 120 to the pixel's latch 118 and is stored as a 1-bit value. When the STROBE signal is high, the comparator 116 is in equilibrium and the voltage at node C will be at an intermediate value. Since such an accidental latch of intermediate values can produce unpredictable results, the buffer 120 is skewed to prevent a voltage signal that is less than the threshold from reaching the latch 118 (see FIG. skewed threshold).

After all the comparator outputs are latched, the latched value for each pixel row is linked to the scan chain, and then the scan chain is serially read into memory for each row by the scan clock signal (shown in the drawing). No) and then correlation with the previous image data is taken. Memory and correlation circuitry (also not shown) may be placed outside the array 100. FIG. 5 illustrates one possible configuration and method for reading data for each pixel in a row (or column) of the array 100. FIG. 5 shows in block form the five latches 118 _i of an array of pixels in the array 100 for a plurality of clock cycles. As an example, the five latches (corresponding to the pixel _{100 b,} 100 2, 100 ₀ and 100 ₇₎ in FIG. 3 and the latch _{118 b,} 118 2, 118 ₀ and 118 _7, immediately above the pixel 100 _b it should be possible to represent together with additional latch from the pixel immediately below the pixel or pixel 100 _7. This arrangement may include more than five latches 118. The presence of additional latches is indicated by three dots on the left side of each stage. Cycle 0 represents a time point just before reading the latched value. Each latch contains a 1-bit value, labeled (cycle 0) and shown at the top of FIG. At the end of the first cycle, the value of each latch is shifted one place to the right and the rightmost latched value is read and stored. At the end of the second clock cycle, the latched value is still shifted one place to the right and the rightmost value is concatenated with the previously stored value. Reading continues until all latches in the row are read and the latched value is stored (labeled (cycle n)). Reading all rows of the array simultaneously in this manner will read the pixel values for the entire column during each clock cycle (assuming that the values are not latched for pixels located at the edge of the array). The image from is scanned in 18 clock cycles. This represents one possible way of reading data, but other methods and configurations are within the scope of the present invention.

FIG. 6 is a timing diagram of the operation of the non-edge pixel 100 _i in the array 100. Pixel operation includes four stages. That is, reset, integrate, convert, and serial output. FIG. 6 also shows the “correlation” and “navigation” stages. These steps refer to the correlation between the pixel image data and the previous image data, and the calculation of motion based on this correlation. In the embodiment described here, the correlation and navigation takes place outside the pixel array 100 and will not be described further here. The first line in FIG. 6 labeled V _int reflects the voltage at node A of pixel 100 _i . The second line labeled data reflects the value latched by pixel 100 _i for a given image after comparison with the signal received from the neighboring pixel (the neighboring pixel signal value is not shown in FIG. 6). ). The “I _bias ” line in FIG. 6 indicates whether a bias current is applied to the NMOS 140 and the “strobe” line indicates whether the STROBE signal is high or low. The “scan clock” line indicates the time when the value of the latch 118 is read for each column of a plurality of pixels. The latched value of pixel 100 _i (latch 118 _i ) should be read in the clock cycle corresponding to the column in which pixel 100 _i is located. For example, when the pixel 100 _i is a pixel 100 ₃ of FIG. 3, the latch 118 _third pixel 100 ₃ should be read in the same clock cycle as the latch 118 ₁ and 118 ₂ of the pixels 100 ₁ and 100 _2.

At t = 0 in FIG. 6, the pixel is already in the reset phase. During reset, for each pixel (including the edge pixels), the voltage V _int at node A is pulled to a common reference voltage V _ref by the operation of devices 132 and 134. During the reset phase, the RESET signal goes high, preventing current from flowing through the PMOS 134, the NRESET signal goes low, and current can flow through the PMOS 132. PMOS devices 132 and 134 provide a charge cancellation circuit for canceling unwanted charge injected into node A. Adjacent pixels should have matched optical and electrical performance characteristics, but charge cancellation circuitry reduces fixed pattern noise (FPN) caused by potential mismatch in the amount of charge injected into adjacent cells To help.

In the integration phase, the RESET signal goes low and the NRESET signal goes high, enabling the light source. The light source can be a light emitting diode (LED) arranged to reflect light from the desk or other surface to the array 100 or other selectively available light source. The I _bias signal goes high so that the initial current I ₀ can flow through the NMOS devices 140, 138 and 142. As shown in FIG. 6, in order to conserve power during the reset phase, I _bias can be _disabled . Since the light intensity is not measured when the array is in the reset phase, there is no need to modulate the value of I ₀ based on V _ref , and I _bias can be _disabled to _conserve power. Alternatively, _Ibias could be left enabled. When light enters the photodiode 136, the current through the photodiode 136 discharges the integration node A and V _int drops. As shown in FIG. 6, V _int decreases during the integration phase. The slope of this decrease corresponds to the rate at which node A discharges and corresponds to the magnitude of the reverse bias current through the illuminated photodiode 136. Since the current through the photodiode 136 increases as the illumination increases, the slope of V _int varies with the intensity of light striking the photodiode 136.

The light source is disabled at the end of the integration phase. Since the dark current through the photodiode 136 (ie, reverse bias current in the absence of illumination) is sufficiently small, V _int remains at the level reached at the end of the integration phase. As can be seen from FIG. 6, this level corresponds to the lower limit of the voltage decrease. FIG. 6 shows two types of voltage reduction. The decrease indicated by the solid line corresponds to the voltage drop associated with more intense (ie, “brighter”) illumination of the photodiode 136, with more reflective object or surface features present (or more object or surface features). Highly reflective state). As the current through the photodiode 136 is larger, node A discharges rapidly and the decrease becomes steeper. Conversely, the reduction indicated by the dashed line corresponds to a voltage drop associated with illuminating the photodiode 136 weaker (ie, “darker”), with no reflective object or surface feature present (or object or surface failure). The feature is less reflective). The smaller the current through the photodiode 136, the more slowly the node A discharges and the slower the decrease. Since the voltage V _{int at} node A biases the gate of NMOS 138, the magnitude of I ₀ is modulated by the magnitude of V _int . _Therefore, as _{V int} is greater _{I 0} is _increased, as the _{V int} is small _{I 0} becomes smaller. V _int (and thus I ₀ ) continues to decrease throughout the integration phase. As long as the current I ₀ flows, the comparison current can be generated with the comparison current generator. When the light source is disabled at the end of the integration phase, the dark current through the photodiode is small, so at the time when the light is disabled (ie at the end of the integration phase) the decrease in magnitude of I ₀ is It stops and the corresponding decrease in the magnitude of the comparison current also stops.

After the integration stage, the conversion stage is entered. At the end of the integration phase, one input to the comparator 116 _i of the pixel 100 _i is eight times the comparison current from the comparison current generator of the pixel. That is, the comparison current, at the end of the integration phase (i.e., when the light is disabled) corresponds to eight times the size of the I ₀ of the pixel in the. Using the solid line V _int of FIG. 6 and the schematic diagram of FIG. 4 as an example, an initial current equal to 8 times I ₀ corresponding to V _bright is input from the PMOS 147 to the node B. A sum of eight external comparison currents from the comparison current generators of the adjacent pixels is input to node C. Therefore, the current at node C corresponds to the sum of the magnitudes of currents I ₀ from the eight adjacent pixels at the end of the integration phase. When the STROBE signal is high, comparator 116 _i is maintained in equilibrium. Near the end of the conversion phase, the STROBE signal goes low, the NMOS device 158 is turned off, and the relative strength of the inputs to nodes B and C are compared. If the input to node B is larger, the total external current is grounded through NMOS device 156 and the voltage at node C goes low. However, if the input at node B is smaller than the input at node C, the total current is not completely grounded and the voltage at node C remains high.

When the STROBE signal is low, “0” or “1” is latched in the latch 118 _i by the voltage of the node C. FIG. 6 shows that the value of the data line becomes high when the strobe signal is low. As a result, “1” is latched in the latch 118 _i of the pixel 100 _i . However, it is important to note that the high value of pixel 100 _i shown on the data line in FIG. 6 is not simply based on the illumination brightness of one pixel 100 _i . Instead, the value of the data line (high or low) is based on a comparison of the internal current signal in pixel 100 _i corresponding to V _bright with current signals provided from other pixels. If enough of these other pixels are also illuminated so that their respective integration node voltages are sufficiently close to V _bright , the value of the data line of pixel 100 _i will probably be low ( That is, “0” should be latched). Thus, the latched value represents the DCR value of one pixel (eg, pixel 100 _{0 in} FIGS. 2 and 3) compared to an adjacent pixel in the subarray. In other words, the latched value represents the relative intensity of the illumination hitting a pixel compared to the illumination of an adjacent pixel.

  After the conversion is complete and the DCRed value for each pixel is latched, the latched value can be read as described above. As shown in FIG. 6, before the correlation and navigation functions, a scanning clock signal (which may function as a readout signal) can be sent to read one column from each row simultaneously.

  By performing DCR image processing in the analog domain and integrating it into the pixel array, interference of digital signals into the analog and photosensitive regions of the array can be reduced.

  In the embodiments described above, each pixel (or at least each non-edge pixel) compares its output with the output of the nearest neighbor pixel. However, another embodiment involves comparing the output of one pixel with the output from a neighboring pixel that is not adjacent (ie not closest). As an example, FIG. 7 shows an array 100 'and a subarray 101'. Formula (1) can be modified as follows.

Or this formula (2) can also be written as follows.

The pixels in the array implementing equation (2) may include additional mirroring devices (such as PMOS devices 143-151 of FIG. 4) when summing more than eight adjacent pixel output signals. This is not always necessary. Of course, if α _i = 0 for a sufficient number of terms in equation (2), no additional mirroring device should be needed. In another embodiment, as shown below in equation (3), equation (2) could be further modified to include subarrays with other sizes.

However, n is the number of adjacent pixels to be considered.

  In another embodiment, one or more pixels can be configured to output image data greater than one bit during an image cycle. FIG. 8 is a schematic diagram of a pixel of such an embodiment. Integration circuit 112 ', comparison current generator circuit 114' and current addition node 110 'are similar to integration circuit 112, comparison current generator circuit 114 and current addition node 110 described with respect to FIG. Accordingly, there is no need to further describe the details and operation of blocks 110 ', 112' and 114 '. However, the comparator 116 'of FIG. 8 is modified to include a plurality of devices 154X and 154Y at node B' and a plurality of devices 156X and 156Y at node C '. Devices 154X and 154Y are of different sizes, but devices 154X and 156X are aligned. Devices 154Y and 156Y are also aligned. The current through device 154X is regulated by device 162. Similarly, the current through devices 154Y, 156X and 156Y is also regulated by devices 161, 163 and 164, respectively. The processor 180 (which may be local, global, or otherwise provide control signals to multiple pixels) controls the devices 161 and 164 with the SELP and SELN signals. Similarly, processor 180 provides a STROBE signal and receives a CLK (clock) signal and a BIT SELECT (bit select) signal.

In general, the reset and integration phases of the image cycle of the pixel of FIG. 8 should be similar to those described above with respect to FIGS. As in the previously described embodiment, the input to node B ′ is eight times the current (I _8x ) from device 147 ′ and the input to comparator node C ′ is the adjacent pixel. _Is the sum of the comparison currents from (I _Σ ). However, unlike the previous embodiment, the input to the comparator 116 'is compared several times during the conversion phase of the image cycle. In the first comparison, the SELP signal is high and device 164 is turned on. In this state, current can flow from node C ′ through devices 156X and 156Y and from node B ′ through device 154X. If the devices 156X and 156Y are sized such that the total size of the devices 156X and 156Y is larger than the size of the device 154X, the comparator 116 'will be skewed towards the node B'. In other words, I _Σ needs to be larger for the comparator output to go high. After the STROBE signal goes low, the output of comparator 116 ′ is latched by latch 118 ′ and then possibly stored in memory 182 (as described below). Memory 182 is outside the pixel. Again, the STROBE signal is brought high to bring the comparator 116 'into a balanced state and the SELN and SELP signals are brought low. In this state, current can flow from node C ′ through device 156X and from node B ′ through device 154X. Since these devices are in equilibrium, the output of comparator 116 'will be high when I _Σ is greater than or equal to I _8x . Again, the STROBE signal is pulled low, thereby latching the output of comparator 116 ′, and the latched value is (possibly) stored in memory 182. The STROBE signal is then brought high, the comparator is again balanced, and the SELN signal is brought high. In this state, current can flow from node C ′ through device 156X and from node B ′ through devices 154X and 154Y. In this state, comparator 116 'is skewed toward node C'. In other words, to make the comparator output high, _IΣ needs to be smaller. Again, the STROBE signal is pulled low, thereby latching the output of comparator 116 ′, and the latched value is (possibly) stored in memory 182.

FIG. 9 is a graph for further explaining the operation of the comparator 116 ′. The horizontal axis represents the input (I _Σ ) to the node C ′, and the vertical axis represents the input (I _8X ) to the node B ′. I _i , I _ii, and I _iii represent any current intensity that satisfies | I _iii |> | I _ii |> | I _i |. Line 1 corresponds to a state where the SELP signal is high (devices 154X, 156X and 156Y are on). For combinations of I _Σ and I _8X values in the region above line 1, the output of comparator 116 'is low. For combinations of I _Σ and I _8X values on or below line 1, the output of comparator 116 'is high. Line 2 corresponds to a state where SELP and SELN are low (devices 154X and 156X are on). When comparator 116 ′ is in this state, the combination of the I _Σ and I _8X values in the region above line 2 provides a low comparator output, and I _{Σ in} the region above or below line 2. And the combination of the I _8X values provides a high comparator output. Line 3 corresponds to a state where the SELN signal is high (devices 154X, 154Y and 156X are on). When comparator 116 ′ is in this state, the combination of the values of I _Σ and I _{8X in} the region above line 3 provides a low comparator output, and I _{Σ in} the region above or below line 3. And the combination of the I _8X values provides a high comparator output. Thus, in this configuration, the comparator 116 'is, I _sigma is how much greater than I _8X, or I _8X provides an output indicating more detail greater how much than I _sigma. Referring again to FIG. 9, the pixel can provide an output that can be decoded to show where I _Σ and I _8X are in the four regions of (a, b, c or d). .

The processor 180 and the memory 182 convert the output of the comparator 116 ′ into a 2-bit value. During the first part of the conversion phase (STROBE goes low and SELP is high), a high comparator output (indicating that I _Σ and I _8X are in region a) is “11” in the external memory 182. Is stored. Since the low output matches that I _Σ or I _8X is in the regions b, c and d, no value is stored for the low output during this first part. During the second part of the conversion phase (STROBE goes low and SELN and SELP are low), the high comparator output indicates that the values of I _Σ and I _8X are in region b and stores in memory 182 Stored as “10”. Since the low output matches that I _Σ and I _8X are in region c or d, no value is stored for the low output during this second portion. During the third part of the conversion phase (STROBE goes low and SELN is high), the high comparator output is stored as “01” in the external memory 182 and the low comparator output is stored as “00”. Is done. Additional bit values can be obtained with additional devices similar to 154Y and 156Y and additional select outputs from 180.

  The pixel array according to the invention can be used for motion detection, more specifically as part of a computer input device or position pointing device. Such devices include computer mice, trackballs, and other devices that measure movement. FIG. 10 shows a possible example in which the photosensor pixel array according to the present invention is mounted on a computer mouse. FIG. 10 is an “exploded” perspective view showing some major components of a typical mouse 250. The mouse 250 includes an upper case 251, a set of keys 252, a circuit board 253, and a lower case 254. Other components of the mouse 250 are not shown, but include a power source (in the case of a battery powered mouse), a cable for connection to a computer (if not a wireless device), a scroll wheel and other mechanical components and various It should be possible to include circuit components. These other components are well known in the art. As is well known in the art, a user operates mouse 250 by moving mouse 250 over a desk or other surface. The lower surface of the lower case 254 is in contact with a desk or other surface and is transparent or includes a transparent portion 255. A lens or other focusing element (not shown) could be placed between the transparent portion 255 and the circuit board 253, or could be incorporated into the transparent portion 255. An image chip 260 (outlined in FIG. 10) and an LED 262 (also outlined in FIG. 10) are placed on the lower surface of the circuit board 253. In operation, light from the LED 262 is reflected from a desk or other surface, illuminates the interior through the transparent portion 255 (and the focusing element, if present), and the array 100 disposed on the chip 260 Receive. The array 100 could be incorporated into the image chip 260 as shown in FIG. 11 which is a partial view of the lower surface of the circuit board 253.

  While specific examples of implementing the invention have been described, there are many variations and substitutions of the systems and techniques described above that fall within the spirit and scope of the invention as set forth in the appended claims. Those skilled in the art will understand. However, as an example, the initial current generator, the comparison current generator and the comparator (and other parts of the described embodiment) could be formed from alternative circuit configurations. A pixel array according to the present invention could include a photosensor that responds to illumination outside the visible light wavelength. In addition to the configuration in which one or more non-adjacent neighboring pixels are connected to a given pixel, the present invention also includes a configuration in which not all adjacent (or nearest neighbor) pixels are connected to a given pixel. .

  The pixel array of the present invention could be implemented in other applications. One example includes motion detection for alarms. Another example includes incorporating a pixel array into an electronic “ruler” or “measurement” used to measure distance. Another possible example includes using a pixel array as part of a paper motion detector in a printer. Such other modifications are within the scope of the present invention as defined in the appended claims.

It is a block diagram which shows the existing photosensor structure used for a motion detection. It is a block diagram which shows the pixel array by one Embodiment of this invention. FIG. 3 is a block diagram showing a part of the pixel array in FIG. 2. It is the schematic which shows the pixel of FIG. It is a block diagram which shows the serial data reading in one Embodiment of this invention. It is a timing diagram which shows operation | movement of embodiment of this invention. It is a block diagram which shows the pixel array by the 2nd Embodiment of this invention. It is the schematic which shows the pixel by the 3rd Embodiment of this invention. It is a graph explaining operation | movement of the pixel of FIG. It is a figure which shows one Embodiment which mounted the pixel array by this invention in the computer mouse. It is a figure which shows one Embodiment which mounted the pixel array by this invention in the computer mouse.

Explanation of symbols

10 Photosensor 12, 14, 18 NMOS transistor 16 Node 20 Storage capacitor 100 Array 100 ₀ Pixel 100 _{1 to} 100 ₈ Pixel 100 'Array 101, 101' Subarray 110, 110 'Current summing node 112, 112' Integration circuit 114, 114 'Comparison current generator circuit 116, 116' Comparator circuit 118, 118 'Serial scan output latch 120, 120' Buffer 132, 134 PMOS device 136 Photodiode 138, 140 NMOS device 142 PMOS reference device 143-151 PMOS mirroring device 154 156 NMOS device 154X, 154Y, 156X, 156Y device 158, 158 'composite charge cancellation device 161-164 device 180 processor 1 82 Memory 250 Mouse 251 Upper case 252 Key 253 Circuit board 254 Lower case 255 Transparent part 260 Image chip 262 LED

Claims (13)

Used in computer input devices with LEDs,
Processor,
memory,
Photodiode,
An initial current generator that generates a current according to the light intensity;
A comparison current generator circuit for generating an internal comparison current and an external comparison current;
A current summing node that sums the current from outside,
A comparator circuit that compares whether two currents are larger or smaller than a predetermined ratio with respect to the other current, and is configured to change the ratio of the comparison. A method for indicating a relative difference in received illumination in a photosensor array comprising a plurality of pixels comprising a comparator circuit and a latch, comprising:
A first step in which the LED illuminates a surface;
When the light from the LED is reflected on the surface, the photodiode receives the illumination reflected on the surface, and the initial current generator generates a current corresponding to the light intensity received by the photodiode. A second step;
A third step in which the comparison current generator circuit generates a plurality of external comparison currents and at least one internal comparison current with reference to the current generated by the initial current generator;
A fourth step of receiving the external comparison currents of comparison current generator circuit or these pixels adjacent to the pixel the current summing node,
A fifth step in which the current summing node sums the received external comparison current;
A sixth step in which the comparator circuit compares the external comparison current summed by the current summing node with the internal comparison current;
The internal comparison current, if with respect to the current summing node summed external comparison current by greater than a predetermined proportion of the comparison, providing an output for the first value in the latch, the previous SL internal comparison current A seventh step of providing the latch with an output for a second value if not greater than a predetermined comparison ratio for the external comparison current summed by the current summing node ;
Wherein the processor, when the output provided by said latch is the second value, and converts the provided output by the latch to the 2-bit value, is stored the converted 2-bit value in the memory or, if the output provided by said latch is a first value, changes the ratio of the comparison of the comparator circuit, and the comparator circuit in equilibrium, it is summed by the current summing node An eighth step of returning to the sixth step for causing the comparator circuit to compare the external comparison current and the internal comparison current;
A method characterized by comprising: At each of said pixels, said plurality of external comparison currents to current generated by the initial current generator, has the same gain or attenuation, wherein at least one internal comparison current, the initial current generation 2. A method according to claim 1, characterized in that the current generated by the generator has the same gain or attenuation . At each of said pixels, said at least one internal comparison current to current generated by the initial current generator, characterized in that it has a multiple of the number of the received external comparison current as a gain The method according to claim 1. The method of claim 1, further comprising the step of the initial current generator interrupting generation of the initial current when the initial current is not required. The method of claim 1, wherein the sixth and seventh steps are not performed at an outer edge of the photosensor array. The method of claim 1, wherein the fourth step includes the current summing node receiving an external comparison current from a comparison current generator circuit of at least one pixel that is not adjacent to the pixel. . A computer input device that generates movement of a cursor on a computer display in response to movement of the computer input device,
LED,
A photosensor array comprising a plurality of pixels ;
Each of the pixels comprises:
Memory,
When the light from the LED is reflected on the surface, a photodiode that receives the illumination reflected on the surface;
An initial current generator for generating a current according to the intensity of light received by the photodiode;
A comparison current generator circuit for generating a plurality of external comparison currents and at least one internal comparison current based on the current generated by the initial current generator;
It receives external comparison currents from comparison current generator circuit of the pixel adjacent to the pixel, a current summing node for summing said received external comparison current,
For the external comparison current summed by the current summing node and the internal comparison current , the internal comparison current is greater than or less than a predetermined comparison ratio with respect to the external comparison current summed by the current summing node. a comparator circuit for comparing either a comparator circuit configured to capable of changing the ratio of the comparison,
If the external comparison currents the internal comparison current is summed by the current summing node greater than the proportion of the predetermined comparison, a first value is latched, pre SL internal comparison current are summed by the current summing node A latch for latching the second value when the external comparison current is not greater than a predetermined comparison ratio ;
If the latched value by said latch is the second value, and converts the latched value by the latch on the 2-bit value, is stored the converted 2-bit value in the memory, or the If the latched value by the latch is a first value, it changes the ratio of the comparison of the comparator circuit, and the comparator circuit in equilibrium, an external comparison summed by the current summing node a processor for comparing the internal comparison current to the comparator circuit,
A computer input device comprising: For each of the pixels, the plurality of external comparison currents, the relative initial current current generated by the generator, have the same gain or attenuation, wherein at least one internal comparison current, the initial current 8. Computer input device according to claim 7, characterized in that the current generated by the generator has the same gain or attenuation . Each of said pixels are arranged in the photosensor array of m rows and n columns, those the photosensor array, and a plurality of latches in a column are read simultaneously, according to claim 7 computer Input device. The initial current, the even I Oh photosensor array is operational, characterized in that it is not continuously generated, a computer input device according to claim 7. The pixel is characterized in that, at the outer edge of the photosensor array, each of the pixels does not compare the external comparison current summed by the current summing node with the internal comparison current. 8. The computer input device according to 7.   The computer input device of claim 7, wherein the photosensor array is part of a single integrated circuit. 8. The computer input device of claim 7, wherein in each of the pixels , the initial current generator comprises an NMOS device.

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