JP4550100B2 - Photomask making method and semiconductor device manufacturing method - Google Patents

Description

The present invention relates to a photomask manufacturing method and a semiconductor device manufacturing method .

  In manufacturing a semiconductor device, an ion implantation technique is generally used. In the ion implantation technique, a photoresist is formed as a mask in order to selectively implant ions into a substrate to be implanted.

  The photoresist functions as a mask both when an insulating film and a conductive film are selectively formed on the substrate and when impurities are thermally diffused selectively on the substrate surface. Of course, it also functions as a mask when impurities are selectively ion-implanted into the substrate surface.

  Among these, there are the following problems when a photoresist is used as a mask for ion implantation.

  First, as a first problem, there is a problem that it is difficult to remove the photoresist, particularly when high-concentration impurities are ion-implanted. When ion implantation is performed, ions also enter the mask photoresist. Then, since the photoresist is cured, it may be difficult to remove the photoresist. As a result, a resist residue may be generated, resulting in a decrease in product yield.

  In order to remove the photoresist without residue, it is conceivable to enhance plasma ashing or perform wet etching in an excessive manner. However, when ashing is strengthened, charging damage to the substrate increases, which may reduce the reliability of the product. Also, if excessive wet etching or ultrasonic cleaning is performed, a fine circuit pattern such as a gate electrode may fall over or be removed. Therefore, it is not desirable to employ enhanced ashing or excessive wet etching.

  That is, there is a problem that the resist removal property is improved by reducing the area where the photoresist is cured in order to facilitate the removal of the photoresist.

  The second problem is the problem of the dimensional accuracy of the photoresist. As the circuit pattern becomes finer, the dimensional accuracy of the photoresist required for the implantation process is becoming stricter.

  For example, conventionally, when ion implantation is performed in the source / drain region of a MOS (Metal Oxide Semiconductor) transistor, a wide element isolation layer has been formed around the source / drain region. / It should have been provided sufficiently larger than the drain region. However, as the elements and circuit patterns become finer, another element may be arranged immediately adjacent to the MOS transistor, and ions for forming source / drain regions should not be implanted into the other element. There must be. Therefore, it is necessary to improve the dimensional accuracy of the opening.

  However, when the opening of the photoresist is dense depending on the location, the shape of the opening is easily deformed. This will be described with reference to FIGS. 22 and 23. FIG.

  FIG. 22 is a view showing a wafer WF on which product chips such as CP1 to CP4 are formed, and FIG. 23 is an enlarged view showing a boundary region R between the product chips CP1 to CP4. In the product chip CP1 in FIG. 23, there is an empty area AR1 in which elements and circuits are not formed on the right side of the area where the N channel MOS transistors N1, N2 and the P channel MOS transistors P1, P2 are formed. Similarly, other product chips CP2 to CP4 have empty areas AR2 to AR4 in which elements and circuits are not formed.

  In such an empty area AR1, no element and circuit are formed, and therefore no photoresist opening is provided. That is, the opening of the photoresist is dense in the region where the N-channel MOS transistor N1 and the like are provided, whereas the opening is sparse in the empty region AR1.

  In general, in a photoresist, surface tension is likely to be generated in a portion having a large area. Therefore, when the empty area AR1 in which elements and circuits are not formed is wide, the photoresist on the area where the N-channel MOS transistor N1 and the like are provided is pulled by the photoresist on the empty area AR1 side. As a result, the shape of the opening provided for element formation is distorted toward the empty area AR1, and the dimensional accuracy of the opening tends to deteriorate.

  In order to improve the dimensional accuracy of the photoresist, thinning is effective. This is because if the thickness of the photoresist is large, the surface side is strongly pulled toward the vacant area AR1, and the amount of distortion of the shape of the opening increases, but if the film is made thin, the amount of distortion can be reduced.

  However, when the film thickness is reduced, there is a possibility that the role of the mask in the ion implantation cannot be sufficiently fulfilled. This is because ions penetrate through the thin photoresist and are implanted outside the desired region.

  That is, there has been a problem that it is desired to improve the dimensional accuracy of the photoresist without reducing the film thickness.

  Further, as a third problem, when the performance of the electron neutralizer that neutralizes the charge of ions entering the substrate is reduced, ions are trapped in the photoresist to cause charge-up, and a nearby gate insulating film In addition, there is a problem of causing electrostatic breakdown in the capacitor dielectric film.

  When the gate insulating film or the capacitor dielectric film causes electrostatic breakdown, the normal operation cannot be performed due to defective withstand voltage, resulting in a defective chip. Even if electrostatic breakdown does not occur, damage may remain on the gate insulating film and part of the capacitor dielectric film. If damage occurs even in a part in this way, a leak current is generated even if it operates, resulting in a defective chip.

  That is, there is a problem that it is desired to prevent the photoresist from being charged up.

Therefore, the object of the present invention is to improve the resist removability by reducing the area where the photoresist is hardened during ion implantation, improve the dimensional accuracy, and prevent the photoresist from being charged up. A method for producing a photomask necessary for manufacturing a semiconductor device in which the danger of a short circuit due to a dummy region between elements and circuits or wells is avoided , and a method for producing a semiconductor device using the photomask producing method are provided. It is in.

One implementation status of the present invention, first a first step of preparing a first pattern in which a plurality of first dummy area is regularly arranged, the pattern of elements and circuits pattern or well described a second step of preparing a second pattern, the second superimposing first and a second pattern, said first dummy portion overlapping the boundary portions of the pattern of the elements and the circuit overlaps with the pattern portion or the well by erasing the area, a third step of determining the placement of the first dummy region and the first dummy area in which the placement has been determined, and a pattern of patterns or the well of the device and circuit and a fourth step of creating a transcribed photomask, in the third step, the position where the first dummy area is cleared, the size of the first dummy area It becomes the second dummy region, which is the element and the circuit pattern or the well of a pattern boundary portions additionally provided to that photomask creation method so as not to overlap in the for.
Another embodiment of the present invention provides a first step of preparing a first pattern in which a plurality of first dummy regions are regularly arranged and a second pattern in which a circuit pattern is described, A second step of determining the arrangement of the first dummy area by superimposing the first and second patterns and erasing the first dummy area in a portion overlapping the circuit pattern; and A third step of creating a photomask that transfers the determined first dummy region and the circuit pattern, and in the second step, at the position where the first dummy region is erased, This is a photomask forming method in which a second dummy area having a size different from that of the first dummy area is newly arranged so as not to overlap the circuit pattern.
Another embodiment of the present invention provides a first step of preparing a first pattern in which a plurality of first dummy regions are regularly arranged and a second pattern in which a circuit pattern is described, By overlapping the first and second patterns and erasing the first dummy area that overlaps the circuit pattern, the first arrangement that is the arrangement of the first dummy area is determined, By arranging a second dummy area having a size different from that of the first dummy area at a position where one dummy area has been erased so as not to overlap the circuit pattern, the second dummy area A second step of determining a second arrangement which is an arrangement of the first arrangement, the first dummy area arranged in the first arrangement, the second dummy area arranged in the second arrangement, and the circuit A photomask with a pattern transferred A photomask generation method and a third step of forming.
Another embodiment of the present invention provides a first step of preparing a first pattern in which a plurality of first dummy regions are regularly arranged and a second pattern in which a circuit pattern is described, By overlapping the first and second patterns and erasing the first dummy area that overlaps the circuit pattern, the first arrangement that is the arrangement of the first dummy area is determined, A second dummy area having a different size from the one dummy area is disposed at a position where the first dummy area is erased and between the circuit pattern and the first dummy area. In the second step of determining the second arrangement that is the arrangement of the second dummy area, the first dummy area arranged in the first arrangement, and the second arrangement arranged in the second arrangement Transfer the dummy area and the circuit pattern And a photomask generation method and a third step of creating a photomask.
Another embodiment of the present invention is a method of manufacturing a semiconductor device comprising a step of forming a photoresist using a photomask, wherein the photomask has a plurality of first dummy regions arranged regularly. A first step of preparing a first pattern, a second step of preparing a second pattern in which an element and circuit pattern or a well pattern is described, and the first and second patterns are superimposed, A third step of determining an arrangement of the first dummy region by erasing the first dummy region in a portion overlapping with an element and circuit pattern or a portion overlapping a boundary of the well pattern; A fourth step of creating a photomask in which the first dummy region whose arrangement has been determined and the pattern of the element and circuit or the pattern of the well are transferred A second dummy region having a size different from that of the first dummy region at the position where the first dummy region is erased in the third step, the element and circuit pattern or the well This is a method for manufacturing a semiconductor device, which is created by a photomask creation method that is newly arranged so as not to overlap the boundary portion of the pattern.
Another embodiment of the present invention is a method of manufacturing a semiconductor device comprising a step of forming a photoresist using a photomask, wherein the photomask has a plurality of first dummy regions regularly arranged. A first step of preparing a first pattern and a second pattern on which a circuit pattern is described, and the first and second patterns are overlapped to overlap the first pattern of the first pattern. By erasing the dummy area, a second step of determining the arrangement of the first dummy area, and creating a photomask that transfers the first dummy area for which the arrangement has been determined and the circuit pattern A second dummy area having a size different from that of the first dummy area at a position where the first dummy area is erased in the second process. Created by the photomask to create a method of newly arranged so as not to overlap in emission, a method of manufacturing a semiconductor device.
Another embodiment of the present invention is a method of manufacturing a semiconductor device comprising a step of forming a photoresist using a photomask, wherein the photomask has a plurality of first dummy regions regularly arranged. A first step of preparing a first pattern and a second pattern on which a circuit pattern is described, and the first and second patterns are overlapped to overlap the first pattern of the first pattern. By erasing the dummy area, the first arrangement which is the arrangement of the first dummy area is determined, and the first dummy area is different in size from the position where the first dummy area is erased. Arranging the second dummy area so as not to overlap the circuit pattern, the second step of determining the second arrangement, which is the arrangement of the second dummy area, and the first arrangement are arranged in the first arrangement The first A semiconductor device produced by a photomask producing method comprising: a third step of producing a photomask having transferred a me region, the second dummy region arranged in the second arrangement, and the circuit pattern. It is a manufacturing method.
Another embodiment of the present invention is a method of manufacturing a semiconductor device comprising a step of forming a photoresist using a photomask, wherein the photomask has a plurality of first dummy regions regularly arranged. A first step of preparing a first pattern and a second pattern on which a circuit pattern is described, and the first and second patterns are overlapped to overlap the first pattern of the first pattern. The first dummy area is determined by erasing the dummy area, and a second dummy area having a size different from that of the first dummy area is determined as the first dummy area. Is a deleted position, and is arranged between the circuit pattern and the first dummy area, thereby determining a second arrangement which is an arrangement of the second dummy area; and Normal in the first arrangement A photomask producing method comprising: a third step of producing a photomask in which the first dummy region, the second dummy region arranged in the second arrangement, and the circuit pattern are transferred. This is a method for manufacturing a semiconductor device.

In one embodiment of the present invention, since the elimination of the first dummy area of the portion overlapping with the boundary portion of the pattern portion or well overlapping the element and the circuit pattern, between the elements and circuits or well, first The danger of a short circuit due to the dummy area is avoided. Then, a photomask is created by transferring the first dummy region whose arrangement has been determined and the pattern of the element and circuit or the well pattern, so that the photomask used for the method of manufacturing a semiconductor device can be created using this photomask. A resist can be formed.
Further, the second dummy region having a size different from that of the first dummy region is not overlapped with the boundary portion of the element and circuit pattern or the well pattern at the position where the first dummy region is erased. Since it is newly arranged, the opening area of the photoresist used in the semiconductor device manufacturing method can be adjusted more finely.

In another embodiment of the present invention, not only the first dummy region overlapping the element and circuit pattern or the portion overlapping the boundary of the well pattern, but also the first dummy region existing in the periphery thereof is provided. Since erasing is performed, the danger of a short circuit or the like due to the first dummy region between the element and the circuit or well is further avoided.

In another embodiment of the present invention, the danger of a short circuit due to the first dummy region is avoided. Further, the opening area of the photoresist used in the semiconductor device manufacturing method can be adjusted more finely.
In another embodiment of the present invention, a highly reliable semiconductor device can be manufactured.

<Embodiment 1>
The present embodiment is a method of manufacturing a semiconductor device in which ion implantation is performed through a photoresist having a dummy pattern opened in an empty area other than the element and circuit patterns in one chip.

  1-6 is a figure which shows each process of the manufacturing method of the semiconductor device which concerns on this Embodiment. 2 to 6 are cross-sectional views taken along the cutting line VI-VI in FIG. 1, and are diagrams showing steps for forming a well and a MOS transistor in the semiconductor substrate 1. FIG. 1 is a top view of the state of FIG. 6 in which the photoresist PR4 has been formed.

  The structure of FIG. 1 corresponds to the structure of FIG. 23 shown as the prior art, and elements having the same functions as those of the structure of FIG. 23 are denoted by the same reference numerals. As shown in FIGS. 1 and 6, in this embodiment, in addition to the structure of FIG. 23, dummy areas DM1 and DM2 are provided in the empty area AR1 of the chip CP1. The same applies to the other chips CP2 to CP4, and dummy areas are provided in the empty areas AR2 to AR4.

  In addition, the ion implantation photoresist PR4 is provided with the opening OP2 of the element and circuit pattern, and in addition, an ion implantation dummy pattern is provided as the opening OP1 on the dummy regions DM1 and DM2. (In FIG. 1, the openings OP1 and OP2 of the photoresist PR4 are indicated by broken lines).

  A process for forming a well, a MOS transistor, and a dummy region in the semiconductor substrate 1 will be described with reference to FIGS.

  First, the element isolation region 2 is formed on the surface of the semiconductor substrate 1 by a LOCOS (Local Oxidation of Silicon) method or the like. Then, after forming the photoresist PR1 on the surface of the semiconductor substrate 1, the N-channel transistor N1 formation region and the dummy region DM1 are patterned so as to be opened, and the patterned photoresist PR1 is used as a mask to form a P-type impurity. Ion implantation IP1 is performed. As a result, a P-type well 1a is formed in the formation region of the N-channel transistor N1 (FIG. 2).

  Since the dummy region DM1 is an empty region where elements and circuits are not originally formed, the P-type well 1a is unnecessary, but a dummy pattern is opened to increase the opening of the photoresist PR1. Yes. The advantage of increasing the opening will be described later.

  Next, the photoresist PR1 is removed, the photoresist PR2 is formed on the surface of the semiconductor substrate 1, and is patterned so that the formation region of the P-channel transistor P1 and the dummy region DM1 are opened. Then, N-type impurity ion implantation IP2 is performed using the patterned photoresist PR2 as a mask. As a result, an N-type well 1b is formed in the formation region of the P-channel transistor P1 (FIG. 3). Again, a dummy pattern is opened to increase the opening of the photoresist PR2 in the dummy region DM1. Thereby, both the P-type impurity and the N-type impurity are ion-implanted into the well 1c formed in the dummy region DM1.

  Next, the photoresist PR2 is removed, and an insulating material and a conductive material are stacked on the entire surface of the semiconductor substrate 1. Then, both are patterned using a photolithography technique and an etching technique, and gate electrodes 3a and 3b and gate insulating films 4a and 4b are formed in the formation region of the N-channel transistor N1 and the formation region of the P-channel transistor P1, respectively. FIG. 4). In dummy region DM1, dummy gate electrode 3c and gate insulating film 4c are formed on the entire surface of dummy region DM1.

  Next, a photoresist PR3 is formed on the surface of the semiconductor substrate 1, and is patterned so that the formation region of the N-channel transistor N1 and the dummy region DM1 are opened. Then, N-type impurity ion implantation IP3 is performed using the patterned photoresist PR3 as a mask. As a result, the source / drain region 5a is formed in the formation region of the N-channel transistor N1 (FIG. 5). Again, a dummy pattern is opened in order to increase the opening of the photoresist PR3 in the dummy region DM1. Thereby, N-type impurities are ion-implanted into the dummy gate electrode 3c formed in the dummy region DM1.

  Next, the photoresist PR3 is removed, a photoresist PR4 is formed on the surface of the semiconductor substrate 1, and this is patterned so that the formation region of the P-channel transistor P1 and the dummy region DM1 are opened. Then, ion implantation IP4 of P-type impurities is performed using the patterned photoresist PR4 as a mask. As a result, the source / drain region 5b is formed in the formation region of the P-channel transistor P1 (FIG. 6). Again, a dummy pattern is opened in order to increase the opening of the photoresist PR4 in the dummy region DM1. As a result, P-type impurities are also ion-implanted into the dummy gate electrode 3c formed in the dummy region DM1.

  Now, an advantage of providing a dummy pattern in the photoresists PR1 to PR4 to increase the number of openings will be described.

  When the dummy patterns are opened in the photoresists PR1 to PR4 for ion implantation, the area of the non-opening portion of the photoresist is reduced, and the number of ions entering the photoresist can be reduced. As a result, it is possible to improve the removal property of the photoresist by reducing the area where the photoresist is hardened due to ion penetration.

  At this time, of course, ions that have not entered the photoresist are implanted into the semiconductor substrate 1, but since they are dummy regions, the implantation does not affect the operation of the semiconductor device. This is because the dummy region is selected at such a location that does not affect the operation of the semiconductor device. For example, if the P-channel transistor P1 and the dummy region DM1 are separated by about 1 μm, the dummy region DM1 does not affect the operation of the P-channel transistor P1. Note that the size of the dummy region DM1 may be set to about 1 to several μm, for example.

  Furthermore, since the number of ions that enter the photoresist can be reduced, the possibility of charge-up can also be reduced. Therefore, it is difficult to cause electrostatic breakdown or damage to the nearby gate insulating film or capacitor dielectric film.

  In addition, since the area of the non-opening portion of the photoresist is reduced, it is difficult for a portion where the surface tension is strongly generated to exist. As a result, it is possible to improve the dimensional accuracy of the photoresist without reducing the thickness.

  Therefore, by using the semiconductor device manufacturing method according to this embodiment, a highly reliable semiconductor device can be manufactured.

  As shown in FIGS. 5 and 6, a conductive material such as a dummy gate electrode 3c that is in contact with the end of the dummy pattern is formed on the surface of the semiconductor substrate 1 exposed in the opening of the dummy pattern. For example, ions IN or IP that have entered the photoresist during ion implantation are likely to escape to the semiconductor substrate 1 through the conductive material. As a result, the removability of the photoresist can be further improved, and the possibility of charge-up can be further reduced.

  Further, as shown in FIGS. 7 and 8 (FIG. 8 is a cross-sectional view taken along section line VIII-VIII in FIG. 7), for example, a dummy pattern of photoresist PR5 is provided even when a dummy region DM3 having a MOS transistor structure is provided. If the end of the opening OP3 is in contact with the dummy gate electrode 3d, the ions IP that have entered the photoresist during ion implantation are likely to escape to the semiconductor substrate 1 through the dummy gate electrode 3d. Even if the end of the opening OP3 is in contact with the dummy active region 5d, the ions IP that have entered the photoresist during the ion implantation easily escape to the semiconductor substrate 1 through the active region 5d. Therefore, also in these cases, the removability of the photoresist can be further improved, and the possibility of charge-up can be further reduced.

  The dummy gate insulating films 4c and 4d can be made as thin as the gate insulating films 4a and 4c of the N-channel MOS transistor N1 and the P-channel MOS transistor P1 functioning as a semiconductor device. That's fine. This is because a thin gate insulating film makes it easier for ions entering the photoresist to escape to the semiconductor substrate 1.

  Further, the ratio of the total opening area of the dummy patterns in the photoresist to the total area of one chip is adjusted according to the size of the opening area of the pattern of the element to be formed and the circuit. For example, when the opening areas of the element and circuit patterns are small, the sum of the opening areas of the dummy patterns takes a large value, and vice versa.

  The ratio of the total opening area of the dummy pattern to the entire area of one chip is set to fall within a range of 30 to 70%, for example. As described above, by adjusting the area of the opening of the photoresist, it is possible to optimize each effect of improving the removal property of the photoresist, improving the dimensional accuracy, and preventing the charge-up.

  Note that the manufacturing method of the semiconductor device according to the present embodiment can be applied to various ion implantation processes. Specifically, for example, implantation during well formation, implantation into a channel region for threshold control, implantation into a gate electrode and a source / drain active region of a MOS transistor (including the purpose of forming a MOS capacitor), LDD (Lightly Doped Drain) The present invention can be applied to various ion implantation scenes such as implantation for forming a region and implantation performed on a hole bottom after forming a contact hole.

  Note that the last "injection performed on the bottom of the hole after forming the contact hole" is that the opening OP4 is provided as a contact hole as shown in FIG. This is a remedy for the case where the recess 2b is formed in the contact hole due to etching. That is, ion implantation is performed on the exposed semiconductor substrate 1 portion so that the semiconductor substrate 1 exposed in the recess 2b and the source / drain region 5b are not electrically connected by the contact plug, thereby expanding the source / drain region. 5c is formed.

  In such a case as well, ion implantation may be performed by providing a dummy pattern in the photoresist in the dummy region.

<Embodiment 2>
The present embodiment is a modification of the method for manufacturing the semiconductor device according to the first embodiment, and the opening of the dummy pattern is provided on the wafer dicing line or in the vicinity thereof.

  As shown in FIGS. 10 and 11 (FIG. 11 is a cross-sectional view taken along section line XI-XI in FIG. 10), in this embodiment, the opening OP5 of the dummy pattern of the photoresist PR7 is on the dicing line DS. It is provided along. Therefore, the photoresist PR7 can be separated for each chip.

  In this case, even if ions are excessively implanted into the photoresist PR7 in the chip CP1 portion and the photoresist is hardened or charged up, the influence remains in the chip CP1. That is, the deterioration phenomenon due to ion implantation does not spread to the other chips CP2 to CP4. Therefore, a method for manufacturing a semiconductor device with a high yield is obtained.

  As shown in FIGS. 12 and 13 (FIG. 13 is a cross-sectional view taken along the cutting line XIII-XIII in FIG. 12), the opening OP6 of the dummy pattern of the photoresist PR8 is connected to the element isolation region 2 near the dicing line DS. You may provide along. Even if it does in this way, there exists an effect similar to the case of FIG. 10 and FIG.

  However, in the case of FIGS. 10 and 11, since the opening OP5 of the dummy pattern is provided along the dicing line DS, ions that have entered the photoresist PR7 during the ion implantation pass through the dicing line DS. As a result, it is easy to escape to the semiconductor substrate 1, which further improves the removability of the photoresist and further reduces the possibility of charge-up.

<Embodiment 3>
This embodiment is a method for producing a photomask used when forming a photoresist used in the method for manufacturing a semiconductor device according to the first and second embodiments. By producing a photomask as follows, a photoresist provided with the dummy pattern shown in Embodiments 1 and 2 can be formed on a semiconductor substrate.

  FIG. 14 is a flowchart showing a photomask creation method according to this embodiment. First, as shown in FIG. 15, a plurality of dummy areas DM4 are regularly arranged to create a dummy pattern (step ST1). Here, as an example of regular arrangement, a case of arranging in an array is shown.

  Next, as shown in FIG. 16, a circuit pattern in which the MOS transistor element P3, the active region N3 constituting part of the circuit, the well 1c, and the element isolation film 2 are described is prepared, and the dummy circuit shown in FIG. The patterns are superimposed (FIG. 17, step ST2).

  Then, the MOS transistor element P3 and the active region N3 in the circuit pattern are oversized (the region is expanded) to create oversized portions OV2 and OV3, and the boundary portion of the well 1c is oversized to oversize portion. OV1 is created (FIG. 18, step ST3).

  Subsequently, the dummy area DM4 overlapping the oversize portions OV1 to OV3 is deleted (FIG. 19, step ST4). That is, in addition to the dummy area DM4 that overlaps the circuit pattern, the dummy area DM4 existing around the circuit pattern is also erased. Then, each photomask is created based on the circuit pattern obtained here (step ST5).

  For example, as shown in FIG. 20, the photomask M1 for forming the gate electrode portion in the MOS transistor element P3 transfers the gate electrode portion and the dummy region DM4 from the circuit pattern of FIG. Create and create. Note that the opening OP7 of the dummy region DM4 is formed to have a slightly larger area than the dummy region DM4 so that the formed dummy gate can run over the element isolation region 2.

  In addition, for example, as shown in FIG. 21, the photomask M2 for forming the source / drain active region in the MOS transistor element P3 transfers the active region portion and the dummy region DM4 from the circuit pattern of FIG. Parts OP7 and OP9 are provided and created. The reason why the opening OP7 in FIG. 21 is smaller than the opening OP7 in FIG. 20 is to make the dummy active region smaller than the dummy gate pattern.

  As described above, according to the photomask manufacturing method according to the present embodiment, the dummy region in the portion overlapping the element and the circuit or the boundary portion of the well is erased. The danger of such is avoided. Then, a photomask is created by transferring the determined dummy region and the element and circuit pattern or well pattern. Using this photomask, the method of manufacturing the semiconductor device according to the first and second embodiments A photoresist used in the above can be formed.

  In addition, since the dummy region overlapping the oversized portion is erased, the danger of a short circuit due to the dummy region between the element and the circuit or well is further avoided.

  In addition, you may provide the dummy area | region from which size differs like dummy area | region DM1, DM2 of FIG. In that case, for example, a dummy area smaller than the dummy area DM4 may be newly arranged at the position where the dummy area DM4 is erased in step ST4 so as not to overlap the circuit pattern. Then, the opening area of the photoresist can be adjusted more finely.

7 is a top view showing the method for manufacturing the semiconductor device according to the first embodiment. FIG. 8 is a cross-sectional view showing the method for manufacturing the semiconductor device according to the first embodiment. FIG. 8 is a cross-sectional view showing the method for manufacturing the semiconductor device according to the first embodiment. FIG. 8 is a cross-sectional view showing the method for manufacturing the semiconductor device according to the first embodiment. FIG. 8 is a cross-sectional view showing the method for manufacturing the semiconductor device according to the first embodiment. FIG. 8 is a cross-sectional view showing the method for manufacturing the semiconductor device according to the first embodiment. FIG. 7 is a top view showing the method for manufacturing the semiconductor device according to the first embodiment. FIG. 8 is a cross-sectional view showing the method for manufacturing the semiconductor device according to the first embodiment. FIG. It is sectional drawing which shows the scene which inject | pours with respect to the hole bottom after contact hole formation. FIG. 10 is a top view showing the method for manufacturing the semiconductor device according to the second embodiment. FIG. 10 is a cross-sectional view showing the method for manufacturing the semiconductor device according to the second embodiment. FIG. 10 is a top view showing the method for manufacturing the semiconductor device according to the second embodiment. FIG. 10 is a cross-sectional view showing the method for manufacturing the semiconductor device according to the second embodiment. 10 is a flowchart showing a photomask creation method according to the third embodiment. It is a figure which shows the photomask production method which concerns on Embodiment 3. FIG. It is a figure which shows the photomask production method which concerns on Embodiment 3. FIG. It is a figure which shows the photomask production method which concerns on Embodiment 3. FIG. It is a figure which shows the photomask production method which concerns on Embodiment 3. FIG. It is a figure which shows the photomask production method which concerns on Embodiment 3. FIG. It is a figure which shows the photomask obtained by the photomask production method concerning Embodiment 3. FIG. It is a figure which shows the photomask obtained by the photomask production method concerning Embodiment 3. FIG. It is a figure which shows the wafer in which the product chip | tip was formed in the surface. It is the figure which expanded and showed boundary region R of the product chip.

Explanation of symbols

  1 semiconductor substrate, 2 element isolation region, 3c, 3d dummy gate electrode, 4c, 4d dummy gate insulating film, 5d dummy active region, DS dicing line, PR1 to PR8 photoresist.

Claims (22)

A first step of preparing a first pattern in which a plurality of first dummy regions are regularly arranged;
A second step of preparing a second pattern in which element and circuit patterns or well patterns are described;
The first and second patterns are overlapped, and the first dummy region is erased by erasing a portion overlapping the element and circuit patterns or a portion overlapping a boundary of the well pattern . A third step of determining the placement of the dummy area;
A fourth step of creating a photomask in which the first dummy region whose arrangement has been determined and the pattern of the element and circuit or the pattern of the well are transferred ;
In the third step, a second dummy region having a size different from that of the first dummy region is provided at a position where the first dummy region is erased, in the pattern of the element and circuit or the pattern of the well. additionally provided to that photomask creation method so as not to overlap the portion of the boundary. The photomask making method according to claim 1,
In the third step, in addition to the first dummy area of the portion overlapping with the boundary portions of the pattern of the elements and the circuit pattern overlaps part or the wells of a pattern of the elements and circuit or around the well by erasing even the first dummy region existing around the portion of the pattern boundary of the photomask to create a method for determining the placement of the first dummy area. A first step of preparing a first pattern in which a plurality of first dummy regions are regularly arranged and a second pattern in which a circuit pattern is described;
A second step of determining the arrangement of the first dummy area by superimposing the first and second patterns and erasing the first dummy area in a portion overlapping the circuit pattern;
A third step of creating a photomask in which the first dummy region whose placement has been determined and the circuit pattern is transferred;
In the second step, a second dummy area having a size different from that of the first dummy area is newly disposed at the position where the first dummy area is erased so as not to overlap the circuit pattern. To create a photomask. The photomask making method according to claim 3,
In the second step, in addition to the first dummy area overlapping the circuit pattern, the first dummy area existing around the circuit pattern is also erased, thereby A photomask making method for determining the arrangement of dummy regions. The photomask making method according to claim 3,
In the first step, the second pattern further includes a pattern of an element or a well,
In the second step, the placement of the first dummy region is determined by further erasing the portion of the first dummy region that overlaps the portion of the element pattern or the portion of the well pattern boundary. ,
In the third step, the photomask is obtained by further transferring the pattern of the element or the well,
In the second step, the second dummy region is not overlapped with the circuit pattern at the position where the first dummy region is erased, and is further overlapped with a boundary portion of the element or the well pattern. A method for creating a photomask that is newly arranged so that it does not become. A first step of preparing a first pattern in which a plurality of first dummy regions are regularly arranged and a second pattern in which a circuit pattern is described;
Overlaying the first and second patterns, and erasing the first dummy area that overlaps the circuit pattern determines a first arrangement that is the arrangement of the first dummy area, By arranging a second dummy area having a size different from that of the first dummy area at a position where the first dummy area has been erased so as not to overlap the circuit pattern, the second dummy area is arranged. A second step of determining a second arrangement which is an arrangement of the areas;
A third step of creating a photomask that transfers the first dummy areas arranged in the first arrangement, the second dummy areas arranged in the second arrangement, and the circuit pattern; A photomask making method provided. The photomask making method according to claim 6,
In the second step, in addition to the first dummy area overlapping the circuit pattern, the first dummy area existing around the circuit pattern is also erased, thereby A photomask creating method for determining the first arrangement of dummy areas. The photomask making method according to claim 6,
In the first step, the second pattern further includes a pattern of an element or a well,
In the second step, the first arrangement is determined by further erasing the first dummy region in a portion overlapping with the element pattern or in a portion overlapping the boundary of the well pattern, By disposing the second dummy region at a position where the dummy region is erased, not overlapping the circuit pattern, and further not overlapping the element pattern or the boundary of the well pattern, Determining the second arrangement;
In the third step, the photomask is produced by further transferring the pattern of the element or the well. A first step of preparing a first pattern in which a plurality of first dummy regions are regularly arranged and a second pattern in which a circuit pattern is described;
Overlaying the first and second patterns, and erasing the first dummy area that overlaps the circuit pattern determines a first arrangement that is the arrangement of the first dummy area, A second dummy area having a size different from that of the first dummy area is disposed at a position where the first dummy area is erased and between the circuit pattern and the first dummy area. Then, a second step of determining a second arrangement that is the arrangement of the second dummy area,
A third step of creating a photomask that transfers the first dummy areas arranged in the first arrangement, the second dummy areas arranged in the second arrangement, and the circuit pattern; A photomask making method provided. The photomask making method according to claim 9,
In the second step, in addition to the first dummy area overlapping the circuit pattern, the first dummy area existing around the circuit pattern is also erased, thereby A photomask creating method for determining the first arrangement of dummy areas. The photomask making method according to claim 9,
In the first step, the second pattern further includes a pattern of an element or a well,
In the second step, the first arrangement is determined by further erasing the first dummy region in a portion overlapping with the element pattern or in a portion overlapping the boundary of the well pattern, The dummy region is erased, and the second dummy region is further disposed between the first dummy region and the boundary portion of the element pattern or the well pattern, Determine the second placement,
In the third step, the photomask is produced by further transferring the pattern of the element or the well. A method of manufacturing a semiconductor device comprising a step of forming a photoresist using a photomask,
The photomask is
A first step of preparing a first pattern in which a plurality of first dummy regions are regularly arranged;
A second step of preparing a second pattern in which element and circuit patterns or well patterns are described;
The first and second patterns are overlapped, and the first dummy region is erased by erasing a portion overlapping the element and circuit patterns or a portion overlapping a boundary of the well pattern. A third step of determining the placement of the dummy area;
A fourth step of creating a photomask in which the first dummy region whose arrangement has been determined and the pattern of the element and circuit or the pattern of the well are transferred;
In the third step, a second dummy region having a size different from that of the first dummy region is provided at a position where the first dummy region is erased, in the pattern of the element and circuit or the pattern of the well. A method for manufacturing a semiconductor device, which is created by a photomask creation method in which a new mask is created so as not to overlap a boundary portion. A method of manufacturing a semiconductor device according to claim 12,
In the photomask manufacturing method, in the third step, in addition to the first dummy region of the portion overlapping the element and circuit pattern or the portion overlapping the boundary of the well pattern, the element and circuit A method of manufacturing a semiconductor device, wherein the arrangement of the first dummy regions is determined by also erasing the first dummy regions existing around a pattern or a boundary portion of the well pattern. A method of manufacturing a semiconductor device comprising a step of forming a photoresist using a photomask,
The photomask is
A first step of preparing a first pattern in which a plurality of first dummy regions are regularly arranged and a second pattern in which a circuit pattern is described;
A second step of determining the arrangement of the first dummy area by superimposing the first and second patterns and erasing the first dummy area in a portion overlapping the circuit pattern;
A third step of creating a photomask in which the first dummy region whose placement has been determined and the circuit pattern is transferred;
In the second step, a second dummy area having a size different from that of the first dummy area is newly disposed at a position where the first dummy area is erased so as not to overlap the circuit pattern. A method for manufacturing a semiconductor device, produced by a photomask producing method. 15. A method of manufacturing a semiconductor device according to claim 14,
In the second step, the photomask creating method also erases the first dummy area existing around the circuit pattern in addition to the first dummy area overlapping the circuit pattern. A method of manufacturing a semiconductor device, wherein the arrangement of the first dummy region is determined. 15. A method of manufacturing a semiconductor device according to claim 14,
The photomask making method is:
In the first step, the second pattern further includes a pattern of an element or a well,
In the second step, the placement of the first dummy region is determined by further erasing the portion of the first dummy region that overlaps the portion of the element pattern or the portion of the well pattern boundary. ,
In the third step, the photomask is obtained by further transferring the pattern of the element or the well,
In the second step, the second dummy region is not overlapped with the circuit pattern at the position where the first dummy region is erased, and further, the boundary portion of the element pattern or the well pattern A method of manufacturing a semiconductor device, which is newly arranged so as not to overlap. A method of manufacturing a semiconductor device comprising a step of forming a photoresist using a photomask,
The photomask is
A first step of preparing a first pattern in which a plurality of first dummy regions are regularly arranged and a second pattern in which a circuit pattern is described;
Overlaying the first and second patterns, and erasing the first dummy area that overlaps the circuit pattern determines a first arrangement that is the arrangement of the first dummy area, By arranging a second dummy area having a size different from that of the first dummy area at a position where the first dummy area has been erased so as not to overlap the circuit pattern, the second dummy area is arranged. A second step of determining a second arrangement which is an arrangement of the areas;
A third step of creating a photomask that transfers the first dummy areas arranged in the first arrangement, the second dummy areas arranged in the second arrangement, and the circuit pattern; A method for manufacturing a semiconductor device, which is created by a photomask creating method. A method of manufacturing a semiconductor device according to claim 17,
In the second step, the photomask creating method also erases the first dummy area existing around the circuit pattern in addition to the first dummy area overlapping the circuit pattern. Thereby, the manufacturing method of the semiconductor device, wherein the first arrangement of the first dummy region is determined. A method of manufacturing a semiconductor device according to claim 17,
The photomask making method is:
In the first step, the second pattern further includes a pattern of an element or a well,
In the second step, the first arrangement is determined by further erasing the first dummy region in a portion overlapping with the element pattern or in a portion overlapping the boundary of the well pattern, By disposing the second dummy region at a position where the dummy region is erased, not overlapping the circuit pattern, and further not overlapping the element pattern or the boundary of the well pattern, Determining the second arrangement;
In the third step, the photomask is a method of manufacturing a semiconductor device, wherein the pattern of the element or the well is further transferred. A method of manufacturing a semiconductor device comprising a step of forming a photoresist using a photomask,
The photomask is
A first step of preparing a first pattern in which a plurality of first dummy regions are regularly arranged and a second pattern in which a circuit pattern is described;
Overlaying the first and second patterns, and erasing the first dummy area that overlaps the circuit pattern determines a first arrangement that is the arrangement of the first dummy area, A second dummy area having a size different from that of the first dummy area is disposed at a position where the first dummy area is erased and between the circuit pattern and the first dummy area. Then, a second step of determining a second arrangement that is the arrangement of the second dummy area,
A third step of creating a photomask that transfers the first dummy areas arranged in the first arrangement, the second dummy areas arranged in the second arrangement, and the circuit pattern; A method for manufacturing a semiconductor device, which is created by a photomask creating method. A method of manufacturing a semiconductor device according to claim 20,
In the second step, the photomask creating method also erases the first dummy area existing around the circuit pattern in addition to the first dummy area overlapping the circuit pattern. Thereby, the manufacturing method of the semiconductor device, wherein the first arrangement of the first dummy region is determined. A method of manufacturing a semiconductor device according to claim 20,
The photomask making method is:
In the first step, the second pattern further includes a pattern of an element or a well,
In the second step, the first arrangement is determined by further erasing the first dummy region in a portion overlapping with the element pattern or in a portion overlapping the boundary of the well pattern, The dummy region is erased, and the second dummy region is further disposed between the first dummy region and the boundary portion of the element pattern or the well pattern, Determine the second placement,
In the third step, the photomask is a method of manufacturing a semiconductor device, wherein the pattern of the element or the well is further transferred.

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