JP4575928B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device, and more particularly to electrode formation on the back surface of a semiconductor element.

  There is a TAB (Tape Automated Bonding) technology in which an electrode is provided on the element formation surface of a semiconductor element and connected to an electrode of a base substrate (wiring board), and the electrode of the base substrate is connected to a printed circuit board or a ceramic substrate. Usually done. On the other hand, a semiconductor device having a chip-on-chip structure in which a plurality of semiconductor elements are stacked in two layers has attracted attention. If this chip-on-chip structure is used, there is an advantage that further integration of semiconductor elements can be achieved.

  When this chip-on-chip structure is adopted, so-called face-up bonding is performed at the time of mounting, and wire wiring between the electrode on the element formation surface of the semiconductor element and the electrode on the base substrate is necessary.

Because of this wire wiring, a base substrate is essential, there is no room for omitting the base substrate, and a base substrate having a large area is required, so that there is a problem that high-density mounting cannot be performed.
Therefore, an object of the present invention is to realize a chip-on-chip semiconductor device that can be directly connected to a printed circuit board or the like without using a base substrate.

The semiconductor device according to claim 1, wherein the semiconductor element has an electrode on a surface that is bonded to the element formation surface so as to face the element formation surface of the semiconductor element, and that faces the element formation surface. A smaller semiconductor chip, a bump electrode disposed outside the region where the semiconductor chip is bonded on the element formation surface, an outer side than the bump electrode, one end connected to the bump electrode, and the semiconductor The other end is arranged in a region where the semiconductor chip on the element formation surface is joined to the wiring drawn out to the back surface opposite to the element formation surface in the semiconductor element through the through hole penetrating the element, and a second bump electrode joined to the electrode of the chip, the wiring is formed in a bump shape that penetrates the through hole is filled in the through hole, One said formed so as to protrude from the back surface of the semiconductor device, the bump electrode, the semiconductor chip in the element formation surface in the outer side than the second bump electrodes are arranged outside the region to be joined The through hole is disposed outside the bump electrode .

The semiconductor device according to claim 2 is for improving the adhesion between the bump electrode and the semiconductor element and between the bump-shaped wiring and the semiconductor element, respectively. The semiconductor device according to claim 1, wherein a TiW alloy layer is formed .
According to the above configuration, even when a package is formed such that the element formation surface is facing up (face up), electrode connection can be made from the back surface of the chip, so direct connection to a printed circuit board or the like can be achieved. Further, since it is not necessary to use a base substrate, high-density mounting is possible. Furthermore, a chip-on-chip structure can be suitably employed.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the embodiment of the present invention, it is assumed that Si is used as the semiconductor type, but other semiconductors such as GaAs and Ge may be used.
FIG. 1 is a cross-sectional view showing a mounted state of the semiconductor device of the present invention.
A plurality of bump electrodes 6 and 20 are formed in the element formation region of the Si semiconductor element 1, and another semiconductor chip 21 is placed on a part of the bump electrodes 20. The semiconductor chip 21 is bonded to the element formation surface so as to face the element formation surface of the semiconductor element 1, has an electrode on the surface facing the element formation surface, and is smaller than the semiconductor element 1. The bump electrode 20 as the second bump electrode is disposed in a region where the semiconductor chip 21 is bonded on the element forming surface of the semiconductor element 1, and is bonded to the electrode of the semiconductor chip 21. Other bump electrode 6 than the bump electrode 20 semiconductor chips 21 are disposed outside the region to be joined in the element formation surface of the semiconductor element 1 at the outside is provided outside the Oite bump electrode 6 to the chip The bump metal 8 disposed outside the bump electrode 6 is penetrated through the through-hole through the wiring 7 connected to the bump electrode 6 to electrically connect the lead 11 on the substrate 10 on the back surface of the chip. Is possible .

FIG. 2 is a cross-sectional view showing another embodiment of the Si semiconductor element 1. The difference between the Si semiconductor element 1 and the Si semiconductor element 1 of FIG. 1 is that there is no step in the wiring 7 connected from the bump electrode 6, but the presence or absence of the step is not essential in the subsequent manufacturing process.
Next, a method for manufacturing the Si semiconductor element 1 of the type shown in FIG. 2 will be described.
FIG. 3 is a process diagram for explaining the manufacturing method. A through hole 1 a is formed in advance in the substrate of the Si semiconductor element 1. FIG. 3A shows a process of applying a passivation film 3 such as SiN, SiON, SiO ₂ , PSG or the like on the substrate 1 on which the Al electrode 2 as a pad electrode is formed. The passivation film 3 is applied to the side wall of the through hole 1 a and the back surface of the substrate 1. An example of a method for forming the passivation film 3 is plasma CVD.

Next, as shown in FIG. 3B, a seed in which a TiW alloy layer for improving adhesion to the base and a layer of Au, Pt or the like for feeding a plating is laminated on the entire region of the substrate 1. Layer 4 is deposited by a method such as sputtering.
Next, a photoresist 5 is applied except for the area to be bump-plated (FIG. 3C).
Then, the bump metal is thickly plated by electrolytic plating (FIG. 3 (d)). Examples of the bump metal include Au, Pd, Pt, Ag, Ir (iridium), and Cu. Of the formed bumps, the bump formed on the Al electrode 2 is denoted by reference numeral 6, the bump formed around the through-hole 1 a is denoted by numeral 8, and an intermediate wiring portion is denoted by numeral 7. Instead of the electrolytic plating method, an electroless plating method that is a metal plating film formation method using a reducing action by a chemical reaction may be employed.

Next, the photoresist 5 is removed, the surface seed layer 4 is removed, and an annealing process is performed to obtain a semiconductor element in which bumps are formed in the through holes (FIG. 3E).
FIG. 4 is a schematic diagram showing a process of forming bumps in the through holes later in the stepped Si semiconductor element 1 shown in FIG. First, bumps 6 and wirings 7 connected to the bumps 6 are formed on the element formation surface, and through holes 1a are provided (FIG. 4 (a)). Thereafter, bumps 8 are formed in the through holes 1a (FIG. 4 ( b)).

  FIG. 5 is a process diagram for explaining in detail the process of forming the bumps 8 in the through holes 1a later. FIG. 5A shows the Si semiconductor element 1 in which the bump 6 is formed on the Al electrode 2 on the element forming surface, the wiring 7 connected thereto is formed, and the through hole 1a is provided. Reference numeral 3 denotes a passivation film 3. From this state, in order to insulate the side wall of the through-hole 1a from the back surface of the substrate 1, the entire surface is covered with a passivation film 3a, and other than the bump portion is covered with a resist film (not shown), and only the bump portion is etched. Thereafter, the resist film is removed (see FIG. 5B). Since the oxide film has already been formed on the surface of the substrate 1, the passivation film 3a may be selectively provided only on the back surface of the substrate 1 and the side wall of the through hole 1a.

Then, the bump metal 8 is thickly plated only in the vicinity of the through hole 1a by the electrolytic plating method or the electroless plating method (see FIG. 5C).
A cross-sectional view of the through hole 1a of the semiconductor element thus formed is shown in FIG. A bump 8 connected to the wiring 7 passes through the through hole 1a. This bump 8 functions as a back electrode. In the semiconductor device manufactured by the method shown in FIG. 3, FIG. 4, or FIG. 5, as shown in FIG. 1, FIG. 2, or FIG.

  As a method of using the back electrode, it can be directly soldered to the lead 11 of the substrate 10 as shown in FIG. Accordingly, the base substrate (wiring board) that has been conventionally required is not particularly required, and the semiconductor element can be made thinner and smaller. In particular, when a chip-on-chip structure is employed, the structure of the present invention is effective because the package must be made such that the element formation surface is opposite to the substrate (face-up).

  The present invention is not limited to the embodiment described above. For example, as shown in FIG. 7, a through hole 1a is formed immediately below the pad electrode 2, and the insulating film 3 and the seed layer 4 are interposed therebetween. The bump 6a may be formed. The 1a can be formed by using an anisotropic etching technique. In addition, various modifications can be made within the scope of the present invention.

It is sectional drawing which shows the mounting state of the semiconductor device of this invention. FIG. 3 is a cross-sectional view showing a state in which bumps are formed in the through holes of the semiconductor element 1. It is process drawing for demonstrating the manufacturing method for forming a bump through a through-hole. It is process schematic for demonstrating the manufacturing method in the case of providing a bump in a through-hole by a post process. It is process detail drawing for demonstrating the manufacturing method in the case of providing a bump in a through-hole by a post process. It is sectional drawing of the through-hole of the semiconductor element by which bump was formed in the through-hole. It is sectional drawing which shows embodiment which provided the through-hole 1a to the chip | tip back surface just under the pad electrode 2 of the element formation surface of a semiconductor element, and made the bump metal 6a penetrate to the said through-hole 1a.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor element 1a Through-hole 6 Bump electrode 7 Wiring 8 Bump metal (wiring)
20 Bump electrode (second bump electrode)
21 Semiconductor chip

Claims (2)

A semiconductor element;
A semiconductor chip which is bonded to the element formation surface so as to face the element formation surface of the semiconductor element, has an electrode on the surface facing the element formation surface, and is smaller than the semiconductor element;
Bump electrodes arranged outside the region where the semiconductor chip is bonded on the element formation surface;
Wiring disposed outside the bump electrode, connected at one end to the bump electrode, and through the through-hole penetrating the semiconductor element, and the other end drawn to the back surface of the semiconductor element opposite to the element formation surface When,
A second bump electrode that is disposed in a region where the semiconductor chip is bonded on the element formation surface and is bonded to the electrode of the semiconductor chip;
The wiring is formed in a bump shape that fills the through-hole and penetrates the through-hole , and is formed to protrude from the back surface of the semiconductor element ,
The bump electrode is disposed outside the region where the semiconductor chip is bonded on the element formation surface outside the second bump electrode ,
The semiconductor device , wherein the through hole is disposed outside the bump electrode .   A TiW alloy layer is formed between the bump electrode and the semiconductor element, and between the bump-shaped wiring and the semiconductor element, respectively, for improving adhesion between them. 1. The semiconductor device according to 1.

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