JP4579798B2 - Arithmetic unit - Google Patents

Description

  The present invention relates to an arithmetic device that executes a product-sum operation process.

  Currently, computers are making great progress and are being used in various situations around the world. However, the so-called Neumann computer is very poor at processing that humans can easily perform (such as recognition of human faces in real time) due to the characteristics of the processing method itself.

  In contrast, a neural network, which is an arithmetic processing model that imitates the information processing mode of the brain, has been studied.

  The following models are generally used as models of neurons constituting the neural network. First, the multiplication value obtained by weighting the output values of other units (neurons) with the synaptic load value is input to the unit corresponding to the neuron, and the output value is obtained by further nonlinearly converting the sum of the input values. And

  That is, in a general neural network, desired processing is realized by product-sum operation and non-linear transformation between each unit and between units.

  As a neural network architecture using the neuron model, an associative memory network in which units that perform a product-sum operation are coupled to each other has been proposed. Similarly, a pattern recognition model or the like in which units that perform product-sum operations are hierarchically coupled has been proposed.

  Here, it is necessary to more efficiently execute the product-sum operation when aiming at the practical use of the neural network and making it an integrated circuit, and the necessity is particularly remarkable in terms of the execution speed of the operation. Become.

  Therefore, various inventions relating to a neuron model for executing a product-sum operation, a neural network architecture, and a product-sum operation processing circuit have been proposed as described below.

  As one of them, a method of configuring an LSI that can perform high-speed arithmetic processing using two-dimensional data with a high degree of parallelism has been proposed (for example, see Patent Document 1).

In addition, a method of configuring a hierarchical neurocomputer that performs a product-sum operation has been proposed (see, for example, Patent Document 2).
JP-A-7-282237 JP-A-5-210651

  However, in the method of Patent Document 1, since the arithmetic circuits are arranged in one column, the layout of the arithmetic circuits is limited, and there is a limit to the parallelism of the arithmetic operations.

  Further, in the method of Patent Document 2, the calculation for all operand values is executed in the product-sum calculation circuit, and the input order of the operand values input to the sum-of-products calculation circuit is arbitrary. It was difficult to improve speed.

  Accordingly, an object of the present invention is to execute product-sum operations of operand values distributed in an array in parallel using product-sum circuits arranged in an array.

  In addition, the product-sum operation can be executed in descending order or ascending order of the value of the operand. Further, it is intended to improve the calculation speed by executing the calculation only for the value to be calculated that is equal to or greater than the predetermined value, or by performing the calculation only for a predetermined ratio value in descending or ascending order of the value of the calculated value. Is.

  In order to solve the above-described problem, according to the present invention, a plurality of product-sum operation means for performing product-sum operation processing including multiplication and accumulation of operand values represented by voltage values, according to the present invention, A plurality of voltage setting means for setting a predetermined voltage value, a plurality of input means for switching and inputting a combination of voltage values to the plurality of product-sum operation means, and a voltage value set by the plurality of voltage setting means, A plurality of switch means for switching connection of wirings for inputting to the plurality of input means; a sorting means for sorting the values of the operand values in descending or ascending order; and an output means for digitally outputting the calculation result by the product-sum calculating means With.

  According to the present invention, product-sum operations can be executed in descending or ascending order of values of operand values. Thereby, the fluctuation | variation of a calculated value can be decreased. In addition, it is possible to execute the product-sum operation of the operand values distributed in an array using the product-sum circuits arranged in the array. Furthermore, the calculation speed can be improved by performing the calculation only on the value to be calculated that is equal to or greater than the predetermined value, or performing the calculation only on the value of the predetermined value in descending or ascending order of the value of the calculated value.

  Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

(First embodiment)
FIG. 1 is a diagram illustrating a configuration of an arithmetic circuit in the present embodiment.

  In FIG. 1, a product-sum circuit array 1 is an array of product-sum circuits that perform multiplication and accumulation in an array (in this embodiment, 10 × 10). The load voltage setting circuit block 2 includes a plurality (three in this embodiment) of load voltage setting circuits for setting a predetermined voltage value. The step voltage setting circuit block 3 is composed of a plurality of (three in this embodiment) step voltage setting circuits for setting time-varying voltage values. The switch circuit block 4 includes a plurality (28 in the present embodiment) of switch circuits that switch the connection of wirings input to the predetermined product-sum circuit. The input circuit block 5 is composed of a plurality (10 in this embodiment) of input circuits that switch combinations of analog voltage values input to the product-sum circuit. The output circuit block 6 includes a plurality (10 in this embodiment) of output circuits that read out the operation results held in the product-sum circuit. The sorting circuit 7 sorts the calculation result values output from the output circuit block 6 in descending order. The decoder 8 decodes the address output from the sorting circuit 7, and two decoders 8 are provided in this embodiment.

  In FIG. 1, only the main wiring, input lines, and output lines are shown. Detailed wiring, input lines, and output lines are shown in each circuit diagram.

  Next, FIG. 2 shows a sorting circuit 7 composed of an associative memory. FIG. 3 shows the decoder 8. FIG. 4 shows the step voltage setting circuit 9 mainly composed of a current source and a capacitor. FIG. 5 shows the load voltage setting circuit 10 mainly composed of a current source and a capacitor.

  FIG. 6 shows a switch circuit 11 mainly composed of logic circuits. FIG. 7 shows an input circuit 12 mainly composed of logic circuits. FIG. 8 shows the product-sum circuit 13 composed of an analog multiplier and a capacitor. FIG. 9 shows an output circuit 14 composed of an A / D conversion circuit. FIG. 10 shows a part of the detailed wiring structure of the load voltage setting circuit 10, the switch circuit 11, and the decoder 8.

  Further, FIG. 11 shows a part of the detailed wiring structure of the step voltage setting circuit 9, the switch circuit 11, and the decoder 8. FIG. 12 shows a part of the detailed wiring structure of the product-sum circuit 13, the output circuit 14, and the sorting circuit 7. FIG. 13 shows a method for selecting a product-sum circuit area for performing product-sum operation in the arithmetic circuit 100 according to the present embodiment.

  With reference to the above-described diagrams, first, description will be given of how the arithmetic circuit as a whole is operated regarding the arithmetic processing step according to the product-sum arithmetic method in the present embodiment, and then the operation of each individual circuit will be described. Do.

  In the following embodiments, the power supply voltage is assumed to be 3.3V.

  The definition of signals used in this specification is as follows.

・ Digital signal: Signal that expresses information with two kinds of voltage values of High and Low ・ Analog signal: Signal that expresses information with voltage value ・ Pulse width modulation signal: Signal that expresses information with time width of pulse First, calculation How the processing is performed as a whole circuit will be described with reference to FIGS.

  1 and 13, the product-sum circuit array 1 is obtained by arranging the product-sum circuits 13 shown in FIG. 8 in a 10 × 10 array.

  Here, each product-sum circuit executes an operation represented by the following equation based on the input signal.

Here, u _MN represents the calculation result calculated by the product-sum circuit array, and the subscript MN represents the position of the product-sum circuit in the array (in the present embodiment, takes a value from 1 to 10). . In addition, w _xm represents an operation value input from a load voltage setting circuit, which will be described later, and the subscript m takes a value corresponding to the number of load voltage setting circuits at the maximum. Takes the value of Further, (o _j · w _yn ) indicates an operand value input from a step voltage setting circuit, which will be described later, and is represented by a product of o _j and w _yn . Here, the subscript _j of o _j indicates the order of output from the sorting circuit, and takes a value from 1 to 100 in this embodiment. In addition, since the subscript m takes a value corresponding to the number of step voltage setting circuits at the maximum, it takes a value from 1 to 3 in this embodiment.

  Subsequently, the load voltage setting circuit block 2 includes three load voltage setting circuits 10 arranged. The step voltage setting circuit block 3 includes three step voltage setting circuits 9 arranged side by side. The switch circuit block 4 includes switch circuits 11 arranged as shown in FIG. The input circuit block 5 includes 10 input circuits 12 arranged side by side. The output circuit block 6 includes 10 output circuits 14 arranged side by side.

First, a pulse width modulation signal having a pulse width corresponding to the value to be calculated w _xm is input to the load voltage setting circuit block 2 for each load voltage setting circuit 10. In the load voltage setting circuit 10, a voltage value corresponding to the operation value w _xm is set as will be described later.

In addition, a pulse width modulation signal having a pulse width corresponding to the value of the operand value w _yn is input to the step voltage setting circuit block 3 for each step voltage setting circuit 9. In the step voltage setting circuit 9, a voltage value corresponding to the operand value w _yn is set in the capacitor 17 as will be described later. Further, the calculation result of ( _operated value o _j ) × ( _operated value w _yn ) is applied to the capacitor 20 by the voltage value set in the capacitor 17 and the control pulse input corresponding to the search value in the sorting circuit 7 ( o _j · w _yn ) is set.

  Subsequently, a predetermined value is input as a search value to the sorting circuit 7. The sorting circuit 7 outputs 4-bit address signals in the X direction and Y direction of the memory cells holding the data matching the search value among the held data, and each address signal is sent to the corresponding decoder 8 respectively. Entered. The decoder 8 decodes the 4-bit address signal and sets one output line corresponding to the decoded value to High among the ten output lines.

An output line of the decoder 8 is connected to an address signal line of the switch circuit block 4 connected to the load voltage setting circuit 10 and the switch circuit block 4 connected to the step voltage setting circuit 9. As will be described later in the description of the switch circuit 11, the switch circuit 11 connected to the high address signal line includes the analog voltage input from the load voltage setting circuit 10 and the step voltage setting circuit 9, and the product-sum circuit 13. And a sign signal corresponding to the sign of the operand value w _xm and operand value (o _j · w _yn ) is output to a signal line connected to the input circuit 12.

  The address signal lines are wired obliquely to the switch circuit block 4 as shown in FIG. 1, and a signal is input to an appropriate row / column of the product-sum circuit array 1 corresponding to the address. Is possible.

  In response to the sign signal input from the switch circuit 11, the input circuit 12 outputs a differential voltage pair of the analog voltage and the reference voltage that are also input from the switch circuit 11 to a signal line to which the sum-of-products circuit array 1 is connected. .

  In the product-sum circuit array 1, as shown in FIG. 1, the following three types of signals are input for each row and each column from the input circuit block 5 positioned on the left side and the lower side, respectively.

Row direction: M_STOP_Y, W_P, W_N
Column direction: M_STOP_X, R_P, R_N
In FIG. 1, three types of signal lines are shown, but the distinction between the signal lines is not shown because of space limitations. Details will be described in the description of the individual circuit.

  As shown in FIG. 23, these signals input to the product-sum circuit array 1 in the row direction and the column direction are respectively three types of signals, each of which is a product-sum for each row or column for the product-sum circuit array 1. A common signal is input to the circuit through a signal line passing through the product-sum circuit array 1 in the row direction or the vertical direction. That is, common signals (M_STOP_Y, W_P, W_N) are input to the product-sum circuits adjacent in the row direction, and common signals (M_STOP_X, R_P, R_N) are input to the product-sum circuits adjacent in the column direction. .

  As described later, the product-sum circuit 13 performs multiplication on the input differential voltage pair, and accumulates the multiplication result by the capacitor 47.

  Here, as shown in FIG. 13, the product-sum circuit 13 in which the product-sum operation is performed in the product-sum circuit array 1 is limited to one in which both the input signals M_STOP_X and M_STOP_Y are High (indicated by dotted lines in the figure). 3 × 3 product-sum circuit).

  That is, this means that the area of the product-sum circuit 13 that performs the product-sum operation in the product-sum circuit array 1 is controlled by the M_STOP signal input from the outside and the address signal from the sorting circuit 7.

  Note that the M_STOP_Y and M_STOP_X signals are not directly input from the load voltage setting circuit and the step voltage setting circuit to the sum-of-products circuit array. The logic operation is performed and then input to the sum-of-products circuit array. FIG. 13 schematically shows a method for controlling the operation area of the sum-of-products circuit while omitting those computation processes.

  The above calculation flow is repeated to execute a desired product-sum operation.

  When the accumulation result is read by the output circuit 14, the voltage output signal CAP_OUT_SW is input to the output circuit 14 for each column of the product-sum circuit array 1 to read the result. The read calculation result is input to the array of the sorting circuit 7 in correspondence with the array of the product-sum circuit array 1. At this time, the arrangement of the product-sum circuit array 1 and the arrangement of the sorting circuit 7 are in a one-to-one correspondence.

  It is also possible to repeat the arithmetic processing described above after all the arithmetic results of the sum-of-products circuit array 1 are read by the output circuit 14 and held in the sorting circuit 7.

  Subsequently, the operation of each individual circuit will be described.

  First, as shown in FIG. 2, the sorting circuit 7 is configured by an associative memory 15 arranged in an array like the product-sum circuit array 1.

In this embodiment, the array arrangement is 10 × 10, but a different array arrangement may be used as necessary. Each memory cell (m, n) in the associative memory 15 holds the value of the operand value o _j as a digital value. Here, (m, n) indicates the position of each memory cell in the array. In the present embodiment, m and n each take a value of 1 to 10.

1 and 2, a control unit that executes search processing and the like described later is omitted. The 5-bit operand value o _j shown in FIG. 2 is a value input from the output circuit 14 or an external circuit. Here, the value of the operand value o _j shown in FIG. 2 is an example for explaining the present embodiment.

Although the bit length of each memory cell of the associative memory is 5 bits here, it may have other bit lengths depending on the bit length of the value of the operand value o _j .

The associative memory 15 has a function of outputting an address value in each of the X direction and the Y direction of the memory cell holding the operation value o _j that matches the input search value. The address value in this embodiment has a 4-bit value in each of the X direction and the Y direction.

Therefore, by increasing or decreasing the search value monotonously from the desired initial value, it becomes possible to read the addresses of the operand values o _j held in the associative memory in the ascending or descending order of the values. In the present embodiment, reading is performed in ascending order of values.

  Also, here, when the search value is monotonously increased, an address related to a value less than the initial value of the search value is not read, and when the search value is monotonously decreased, a value smaller than the predetermined search value The address for is not read.

Here, the search value and its initial value can be arbitrarily set according to the desired arithmetic processing. In this embodiment, in order to use only about 30% from the largest value of the operand value o _{j in} the calculation process, the minimum search value is (10001), and the operand has a value less than this search value. The address related to the value o _j is set so as not to be read (not subject to calculation).

If there are a plurality of operand values o _j whose values match the search value, the addresses of the operands o _j are output in an appropriate order.

  In this embodiment, the search value is input from the outside, but a counter circuit or the like may be prepared and generated internally. Other methods may be used as long as the same processing can be performed.

  In this embodiment, the sorting circuit 7 is configured by the associative memory 15. However, the sorting circuit 7 may be configured by other circuits as long as the function described above can be realized.

  Next, the two decoders 8 will be described. As shown in FIGS. 1 and 3, each decoder 8 receives one of the corresponding 4-bit address values output from the sorting circuit 7 in the X and Y directions.

  The decoder 8 decodes the 4-bit address value and sets one output line corresponding to the decoded value to High among the ten output lines. Here, the output line which becomes high among the 4-bit data and the 10 output lines corresponds as follows.

Address value Output line 0000 1000000000
0001 0100000000
0010 0010000000
0011 0001,000,000
0100 0000100000
0101 00000100
0110 0000001000
0111 0000000100
1000 0000000010
1001 0000000001
The ten output lines of the decoder 8 are connected to the switch circuit 11 as shown in FIGS. 10 and 11, and as described above, one signal line is set to High corresponding to the address value.

  Next, the step voltage setting circuit 9 will be described with reference to FIG. As shown in FIG. 2A, the step voltage setting circuit 9 includes a two-stage circuit group including a current source, a capacitor, a source follower, and a reset switch.

First, a pulse width modulation signal PWM_IN_R having a pulse width corresponding to the value of the operand value w _yn is input as a control signal for controlling on / off of the operation of the current source 16.

At this time, the pulse width modulation signal PWM_IN_R having a pulse width corresponding to the value of the operand value w _yn may be input from the outside, or a memory circuit and a digital / pulse width modulation circuit are separately prepared and generated. It doesn't matter. In the present embodiment, it is assumed that the input is from outside. Further, a bias signal BIAS_CS for determining a current value is input to the gate of the current source 16.

Details of the vicinity of the current source 16 are shown in FIG. The current source 16 is constituted by, for example, a CMOS circuit as shown in FIG. The MOS element 16 allows a current to flow only while the pulse width modulation signal PWM_IN_R is High, and charges are accumulated in the capacitor 17. For this reason, the voltage of Node 0 indicates a voltage value proportional to the pulse width of the pulse width modulation signal PWM_IN_R, and corresponds to the value of the operand value w _yn as described above.

Subsequently, the voltage of Node 0 is applied to the current source 19 by the source follower 18. Details of the vicinity of the current source 16 are shown in FIG. As shown in the figure, when a MOS element is used as the current source 19, the current value is controlled by the gate voltage, so the current value flowing through the current source 19 is controlled by the voltage value of Node0. As described above, since the voltage value of Node 0 corresponds to the value of the operand value w _yn , as a result, the current value flowing through the current source 19 corresponds to the value of the operand value w _yn .

  Subsequently, a control pulse FLAG_IN for controlling on / off of the operation is input from the sorting circuit 7 to the current source 19. The control pulse FLAG_IN is input when the search value is changed (increased) by one unit in the sorting circuit 7 described above.

The MOS element functioning as the current source 19 causes a current to flow only while the control pulse FLAG_IN is High, and charges are accumulated in the capacitor 20. Therefore, the voltage of Node1 increases corresponding to the value of the operand value w _yn every time the search value is changed (increased) by one unit in the sorting circuit 7. Note that the initial value of Node 1 is set in association with the initial value of the search value in the sorting circuit 7.

At this time, since the value stored in the sorting circuit 7 is the operand value o _j , as a result, the voltage value of Node 1 can be associated with the calculation result of the following equation.
(Operation value w _yn ) × (Operation value o _j ) (Expression 2)
Subsequently, the voltage value of Node 1 is read by the source follower 21 and input to the switch circuit block 4 as shown in FIGS.

  In FIG. 4, the two reset switches 22 and 23 are used for initializing charges accumulated in the capacitors 17 and 20. Further, the initial voltage value of the capacitor 20 (the voltage value of Node 1) is made to correspond to the minimum search value in the sorting circuit 7 as described above.

In the present embodiment, a current source that performs operation control using a pulse width modulation signal is used, but other control signals may be used as long as the operation of the current source can be controlled. In addition, any circuit configuration may be used as long as a value corresponding to the above-described ( _operating value w _yn ) × ( _operating value o _j ) can be set.

  Next, the load voltage setting circuit 10 will be described with reference to FIG.

  The load voltage setting circuit 10 includes a current source 24, a capacitor 25, a source follower 26, and a reset switch 27, as shown in FIG.

Here, first, a pulse width modulation signal PWM_IN_W having a pulse width corresponding to the value of the operand value w _xm is input as a control signal for controlling on / off of the operation of the current source 24.

  Further, a bias signal BIAS_CS_W for determining a current value is input to the gate of the current source 24. Here, the current source 24 is constituted by a CMOS circuit, for example, as shown in FIG.

In the MOS element functioning as the current source 24, the current flows only while the pulse width modulation signal PWM_IN_W is High, and electric charge is accumulated in the capacitor 25. Therefore, the voltage of Node3 is proportional to the pulse width of the pulse width modulation signal PWM_IN_W. This indicates a voltage value, which corresponds to the value of the operand value w _xm as described above.

  Subsequently, the voltage value of Node 3 is read by the source follower 26 and input to the switch circuit block 4 as shown in FIGS.

  In FIG. 5, the reset switch 27 is used to initialize the electric charge accumulated in the capacitor 25.

In the present embodiment, a current source that performs operation control using a pulse width modulation signal is used, but other control signals may be used as long as the operation of the current source can be controlled. In addition, any circuit configuration may be used as long as a value corresponding to the above-described operand value w _xm can be set.

  Next, the switch circuit 11 will be described with reference to FIG. 1, FIG. 6, FIG. 10, and FIG. As shown in FIG. 6, the switch circuit 11 includes a NAND gate 28, an inverter 29, and switches 30, 31 and 32.

There are a total of four input signals: an analog voltage INPUT_V, a control signal M_STOP that controls the operation in the product-sum circuit 13, a sign signal SIGN, and an output signal DEC_OUT from the decoder 8. Here, the analog voltage INPUT_V is an output signal of the load voltage setting circuit 10 or the step voltage setting circuit 9 described above, and the sign signal SIGN is the operand value w _xm and (the operand value w _yn × the operand value o _j ). It corresponds to the sign of.

  Further, the control signal M_STOP and the sign signal SIGN may be input from an external circuit or may be input from a separately prepared memory circuit. In this embodiment, it is assumed that input is from an external circuit.

Here, when the output signal DEC_OUT from the decoder 8 becomes High, the analog voltage INPUT_V that is an output signal of the load voltage setting circuit 10 or the step voltage setting circuit 9 is output to the output line via the switch 30. At the same time, the sign signal SIGN indicating the sign of the operand value w _xm and (the operand value w _yn × the operand value o _j ) is output to the output line via the switch 32. At this time, if the control signal M_STOP for controlling the calculation in the product-sum circuit 13 is High, the output line M_STOP is High.

  A total of three output lines of the switch circuit 11 described above are connected to output signal lines that are input lines to the input circuit 12 at the subsequent stage, as shown in FIGS.

  10 and 11, input signals of the load voltage setting circuit 10 and the step voltage setting circuit 9 are omitted. Further, the switch circuit 11 shows only what is necessary for the description, and a part of the switch circuits is omitted.

  Next, the input circuit 12 will be described with reference to FIG. The input circuit 12 includes NAND gates 33 and 34, NOR gates 35 and 36, 2-1 selectors 37 and 38, inverters 39, 40, 41, 42 and 43, and switches 44 and 45. Note that the inverters 39 and 40 have a function of latching the M_STOP signal when the M_STOP_RESET signal is High.

  The input signal of the input circuit 12 includes seven signals: an analog voltage INPUT_V, a sign signal SIGN, a control signal M_STOP, a control signal M_STOP_RESET, a reference voltage input BASE_BIAS, a control signal M_STOP_ON, and a reset signal RESET.

  Among these, the analog voltage INPUT_V, the sign signal SIGN, and the control signal M_STOP are as described above for the switch circuit 11 and are input from the switch circuit block 4.

  The control signal M_STOP_RESET resets the input line of the control signal M_STOP that controls the calculation in the product-sum circuit 13. The reference voltage input BASE_BIAS is set to 1.65 V in this embodiment. The control signal M_STOP_ON controls the arithmetic operation. The reset signal RESET resets the analog voltage output pair.

  Among the above input signals, the control signal M_STOP_RESET, the reference voltage input BASE_BIAS, the control signal M_STOP_ON for controlling the arithmetic operation, and the reset signal RESET for resetting the analog voltage output pair are supplied to all the input circuits 12. Input in common.

  The output signals are three in total: two output voltages serving as differential pair inputs to the product-sum circuit 13 and one control signal (M_STOP_X or M_STOP_Y) for turning on / off the arithmetic operation of the product-sum circuit 13.

Here, the output voltage pair of the differential pair is inverted by the High / Low of the sign signal SIGN indicating the sign of the operand value w _yn and (the operand value w _yn × the operand value o _j ). For example, when the sign signal SIGN is High, the output A is 2.0 V and the output B is 1.65 V. When the sign signal SIGN is Low, the output A is 1.65 V and the output B is 2.0 V. The output line pair is inverted without changing itself.

  Further, when the reset signal RESET becomes Low, or when the latched signal of the control signal M_STOP is Low (when the potential of Node 5 is Low), the reference voltage BASE_BIAS is output from both the outputs A and B.

  When the reset signal RESET is High and the latched signal of M_STOP is High (when the potential of Node5 is High), one of the outputs A and B becomes the reference voltage BASE_BIAS, and the other becomes the analog voltage INPUT_V. .

  Further, only when the input control signal M_STOP_ON is High and the input control signal M_STOP is High, the control signal output (M_STOP_X or M_STOP_Y) for turning on / off the arithmetic operation of the product-sum circuit 13 becomes High.

  Next, the product-sum circuit 13 will be described with reference to FIG. The product-sum circuit 13 includes a multiplier 46, a capacitor 47, a NAND gate 48, switches 49, 50 and 51, and a source follower 52. In the present embodiment, a four-quadrant multiplier is used as a multiplier. However, other multipliers may be used as long as the same function can be realized.

  The input signal of the product-sum circuit 13 includes two sets of differential voltage pair inputs (W_P and W_N, RAMP_P and RAMP_N), a bias voltage input VI, a reset signal CAP_RESET_SW of the capacitor 47, and a reset voltage CAP_RESET_V of the capacitor 47. Including. Further, it includes an output control signal CAP_OUT_SW and control signals M_STOP_X and M_STOP_Y of a switch 49 connected between the multiplier 46 and the capacitor 47.

  The output signal of the product-sum circuit 13 is a voltage value output corresponding to the product-sum operation result.

  The multiplier 46 performs multiplication on the input differential voltage pair (W_P and W_N, RAMP_P and RAMP_N), and outputs the result to the capacitor 47 as a current value I1.

  Here, as shown in FIG. 1, two sets of differential voltage pairs (W_P and W_N, RAMP_P and RAMP_N) include an input voltage from the load voltage setting circuit 10, and the other set includes a step voltage. The input voltage from the setting circuit 9 is included.

As described above, the voltage value of the load voltage setting circuit 10 corresponds to (calculated value w _xm ), and the voltage value of the step voltage setting circuit 9 is (calculated value w _yn × _operated value o _j ). It corresponds. Therefore, in the multiplier 46, the calculation of the following formula 3 is executed.

(Operation value w _xm ) × (Operation value w _yn × Operation value o _j ) (Equation 3)
The current corresponding to the calculation result flows into (or flows out of) the capacitor 47 connected via the switch 49, and is accumulated as electric charge. Here, by making the calculation time t 1 performed by the multiplier 46 constant, the charge of I × t 1 is accumulated in the capacitor 47.

  A switch 49 is arranged in front of the capacitor 47, and its on / off operation is controlled by the logical product of the signals M_STOP_X and M_STOP_Y.

  That is, in the product-sum circuit array 1, only in the product-sum circuit 13 in which both M_STOP_X and M_STOP_Y are High, the current of the calculation result flows into (flows out) the capacitor 47, and the multiplication result is accumulated. In the present embodiment, inflow of current corresponds to positive accumulation, and outflow of current corresponds to negative accumulation.

  By repeating the above multiplication and accumulating the current output for each multiplication in the capacitor 47 as an electric charge, the multiplication result can be accumulated.

  In this embodiment, since a differential multiplier is used as the multiplier 46, the current value I1 of the multiplication result is 0 when at least one of the differential pairs has the same voltage.

  The accumulated charge amount (that is, the accumulation result) is finally output as a voltage value of Node 4 via the source follower 52 and the switch 51. The Node 4 is connected to the output signal line of the product-sum circuit array 1 as shown in FIGS.

  When the voltage output signal CAP_OUT_SW is input for each column of the sum-of-products circuit array, the voltage value of the capacitor 47 is output to the Node 4 via the source follower 52.

  The voltage of the capacitor 47 is set to the reset voltage by turning on the switch 50 by a reset signal before the accumulation starts. The switch 50 is turned off until the accumulation is executed and the output is completed.

  In the present embodiment, the reset voltage is set to 1.65 V, but other voltage values may be set as necessary.

  Next, the output circuit 14 will be described with reference to FIGS. In FIG. 12, only signal lines related to reading the voltage value of the capacitor 47 of the product-sum circuit 13 are shown, and other signal lines related to input / output are omitted. In the present embodiment, the output circuit 14 is configured by the A / D conversion circuit 53.

  Here, the input terminal of the A / D conversion circuit 53 is connected to the output signal line of the product-sum circuit array 1. The output is connected to the input of the sorting circuit 7.

  That is, the output circuit 14 reads the product-sum operation result accumulated as electric charge in the capacitor 47 of the product-sum circuit 13 as a voltage value, converts it into a digital value, and outputs it.

  In the above description, FIG. 14 shows a timing chart example of main input signals. The timing chart of FIG. 14 is an example in the present embodiment, and other input signal timings may be used as long as the same processing can be performed.

(Second Embodiment)
A second embodiment of the present invention will be described with reference to a specific processing configuration diagram.

  In the present embodiment, arithmetic processing represented by the following expression is executed using the arithmetic circuit described in the first embodiment.

Here, the subscript _MN of uMN represents the row / column number when the operation value u is configured in an array. The subscript mn of the operand value w _mnj represents the row and column numbers of w distributed in an array as shown in the figure, and the suffix j represents the label of the operand value o 1.

At this time, the operand value w _mnj can be approximated by a product sum of a basis vector pair as shown in the following equation. In the specification, this is called load basis vector decomposition.

  FIG. 24 shows a case where w is distributed in a 3 × 3 array in the weight basis vector decomposition expressed by Equation 5.

In Equation 5, the equal sign holds when Nw is infinite. In actual use, an appropriate basis vector decomposition number Nw is determined according to the distribution of the load array, and w _mnj is approximated by a product-sum value of a set of appropriate basis vector pairs.

  Subsequently, when Expression 5 is substituted into Expression 4, the following expression is derived.

Here, the element of the basis vector w ^k _xj is regarded as the operand value wx _m described in the first embodiment, and the element of the product (o _j · w ^k _yj ) of the other basis vector w ^k _yj and o _j is used. Is the product of the operand value w _yn and operand value o _j (o _j · w ^k _yj ) described in the first embodiment, the arithmetic expression enclosed in braces {} in Equation 6 is It can be seen that the calculation can be performed by the product-sum circuit described in the first embodiment.

Therefore, the operand value wx _m and operand value w _yn are appropriately set as elements of a set of basis vector pairs for the desired w _mnj and are enclosed in the braces by the product-sum circuit described in the first embodiment. It is possible to approximately execute the calculation of Formula 4 by performing the calculation of the above formula and repeating it Nw times.

  As described above, the load values distributed in the array are executed in parallel by the arithmetic circuit described in the first embodiment by approximating the load values distributed in the array by the sum of products of the basis vector pairs. It becomes possible to do.

(Third embodiment)
A third embodiment of the present invention will be described with reference to a specific processing configuration diagram. FIG. 15 shows a configuration diagram of the arithmetic circuit 200 in the present embodiment.

  As can be seen from FIG. 15, the arithmetic circuit 200 in the present embodiment differs from the arithmetic circuit 100 in the first and second embodiments shown in FIG. 1 in the following points. First, the memory 54 is connected to the subsequent stage of the sorting circuit 7. Further, a memory 55 and a digital / pulse modulation circuit 56 are connected to the load voltage setting circuit 10 and the step voltage setting circuit 9. The output circuit block 6 includes a comparator 57 and a pulse / digital conversion circuit 58.

  Therefore, in the present embodiment, only the difference will be described, and the other parts will be omitted as they are the same as the first and second embodiments.

  First, the point that the memory 54 is connected to the subsequent stage of the sorting circuit 7 will be described.

  The memory 54 includes an X-direction / Y-direction address value output from the sorting circuit 7, a search value when the address is output, and a flag indicating whether or not one unit has been changed from the previous search value. Are stored in the output order. In the present embodiment, the X-direction and Y-direction address values each have a 4-bit value. Further, the flag indicating whether or not one unit has been changed from the previous search value indicates by one bit whether or not one unit has been increased in the present embodiment.

  The stored address values and flags are output in the order in which they are input to the memory 54. Note that the output order may be output in the reverse order to the order input to the memory 54, unlike the present embodiment.

  Here, the output address value is input to the decoder 8 in both the X direction and the Y direction, as in the first embodiment. At the same time, a flag is input to the step voltage setting circuit 9. At this time, the input flag corresponds to the control pulse FLAG_IN in the first embodiment.

  As described above, the memory 54 has a function of temporarily storing the address output from the sorting circuit 7 and the control signal of the step voltage setting circuit 9.

Therefore, in the calculation described in the first embodiment, the data (address value, flag) of the operand value o _j held in the sorting circuit 7 is temporarily stored in the memory 54. As a result, the memory cells of the sorting circuit 7 are released, and the sorting circuit 7 can be used for holding and sorting the next calculation result. It is also possible to use the calculated calculation result as the operand value o _j in the next calculation.

In the present embodiment, two sets of memory 54 for holding the previous calculation result and two sets of memory 54 for holding the calculation result when calculating the calculation result as the operand value o _j are prepared. is doing. That is, as shown in FIG. 15, a total of four sets of memories 54 are prepared. It should be noted that the number of sets in the memory 54 may be other set numbers depending on the arithmetic processing.

  Next, the point that the memory 55 and the digital / pulse modulation circuit 56 are connected to the load voltage setting circuit 10 and the step voltage setting circuit 9 will be described.

As shown in FIG. 15, the digital value (5 bits in this embodiment) of the operand value w _yn and operand value w _xm held in the memory 55 is converted into a pulse width modulation signal by the digital / pulse modulation circuit 56. . Thereby, the pulse width modulation signals PWM_IN_W and PWM_IN_R input to the load voltage setting circuit 10 and the step voltage setting circuit 9 in the first embodiment are generated.

  The memory 55 also stores a positive and negative sign (1 bit) together with the digital value, which is input to the switch circuit 11 as the sign signal SIGN in the first embodiment.

  The digital / pulse modulation circuit 56 described above may have any structure as long as it has a function of converting an input digital value into a pulse width modulation signal and outputting it.

  Next, the point that the output circuit block 6 is composed of the comparator 57 and the pulse / digital conversion circuit 58 will be described.

  FIG. 16 shows the output circuit block 6 constituted by the comparator 57 and the pulse / digital conversion circuit 58.

  The comparator 57 has a function of comparing the input voltage value (that is, corresponding to the calculation result output from the sum-of-products circuit array 1) with the reference voltage Vref, converting it into a pulse width modulation signal, and outputting the pulse width modulation signal.

  Although FIG. 16 uses the comparator 57 using an operational amplifier, a comparator having another circuit configuration may be used.

  In addition, when the reference voltage Vref is a voltage value that changes nonlinearly with respect to time, the input voltage value has a pulse width that has been subjected to nonlinear conversion determined by the time change of the reference voltage Vref. It can be converted into a width modulation signal.

  The pulse width modulation signal output from the comparator 57 is input to the pulse / digital conversion circuit 58 and converted into a digital value. The converted digital value is input and held in the sorting circuit 7 as in the first embodiment.

  The pulse / digital conversion circuit 58 described above may have any structure as long as it has a function of converting an input pulse width modulation signal into a digital value and outputting it.

  In the present embodiment, the memories 54 and 55 are constituted by SRAM. However, other circuits may be used as long as they have similar functions.

(Fourth embodiment)
A fourth embodiment of the present invention will be described with reference to a specific processing configuration diagram.

  FIG. 17 shows a configuration diagram of an arithmetic circuit in the present embodiment. As can be seen from FIG. 17, in the arithmetic circuit in this embodiment, the output circuit block 6 is configured by a comparator 57 and a pulse / digital conversion circuit 58, as in the arithmetic circuit of the third embodiment shown in FIG. . 15 is different from FIG. 15 only in that a look-up table (LUT) 59 is connected to the subsequent stage of the output circuit block 6.

  Therefore, in the present embodiment, only the difference will be described, and the other parts are the same as those in the third embodiment, and the description thereof will be omitted.

  As shown in FIG. 17, the digital values output from the pulse / digital conversion circuit 58 are input to the LUT 59 in parallel in a column.

  The LUT 59 once holds the input digital value in a built-in register, serially performs predetermined conversion on the held data, and outputs the converted value to the sorting circuit 7. That is, the LUT 59 has a function of executing a predetermined conversion on the operation result calculated by the product-sum circuit 13.

  The LUT 59 generally has the same configuration as that of a digital memory (for example, SRAM), but may have any structure as long as it has the above-described function.

(Fifth embodiment)
A fifth embodiment of the present invention will be described with reference to a specific processing configuration diagram.

  A model of neuron elements in a general neural network is shown in FIG. As shown in the figure, the general neuron element 60 determines the internal state value of the neuron element 60 by taking the sum of values obtained by weighting the output values of the plurality of neuron elements in the previous stage with the synaptic load. That is, the internal state value of the neuron element 60 is calculated by a product-sum operation.

  The calculation formula of the internal state value in each neuron element is shown below.

Here, the subscript _MN of UMN represents the row / column number when the internal state value U is configured in an array. _Further, the subscript mn of the synapse load value W _mnj represents the row / column number of W distributed in an array as shown in the figure, and the subscript j represents the label of the preceding neuron output value O.

  It can be seen that this is the same arithmetic expression as Expression 4 described in the second embodiment.

  Each neuron element performs nonlinear transformation (or linear transformation) on the internal state value, and then outputs the transformation value to the neuron element connected to the subsequent stage.

  Here, a neuron group region connected to a post-stage neuron element is generally called a receptive field.

  On the other hand, in a neural network having exactly the same connection, what defines a neuron group region connected to the preceding layer neuron as shown in FIG. 19 is called a projection field.

  The only difference between FIG. 18 and FIG. 19 is that the connection region is defined for one post-layer neuron or one pre-layer neuron.

  Therefore, the arithmetic processing executed as a neural network is exactly the same according to either definition.

In addition, the connection between neurons is defined using a projection field, and an array structure (one neuron element is represented by one cell) as shown in FIG. Suppose you have it. In this case, W _mnj can be approximated by the following equation, where W _mnj is the synaptic load distribution in the _connection with the _subsequent layer neuron defined for the output value Oj of one preceding layer neuron. In FIG. 20, W _mnj is shown in the cell of the corresponding _subsequent- stage neuron element.

  In this embodiment, Nw = 5, but other values may be used. The subscript i takes a value of 1 to 3 (integer), which matches the size of the projection field.

  FIG. 21 shows this in comparison with FIG. In FIG.

を対応する後段層ニューロン素子のセル内に示している。

Is shown in the cell of the corresponding post-stage neuron element.

  That is, the distribution of synaptic load values can be approximated by a product sum of a pair of appropriate basis vector pairs. This is the same principle as the basis vector decomposition described in the second embodiment.

  Therefore, as in the second embodiment, the synaptic load value is decomposed into a pair of appropriate basis vector pairs, and is repeatedly expressed by the arithmetic circuit described in the first embodiment. Neural network processing can be executed.

  Based on the above premise, in this embodiment, when the neural network is mounted as a circuit, the circuit configuration described in the first to fourth embodiments is applied.

That is, the operand value o _j in the first, third, and fourth embodiments corresponds to the output value O _j of the preceding neuron, and the operand value w _xn corresponds to an element of one basis vector W ^k _xj , The operand value w _yn corresponds to an element of the other one-dimensional basis vector W ^k _yj .

An area of the product-sum circuit 13 that performs product-sum operations in parallel on one operand value o _j corresponds to a projection field.

  In the product-sum circuit array, the calculation shown in Equation 1 is executed as described above, and this is repeated Nw times according to Equation 6, thereby realizing multiplication of the pre-stage neuron output value and the synapse load value.

After the above product-sum operation is completed for all preceding-layer neuron output values (that is, the operand value o _j ) to be calculated, the calculation result (voltage value) is output to the output circuit 14.

  Nonlinear conversion (or linear conversion) in the neuron element is executed by the A / D conversion circuit 53, the comparator 57, or the LUT 59, and the neuron output value is calculated.

  After the neuron output values are sorted by the sorting circuit 7, the address value and the flag are held in the memory 54 connected to the subsequent stage, and are used at the time of calculation related to the subsequent layer neuron.

  As described above, a neural network can be implemented by using the arithmetic circuit described in the first to fourth embodiments.

(Sixth embodiment)
A sixth embodiment of the present invention will be described with reference to a specific processing configuration diagram.

  The arithmetic circuit in this embodiment is shown in FIG. The arithmetic circuit in the figure executes image processing.

As can be seen from FIG. 22, the arithmetic circuit in the present embodiment is different from the arithmetic circuits in the first to fifth embodiments in that an imaging element array 61 (for example, a CCD or CMOS image sensor) is connected to the sorting circuit 7. Only that it is different. FIG. 22 shows the case of the fourth to fifth embodiments. )
That is, in the present embodiment, the arithmetic processing is performed on the image signal captured by the image sensor array 61 by the arithmetic circuit described in the first to fifth embodiments. This is intended to perform desired image processing (for example, pattern detection and pattern recognition).

  The content of the image processing that is actually realized is determined by the setting of the synapse load value, the projection field, and the like in the neural network that is realized by the arithmetic circuit. Since the detailed setting method is not the main point of the present invention, the description is omitted.

  Here, in the present embodiment, the image signal output from the image sensor array 61 is first input to the sorting circuit 7. The image signal is converted into a digital signal and then input to the sorting circuit 7. However, in FIG. 22, details regarding the conversion into the digital signal are omitted.

That is, the image signal is used in the calculation as the operand value o _j described in the first to fifth embodiments. Since the arithmetic processing after the sorting circuit is the same as in the first to fifth embodiments, the description thereof is omitted.

It is a figure which shows the whole structure of the arithmetic circuit in 1st Embodiment. It is a figure which shows the sorting circuit in 1st Embodiment. It is a figure which shows the decoder in 1st Embodiment. It is a figure which shows the step voltage setting circuit in 1st Embodiment. It is a figure which shows the load voltage setting circuit in 1st Embodiment. It is a figure which shows the switch circuit in 1st Embodiment. It is a figure which shows the input circuit in 1st Embodiment. It is a figure which shows the product-sum circuit in 1st Embodiment. It is a figure which shows the output circuit in 1st Embodiment. It is a figure which shows the connection from the load voltage setting circuit in 1st Embodiment to a switch circuit. It is a figure which shows the connection from the step voltage setting circuit in 1st Embodiment to a switch circuit. It is a figure which shows the connection from the sum of products circuit to a sorting circuit in 1st Embodiment. It is a figure which shows control of the product-sum circuit in 1st Embodiment. It is a figure which shows the timing chart of the main signal in 1st Embodiment. It is a figure which shows the whole structure of the arithmetic circuit in 2nd Embodiment. It is a figure which shows the output circuit in 2nd Embodiment. It is a figure which shows the whole structure of the arithmetic circuit in 3rd Embodiment. It is a figure explaining the receptive field in 4th Embodiment. It is a figure explaining the projection field in a 4th embodiment. It is a figure which shows the synaptic load distribution of the projection field in 4th Embodiment. It is a figure which shows the basis vector decomposition | disassembly of the synaptic load with respect to the projection field in 4th Embodiment. It is a figure which shows the whole structure of the arithmetic circuit in 5th Embodiment. It is a figure which shows the input of the signal with respect to a sum-of-products circuit array from the input circuit block in 1st Embodiment. It is a figure which shows the load basis vector decomposition | disassembly in 2nd Embodiment.

Claims (25)

A plurality of product-sum operation means for performing product-sum operation processing including multiplication and accumulation of operand values represented by voltage values;
A plurality of voltage setting means each for setting a predetermined voltage value;
A plurality of input means for switching and inputting a combination of voltage values to the plurality of product-sum operation means;
A plurality of switch means for switching connection of wirings for inputting voltage values set by the plurality of voltage setting means to the plurality of input means;
Sorting means for sorting the values of operands in descending or ascending order;
Output means for digitally outputting the result of the product-sum operation means;
A computing device having   The sorting means includes a holding means for holding the operand values, an address output means for outputting addresses at which the operand values are held in descending or ascending order of the operand values, The arithmetic unit according to claim 1, further comprising: decoding means for inputting to the switch means.   The arithmetic unit according to claim 1, wherein the sorting unit includes an associative memory.   4. The arithmetic device according to claim 1, wherein a part of the plurality of voltage setting means sets a voltage value that changes with time.   5. The arithmetic device according to claim 1, wherein a part of the plurality of voltage setting means has a function of weighting a value to be calculated in a product-sum operation process.   The arithmetic device according to claim 1, wherein the plurality of product-sum operation means are arranged in an array.   The arithmetic unit according to claim 1, wherein the product-sum operation unit includes an analog multiplier and a capacitor.   The arithmetic device according to claim 7, wherein the analog multiplier is a differential multiplier.   The arithmetic unit according to claim 1, wherein the output unit includes an A / D conversion circuit.   9. The arithmetic unit according to claim 1, wherein the output circuit includes a comparator and a pulse width / digital conversion circuit.   The arithmetic unit according to claim 1, wherein the voltage setting unit includes a current source and a capacitor.   The arithmetic device according to claim 1, further comprising a memory circuit that holds data of an operand value.   The arithmetic device according to claim 1, further comprising a pulse width / digital conversion circuit.   The arithmetic unit according to claim 1, further comprising a digital / pulse width modulation circuit.   15. The arithmetic device according to claim 1, further comprising a look-up table for executing a predetermined conversion process on the digital data output from the output means.   16. The arithmetic device according to claim 1, wherein one or both of the operand values in the product-sum operation processing are values distributed in a two-dimensional shape or an array shape.   The arithmetic unit according to claim 16, wherein one or both of the operand values are decomposed into basis vectors to perform a product-sum operation process.   The plurality of product-sum operation means includes a product-sum circuit array arranged in an array, and the operation value decomposed into the base vector, and the operation value further decomposed into the base vector and further weighted, 18. The arithmetic unit according to claim 17, wherein the arithmetic unit is input as a common signal for each row direction and each column direction through a signal line arranged for each row and column of the product-sum circuit array.   Multiple layers are hierarchically connected by synapses, and each layer performs product-sum operation including multiplication and accumulation of input signal from external or previous layer and synaptic load value, and outputs by nonlinear conversion or linear conversion The arithmetic device according to claim 1, wherein arithmetic processing of a neural network including a neuron that performs the processing is executed.   The arithmetic device according to claim 19, wherein the synapse load value is an arithmetic value to be decomposed into basis vectors.   21. The arithmetic unit according to claim 1, wherein a part of the arithmetic value is an image signal.   The computing device according to claim 21, further comprising an image sensor array that outputs the image signal.   The arithmetic device according to claim 21 or 22, wherein the plurality of product-sum operation means performs predetermined image processing on the image signal.   The arithmetic device according to any one of claims 1 to 23, wherein the plurality of product-sum operation means perform an operation only on an operand value having a value equal to or greater than a predetermined value. The arithmetic unit according to any one of claims 1 to 23, wherein in the plurality of product-sum operation means, the operation is performed only on the operation values included in a predetermined ratio in descending order of the values of the operation values.

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