JP4512285B2 - Video signal processing circuit and camera system - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a signal processing technique for converting an analog video signal output from a solid-state imaging device such as a CCD or CMOS sensor into a digital video signal, and in particular, a clamp that fixes the black level of the video signal to a predetermined DC value. Regarding technology.
[0002]
[Prior art]
When an analog video signal output from a solid-state image sensor is converted into a digital video signal by an analog / digital (A / D) converter, it is necessary to fix the black level in the analog video signal to a predetermined DC value. For this purpose, a clamp circuit is used. Normally, the black level of the analog video signal corresponding to the OB portion is fixed to a predetermined DC value by the clamp circuit using the signal in the light shielding portion (Optical Black: OB portion) of the solid-state image sensor as the black level reference. ing.
[0003]
Conventionally, an analog circuit has been used for this clamp circuit, but the analog circuit cannot control the time constant of the clamp according to the situation.
[0004]
However, a technique for solving this problem is disclosed in Japanese Patent Laid-Open No. 2000-224440, and a video signal processing circuit including a clamp circuit capable of controlling a time constant according to the situation has been proposed. The configuration is shown in FIG.
[0005]
In the configuration of FIG. 2, an analog video signal AVin is input to an analog video signal input terminal 201 from an imaging device (not shown) and supplied to a non-inverting input terminal (+) of a differential amplifier 202. The differential amplifier 202 functions as a part of the first clamp circuit by a DC voltage supplied from a digital / analog (D / A) converter 219 described later to the inverting input terminal (−). An output signal from the differential amplifier 202 is supplied to the variable gain amplifier 203, and its gain is variably controlled in accordance with a gain control signal GC input from the outside. Similar to the differential amplifier 202, the output signal of the variable gain amplifier 203 is supplied to the inverting input terminal (−) by a DC voltage supplied from a digital / analog (D / A) converter 215, which will be described later. The signal is input to the A / D converter 205 via the differential amplifier 204 functioning as a part of the circuit, converted into the digital video signal DVout, and sent from the digital video signal output terminal 206 to the subsequent digital video signal processing unit. Is output.
[0006]
The output signal of the A / D converter 205 is subjected to a difference calculation between the black level of the OB portion in the digital video signal and the reference value VR in the subtractor 207, and an error signal with respect to the reference value VR is output. The error signal from the subtracter 207 is supplied to the averaging circuit 208 and output in the horizontal direction, that is, averaged for a plurality of pixels. At this time, the averaging circuit 208 outputs an average error from the reference value VR of the black level corresponding to the OB portion and the pedestal level corresponding to the non-signal portion in the horizontal blanking period based on the averaging control signal AC. Is done.
[0007]
The output signal from the averaging circuit 208 is clipped by the clip circuit 209 to cut the excessive level to a predetermined level, and is averaged by the vertical integration circuit 210 in the vertical direction, that is, in a plurality of horizontal scanning line periods. The error signal from the vertical integration circuit 210 is input to one end of the adder 211. The other end of the adder 211 is a signal delayed by one horizontal scanning period (1H) by the clock signal HCLK2 in the 1H delay circuit 212. Is entered. Therefore, from the adder 211, the DC level of the current error signal and the DC level of the error signal added 1H before are cyclically added and output.
[0008]
The digital signal output from the 1H delay circuit 212 is converted to an analog signal level by the D / A converter 213 and fed back to the inverting input terminal (−) of the differential amplifier 204. That is, the differential amplifier 204 and a feedback circuit composed of a circuit from the output terminal to the inverting input terminal of the differential amplifier 204 constitute a first clamp circuit. The black level in the OB portion is compared with the reference value VR, and the feedback control is performed so that the error becomes 0, that is, the black level in the OB portion matches the reference value VR.
[0009]
The output signal from the clip circuit 209 is also supplied to the multiplier 214, multiplied by the gain k, and then input to one end of the adder 215. To the other end of the adder 215, a signal delayed by one vertical scanning period (1V) by the clock signal HCLK1 in the 1V delay circuit 216 is input. Therefore, the adder 215 cyclically adds and outputs the DC level of the current error signal and the DC level of the error signal added 1V before.
[0010]
The digital signal output from the 1V delay circuit 216 is converted to an analog signal level by the D / A converter 217 and fed back to the inverting input terminal (−) of the differential amplifier 202. In other words, the differential amplifier 202 and a feedback circuit composed of a circuit from the output terminal to the inverting input terminal of the differential amplifier 202 constitute a second clamp circuit. The level of the non-signal portion is compared with the reference value VR, and the feedback control is performed so that the error becomes 0, that is, the DC level of the non-signal portion matches the reference value VR.
[0011]
As described above, in the conventional video signal processing circuit, at the input of the variable gain amplifier 203, the second gain circuit is used to match the DC component level of the video signal with the reference value VR, whereby the gain is obtained by the variable gain amplifier 203. Even if the direct current component level is changed by changing, the output video signal level falls within the operation range of the variable gain amplifier 203.
[0012]
Also, at the input of the A / D converter 205, the first clamp circuit is used to match the black level of the video signal to the reference value VR, whereby the peak level of the video signal is A / D converted based on the black level. The full-scale input range of the unit 205 is included.
[0013]
[Problems to be solved by the invention]
In the conventional video signal processing circuit, when the analog video signal is converted into the digital video signal, the first clamp circuit configuration for fixing the black level of the video signal to a constant value and the DC component level of the video signal to a constant value Two circuit configurations, i.e., a second clamp circuit configuration to be fixed to the circuit, are required.
[0014]
In addition, since the clipping circuit 209 is used to clip the error between the black level or the DC component level and the reference value, if the clipping value is small, the feedback control loop converges when the error is large. If time is required and the clip value is large, the image is disturbed by the influence of noise. Therefore, it is necessary to set an optimum clip value for the clip circuit 209 according to the input analog video signal.
[0015]
The present invention has been made in view of the above-described problems, and an object of the present invention is to provide a video signal processing circuit capable of achieving a desired clamp characteristic with a simple circuit configuration and the same on a semiconductor substrate that is the same as an image sensor. It is to provide a configured camera system.
[0016]
[Means for Solving the Problems]
In order to achieve the above object, a video signal processing circuit according to the present invention is provided with a differential amplifier in which an analog video signal is input to one input terminal and gain is controlled by a control signal, and output from the differential amplifier. Calculates the difference between the A / D converter that converts the analog video signal to the digital video signal and the level of the predetermined part other than the effective signal part in the output signal of the A / D converter and the reference value, and outputs it as a digital error signal A subtractor that compares the level of the digital error signal with the threshold value and switches the coefficient to be multiplied by the digital error signal according to the comparison result, and the digital error signal output from the comparison operation unit is converted into an analog error. is converted into a signal, and a other supplies D / a converter to an input terminal of the differential amplifier, the video signal processing circuit, output from the subtracter Digi Comprising an averaging circuit for averaging the Le error signal over a plurality of pixels, the averaging circuit is characterized in that supplying the digital error signal obtained by averaging in the comparison operation unit.
[0017]
In this video signal processing circuit, the comparison operation unit sets the coefficient to a value larger than 1 when the level of the digital error signal is larger than the threshold, and sets the coefficient to 1 when the level of the digital error signal is equal to or smaller than the threshold. It is preferable to set to.
[0018]
In this case, the comparison operation unit compares the digital error signal with the threshold value. When the level of the digital error signal is equal to or lower than the threshold value, the comparison operation unit outputs the digital error signal from the first output terminal and outputs from the second output terminal. When the signal output is prohibited and the level of the digital error signal is larger than the threshold value, the signal output from the first output terminal is prohibited and the digital error signal is output from the second output terminal; It is preferable that a multiplier for multiplying the digital error signal output from the two output terminals by a coefficient larger than 1 is provided, and the first output terminal of the comparator and the output terminal of the multiplier are connected.
[0019]
Alternatively, the comparison operation unit sets the coefficient to 1 when the level of the digital error signal is equal to or lower than the threshold value as a result of comparison by the comparator that compares the digital error signal and the threshold value, and the digital error signal It is preferable to provide a multiplier for setting the coefficient to a value larger than 1 when the level is larger than the threshold.
[0021]
The video signal processing circuit according to the present invention adds a delay circuit that delays an input signal by one horizontal scanning period, an output signal from the comparison operation unit, and an output signal from the delay circuit, and It is preferable that an adder to be supplied to the input terminal is provided, and an output signal of the delay circuit is supplied to the D / A converter.
[0022]
In order to achieve the above object, a camera system according to the present invention is characterized in that the video signal processing circuit according to the present invention and an image sensor for outputting an analog video signal are configured on the same semiconductor substrate. .
[0023]
According to the above configuration, in the clamp circuit configuration including one feedback loop, the time constant of the feedback system is switched according to the fluctuation of the DC component level of the video signal, and the pedestal level of the non-signal portion and the OB portion of the video signal are switched. Both the black level and the reference value can be fixed. This makes it possible to achieve desired clamping characteristics with a simple circuit configuration.
[0024]
Further, by using the video signal processing circuit according to the present invention, a DC direct connection circuit from the solid-state imaging device can be configured, and the CMOS sensor and the video signal processing circuit can be arranged on the same silicon substrate. A chip camera system can be realized.
[0025]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings.
[0026]
FIG. 1 is a block diagram showing a configuration of a video signal processing circuit according to an embodiment of the present invention.
[0027]
In FIG. 1, 101 is an analog video signal input terminal, 102 is a differential amplifier, 103 is an A / D converter, 104 is a digital video signal output terminal, 105 is a subtractor, 106 is an averaging circuit, 107 is a comparator, 108 is a multiplier, 109 is an adder, 110 is a delay circuit, and 111 is a D / A converter. The comparator 107 and the multiplier 108 constitute a comparison operation unit.
[0028]
Next, the operation of the video signal processing circuit configured as described above will be described.
[0029]
The analog video signal S101 input from the video signal input terminal 101 includes an effective signal portion that includes a video signal and a horizontal blanking period that does not include the video signal. The horizontal blanking period is composed of an OB portion serving as a reference for the black level and a non-signal portion.
[0030]
The analog video signal S101 is input to the non-inverting input terminal (+) of the differential amplifier 102, and the analog video signal S102 amplified by a predetermined gain (1 + R1 / R2) is input to the A / D converter 103. . Here, a DC voltage S114 is applied to the inverting input terminal (−) of the differential amplifier 2 through a resistor R2 from a D / A converter 111, which will be described later, and this is subtracted from the analog video signal S101 to obtain a differential. Output from the amplifier 102.
[0031]
The analog video signal S102 is converted into a digital video signal S103 by the A / D converter 103 and output from the digital video signal output terminal 104 to the subsequent digital video signal processing unit.
[0032]
The output signal S103 of the A / D converter 103 is subjected to a difference operation between the black level of the OB portion in the digital video signal and the reference value S104 (VR) in the subtractor 105, and an error signal S105 with respect to the reference value S104. Is output. The error signal S105 from the subtractor 105 is supplied to the averaging circuit 106, and is output by taking an average of, for example, 8 pixels in the horizontal direction. By taking an average of several pixels in this way, noise components are averaged, and the influence on the image can be reduced.
[0033]
The output signal S106 of the averaging circuit 106 is supplied to one input terminal of the comparator 107 and compared with a threshold value S107 (VT) supplied to the other input terminal. From the comparator 107, when the level of the input signal S106 is equal to or lower than the threshold value S107, the second output terminal 1072 of the comparator 107 is in a high impedance state, and the input signal S106 is directly output from the first output terminal 1071. It is output to one end of the adder 109 as S108. On the other hand, when the level of the input signal S106 is larger than the threshold value S107, the first output terminal 1071 of the comparator 107 has a high impedance, and the input signal S106 is output from the second output terminal 1072 to the multiplier 108 as the output signal S109. Is done. The multiplier 108 multiplies the signal S109 by the coefficient k and outputs the signal S110 to one end of the adder 109. Therefore, the output signal S108 from the first output terminal of the comparator 107 or the output signal S110 from the multiplier 108 is supplied to one end of the adder 109.
[0034]
The other end of the adder 109 is supplied with a signal S112 that is delayed by one horizontal scanning period (1H) by the clock signal HCLK in the 1H delay circuit 110 configured by, for example, a D-type flip-flop. Therefore, from the adder 109, the DC level of the current error signal S108 or S110 and the DC level of the error signal S113 added 1H before are cyclically added and output as clamp voltage correction data S111. .
[0035]
The digital signal S112 output from the delay circuit 110 is converted into an analog signal S113 by the D / A converter 111 and input to the inverting input terminal (−) of the differential amplifier 102 via the resistor R2.
[0036]
As described above, in the present embodiment, the black level of the OB portion in the video signal is monitored for each horizontal scanning period, an error from the reference value is detected, and the clamp voltage is corrected thereby, thereby correcting the black level. Fix to the reference value. At this time, a threshold value VT is provided for the error, and for an error larger than the threshold value VT, the gain of the feedback loop is increased via the multiplier 108 to increase the correction amount, thereby obtaining the error reference value VR. The convergence speed can be improved.
[0037]
Here, the state where the error is larger than the threshold value VT is a case where the DC component level of the analog video signal fluctuates greatly, such as when the power is turned on or when the signal gain is varied. The changed DC component level can be immediately fixed to the reference value VR.
[0038]
Further, in a state where the error is equal to or less than the threshold value VT, it is desirable to set the threshold value VT so as to cover the fluctuation range of the black level in order to reliably fix the black level of the video signal to the reference value VR.
[0039]
In the present embodiment, the output terminals of the comparator 107 are separately provided as the first output terminal 1071 and the second output terminal 1072, and the coefficient k is set by the multiplier 108 for the output signal S109 from the second output terminal 1072. However, the present invention is not limited to such a configuration. For example, the comparison result of the comparator 107 is supplied to the multiplier 108, and the coefficient k of the multiplier 107 is input to the input signal S106, and the input signal S106 is a threshold value. It can also be handled by setting it to a value greater than 1 if it is greater than VT, and setting it to 1 if the input signal S106 is less than or equal to the threshold value VT.
[0040]
【The invention's effect】
As described above, according to the present invention, with a clamp circuit configuration composed of one feedback loop, the time constant of the feedback system is switched according to the fluctuation of the DC component level of the video signal, and the pedestal of the no-signal part in the video signal Both the level and the black level of the OB portion can be fixed to the reference value. This makes it possible to achieve desired clamping characteristics with a simple circuit configuration.
[0041]
In addition, by using the video signal processing circuit of the present invention, a DC direct connection circuit from a solid-state imaging device can be configured, and a CMOS sensor and a signal processing circuit can be arranged on the same silicon substrate. A system can be realized.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of a video signal processing circuit according to an embodiment of the present invention. FIG. 2 is a block diagram showing a configuration of a conventional video signal processing circuit.
101 Analog Video Signal Input Terminal 102 Differential Amplifier 103 A / D Converter 104 Digital Video Signal Output Terminal 105 Subtractor 106 Averaging Circuit 107 Comparator (Comparison Operation Unit)
1071 First output terminal 1072 of the comparator 107 Second output terminal 108 of the comparator 107 Multiplier (comparison operation unit)
109 Adder 110 1H Delay Circuit 111 D / A Converter VR Reference Value VT Threshold HCLK Clock Signal

Claims (11)

A differential amplifier in which an analog video signal is input to one input terminal and the gain is controlled by a control signal;
An A / D converter for converting an analog video signal output from the differential amplifier into a digital video signal;
A subtractor that calculates a difference between a level of a predetermined portion other than an effective signal portion in the output signal of the A / D converter and a reference value, and outputs the difference as a digital error signal;
A comparison operation unit that compares the level of the digital error signal with a threshold value, and switches a coefficient to be multiplied by the digital error signal according to the comparison result;
A D / A converter that converts the digital error signal output from the comparison operation unit into an analog error signal and supplies the analog error signal to the other input terminal of the differential amplifier ;
The video signal processing circuit includes an averaging circuit that averages the digital error signal output from the subtractor over a plurality of pixels, and the averaging circuit outputs the averaged digital error signal to the comparison operation unit. A video signal processing circuit characterized by being supplied .   The comparison operation unit sets the coefficient to a value greater than 1 when the level of the digital error signal is greater than the threshold, and sets the coefficient to 1 when the level of the digital error signal is equal to or less than the threshold. The video signal processing circuit according to claim 1, wherein The comparison operation unit
The digital error signal is compared with the threshold value. When the level of the digital error signal is equal to or lower than the threshold value, the digital error signal is output from the first output terminal and the signal output from the second output terminal is output. A comparator that inhibits signal output from the first output terminal when the level of the digital error signal is greater than the threshold, and outputs the digital error signal from the second output terminal;
A multiplier for multiplying the digital error signal output from the second output terminal of the comparator by a coefficient larger than 1,
2. The video signal processing circuit according to claim 1, wherein a first output terminal of the comparator is connected to an output terminal of the multiplier. The comparison operation unit
A comparator for comparing the digital error signal and the threshold;
As a result of the comparison by the comparator, if the level of the digital error signal is less than or equal to the threshold, the coefficient is set to 1. If the level of the digital error signal is greater than the threshold, the coefficient is set to be less than 1. 2. The video signal processing circuit according to claim 1, further comprising a multiplier for setting a large value. The video signal processing circuit includes:
A delay circuit for delaying an input signal by one horizontal scanning period;
An adder that adds the output signal from the comparison operation unit and the output signal from the delay circuit and supplies the signal to the input terminal of the delay circuit;
The video signal processing circuit according to any one of claims 1 to 4, the output signal is characterized in that it is supplied to the D / A converter of said delay circuit. A differential amplifier in which an analog video signal is input to one input terminal and the gain is controlled by a control signal;
An A / D converter for converting an analog video signal output from the differential amplifier into a digital video signal;
A subtractor that calculates a difference between a level of a predetermined portion other than an effective signal portion in the output signal of the A / D converter and a reference value, and outputs the difference as a digital error signal;
A comparison operation unit that compares the level of the digital error signal with a threshold value, and switches a coefficient to be multiplied by the digital error signal according to the comparison result;
A video signal processing circuit including a D / A converter that converts the digital error signal output from the comparison operation unit into an analog error signal and supplies the analog error signal to the other input terminal of the differential amplifier;
A camera system, wherein the video signal processing circuit and the image sensor for outputting the analog video signal are configured on the same semiconductor substrate. The comparison operation unit sets the coefficient to a value greater than 1 when the level of the digital error signal is greater than the threshold, and sets the coefficient to 1 when the level of the digital error signal is equal to or less than the threshold. The camera system according to claim 6, wherein the camera system is set as follows. The comparison operation unit
The digital error signal is compared with the threshold value. When the level of the digital error signal is equal to or lower than the threshold value, the digital error signal is output from the first output terminal and the signal output from the second output terminal is output. A comparator that inhibits signal output from the first output terminal when the level of the digital error signal is greater than the threshold, and outputs the digital error signal from the second output terminal;
A multiplier for multiplying the digital error signal output from the second output terminal of the comparator by a coefficient larger than 1,
The camera system according to claim 6, wherein a first output terminal of the comparator is connected to an output terminal of the multiplier. The comparison operation unit
A comparator for comparing the digital error signal and the threshold;
As a result of the comparison by the comparator, if the level of the digital error signal is less than or equal to the threshold, the coefficient is set to 1. If the level of the digital error signal is greater than the threshold, the coefficient is set to be less than 1. The camera system according to claim 6, further comprising a multiplier that sets a large value. The video signal processing circuit includes an averaging circuit that averages the digital error signal output from the subtractor over a plurality of pixels, and the averaging circuit outputs the averaged digital error signal to the comparison operation unit. The camera system according to claim 6, wherein the camera system is supplied. The video signal processing circuit includes:
A delay circuit for delaying an input signal by one horizontal scanning period;
An adder that adds the output signal from the comparison operation unit and the output signal from the delay circuit and supplies the signal to the input terminal of the delay circuit;
The camera system according to claim 6, wherein an output signal of the delay circuit is supplied to the D / A converter .

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