JP4643376B2 - Multi-value storage means, multi-value transfer gate means, multi-value synchronous latch means and multi-value synchronous signal generating means - Google Patents

Description

  The first invention has three or more memorable numerical values (or meanings or contents), can hold or input / output voltage or potential according to the numerical values, etc. The present invention relates to multi-value storage means that is not provided with an output terminal independently. For this reason, this multi-value storage means reads out the magnitude of the write input current of the stored content as in “Static type multi-value storage means having only input / output means (eg, input / output terminals) having common input / output”. It is not influenced by the output current capacity, and there is no need to provide a separate reading means such as a sense amplifier for reading unlike the binary capacitor type DRAM. Therefore, the first invention can be used as a multi-value memory cell, multi-value memory, multi-adic memory cell, multi-adic memory or multi-stable circuit, but if the multi-value transfer gate means is connected to the previous stage, Multi-level synchronous latch means ”can be configured. In the case of multi-values, unlike binary, the name of flip-flop having only two stable states is not appropriate, and will be referred to as “multi-value synchronous latch means” hereinafter.

The second invention relates to a multi-value transfer gate means that can cope with a multi-value synchronization signal waveform such as a staircase waveform (eg, FIG. 4) combining an up-stairs and a down-stairs. In a conventional rectangular wave binary synchronization signal, only two timings such as switching can be taken at the rising edge and the falling edge of the synchronization signal. On the other hand, if the multi-level synchronization signal has a staircase waveform, for example, since there are a plurality of rising points and falling points in one cycle or in a single waveform, the timing of switching and the like can be diversified. spread.
The third invention relates to a multi-value synchronous latch means in which a multi-value transfer gate means is connected to an inlet means (eg, an input terminal) of the multi-value storage means of the first invention. Of course, the multi-value transfer gate means of the second invention can be used as a component of the third invention.
The fourth invention relates to a multi-level synchronization signal generating means for digitally generating a staircase waveform (eg, FIG. 4) combining an upstairs and a downstairs. Less power loss than analog type.
Each invention includes a multi-value (or multi-adic) logic circuit, a multi-value (or multi-adic) arithmetic circuit, a multi-value computer (or a multi-adic computer, particularly 4, 8, “10”, 16, 32, 64 , "100", 128 base computer), multi-value (or multi-base) modulation communication means, multi-value (or multi-base) recording means or multi-value (or multi-base) control means. .

Background art of the first invention

An example of the multi-value storage means disclosed in Japanese Patent Laid-Open No. 2005-116168 is shown in the left half of FIG. Since this multi-value storage means is a "multi-value storage means in which the input and output terminals of the multi-value buffer means shown in the right half of FIG. 2 are connected and the input / output terminals are common", the input current at the time of writing the stored contents Is affected by the read output current capacity. When the output current capacity is large, there is no need to change the memory contents or read errors when reading the memory contents due to the charge of the data line connected to the input / output terminal or the drive current of the connected transistor. It is necessary to increase the input current during writing. Even if the write input current is reduced, the read operation such as the sense amplifier used in the binary capacitor type DRAM is used carefully so that the stored contents do not change, or the read operation is performed again after the read. Need to do. In this first solution, as shown in FIG. 2, the input / output terminal of the multi-value storage means and the input terminal of the multi-value buffer means are connected, and a new output terminal Out is provided. The input terminal In and the output terminal Out are independent. There is a way to separate them. However, this improved multi-value storage means has a problem that “the number of parts is large and the configuration becomes complicated”. (First problem)
The input terminal In is connected to all input terminals of the binary NOT means group of the multi-value storage means before improvement and all input terminals of the binary NOT means group of the multi-value buffer means. The multi-value storage means has a problem that “input capacitance or input current is doubled”. (Second problem)
This means that in the case of multi-value storage means using an insulated gate transistor (eg, MOS / FET, IGBT, etc.), the capacitive load (the total gate-source capacitance, etc.) is doubled for the previous stage. Therefore, the power consumption associated with the charging / discharging is doubled, and the rising speed and falling speed of the input signal are reduced. In the case of multi-value storage means using a bipolar transistor or the like, the power consumption due to the total driving current twice is naturally doubled.

Then, as a second solution, the input of the ternary buffer means as in “Static type ternary storage means from which the transfer gate means GA1 is removed in the circuit of FIG. 3 (disclosed in Japanese Patent Application Laid-Open No. 2005-80258)”. The transfer gate means GA2 is connected between the terminal and the output terminal, the transfer gate means GA2 is turned off at the time of writing and the write signal is inputted from the input terminal, while the transfer gate means GA2 is turned on and outputted at the time of reading. There is a method of outputting a read signal from a terminal. However, when the transfer gate means GA2 is switched on / off, the stored contents are held by the charge charges of several gate-source capacitances of the input side MOS / FETs which are constituent elements thereof.
However, the above-mentioned “ternary storage means from which the transfer gate means GA1 is removed in the circuit of FIG. 3” and “similarly, the transfer gate means is connected to the multi-value buffer means in the right half of FIG. "Multi-value storage means that do not do" says "the synchronization signal (eg, clock pulse, single pulse, etc.) and the synchronization signal line for controlling the transfer gate means is always required for the multi-value storage operation" There is a problem. (Third problem)
This means that the write and read timings are limited to the rising and falling edges of the synchronization signal, and the write and read operations must be waited until the rise and fall times. Connected.
JP-A-2005-80258 (3-value storage means and 3-value synchronous latch means) JP-A-2005-116168 (multi-value storage means of the present inventor) JP 2004-88763 (same as above) Japanese Patent Application No. 2005-75909 (same as above) Japanese Patent Application No. 2005-109163 (same as above)

Disclosure of the first invention

Problems to be solved by the first invention

Therefore, the conventional circuit has the following six problems.
a) The number of parts is large and the configuration is complicated.
b) Input capacitance or input current is doubled.
c) Power consumption increases due to the doubling of the input capacitance or input current.
d) In the multi-value storage means using the insulated gate type switching means, the rising speed and falling speed of the input signal become slow due to the doubling of the input capacitance. In other words, operation delay.
e) A synchronizing signal and a synchronizing signal line are always necessary for the multi-value storing operation (writing and reading).
f) Write timing and read timing are limited due to the synchronous operation, and there is a circuit operation delay due to timing adjustment.
(Task)
Therefore, the first invention aims to provide a multi-value storage means that can solve the above-mentioned problems, that is, the six problems a) to f). (Object of the first invention)

Means for solving the problem of the first invention

  That is, the first invention is the multivalue storage means described in claim 1. When the multi-value storage means and the multi-value buffer means as the constituent means are combined to constitute the multi-value storage means of the first invention, the former input potential discrimination means and the latter input potential discrimination means are used in common. In summary, one input potential discrimination means is saved.

Effects of the first invention

This saves one input potential discriminating means that doubles the input capacitance or input current, so that the number of parts can be reduced and the configuration can be simplified. In the case of multi-value storage means using an insulated gate type switching means, the input signal rise speed or fall speed Can be suppressed.
In addition, since the transfer gate means is not required as the configuration means, no synchronization signal or synchronization signal line is required for the multi-value storage operation (write, read), the write timing and the read timing are not limited, and each timing is limited. There is no delay in circuit operation.

Background Art of the Second Invention

Until now, there has been no multi-value transfer gate means that is optimal for multi-value (or multi-adic) circuits and means. For example, in the circuit of FIG. 3 (disclosed in Japanese Patent Application Laid-Open No. 2005-80258), both transfer gate means GA1, using a rectangular-wave synchronization signal (eg, clock pulse, single pulse, etc.), GA2 is controlled. In this case, only two timing points can be taken during the one period or single pulse period, that is, the rising point and the falling point of the rectangular wave synchronization signal. This is because a multi-level sync signal waveform suitable for a multi-level (or multi-ary) circuit has not yet been proposed. Here, the present inventor proposes, for example, a multilevel synchronization signal (six values of potentials v0 to v5) of “a staircase waveform combining the upstairs and the downstairs shown in FIG. 4” as an example of the multilevel synchronization signal. Of course, it is not limited to six values. In this multilevel synchronization signal having a staircase waveform, there are a number of rising and falling points in one cycle, and any time (when rising or falling) may be used as the turn-on point of the multilevel transfer gate means. )), The switching timing of the multi-value transfer gate means, the ON period, the OFF period, etc., depending on which time (either rising or falling) may be used as the turn-off time. Since it can be diversified, it leads to an increase in the width of switching control and, in turn, an increase in the width of logic processing / design methods and a reduction in processing time. Therefore, there is a need for multi-level transfer gate means that can cope with such multi-level sync signals.
JP-A-2005-80258 (3-value storage means and 3-value synchronous latch means)

Disclosure of the second invention

Problems to be solved by the second invention

The conventional problem is that "the switching timing, on-period, and off-period are diversified in conformity with the new multi-level synchronization signal proposed by the present inventor (eg, periodic or single step wave). It is desirable to have a multi-value transfer gate means capable of. (Task)
In view of this, the second aspect of the invention is to provide multi-level transfer gate means that can be adapted to a new multi-level synchronization signal and can be diversified in switching timing, on period or off period. (Object of the second invention)

Means for solving the problem of the second invention

  That is, the second invention is the multi-value transfer gate means described in claim 2. The staircase-shaped synchronization signal is “one period or a plurality of periods in succession in the period of the horizontal portion of the (N−1) -th potential sequentially from the period of the horizontal portion of the second potential of the staircase wave”. "On / off drive means controlled by the synchronization signal potential determination means" drives the bidirectional switching means on and off when there is no, or on / off drive opposite to it. To do. In order to determine the “start time or end time” of the “on or off”, the potential of the synchronization signal is “based on the first specific potential from the second potential to the (N−1) th potential. The negative side on / off threshold potential is the same as “the negative side on / off threshold potential”, and “the positive side on / off with reference to the second specific potential of the (N−1) th potential from the first specific potential”. The synchronization signal potential discriminating means discriminates whether or not it is the same as the “threshold potential”.

Effects of the second invention

  As a result, the “start time or end time” of “the“ on or off ”” and “on period and off period” options are increased in conformity with the staircase-shaped synchronization signal, and thus the second invention has many options. The value transfer gate means can be adapted to a new multi-level synchronization signal, and can have a wide variety of switching timings, on periods, and off periods. 』

Background art of the third invention

  As a matter of course, there has never been a multi-value synchronous latch means using the multi-value storage means of the first invention. If such a multi-level synchronous latch means is provided, the advantages of the first invention can be utilized. As described above, in the case of multi-value, unlike the case of binary, the name “flip-flop having only two stable states” is not suitable, so the name “multi-value synchronous latch means” is adopted.

Disclosure of the third invention

Problems to be solved by the third invention

Therefore, the problem is that "multi-level synchronous latch means utilizing the multi-value storage means of the first invention is desired". (Task)
In view of this, the third aspect of the present invention aims to provide a “multi-level synchronous latch unit using the multi-level storage unit of the first aspect”. (Object of the third invention)

Means for solving the problem of the third invention

That is, the third invention is the multilevel synchronous latch means according to the third aspect. As the preceding stage of the multi-value storage means of the first invention, the multi-value transfer gate means or the multi-value transfer gate means described in claim 2 is connected.
Thus, while the connected multi-value transfer gate means is on, the input signal of the connected multi-value transfer gate means is directly input to the multi-value storage means, and the contents of the input signal are stored in the multi-value storage. Written in the means. However, while the connected multi-value transfer gate means is off, the multi-value storage means keeps the contents written before the turn-off, no matter how the contents of the input signal change.

Effects of the third invention

  As a result, “the multi-value synchronous latch means of the third invention can be a multi-value synchronous latch means using the multi-value storage means of the first invention. 』

Background art of the fourth invention

For example, as shown in FIG. 4, there has conventionally not been a multi-level synchronization signal generating means for digitally generating a staircase waveform combining an upstairs and a downstairs (using a digital concave path). However, it is not limited to 6 values. It is 3 or more.
Note that a conventional staircase wave generation circuit that generates an analog staircase wave using an operational amplifier or the like exists in the pulse circuit field, but naturally power loss increases. Also, the power supply must have a high voltage accuracy dedicated to the analog circuit. Further, in order for the analog staircase wave generation circuit to output the lowest potential v0 and the highest potential v5, for example, the analog power supply potential needs to be able to supply a power supply potential lower than the lowest potential v0 and a power supply potential higher than the highest potential v5. Therefore, it is necessary to increase the types of power supply potentials and voltages, which increases the number of parts and increases costs.
"Introduction to Transistor Circuits 4 Pulse Circuit Concept" published by OHM Co., Ltd. on February 20, 1985. p. 131-p. 132. “Bootstrap staircase wave generation circuit”. Supervised and written by Yoshifumi Amemiya and others.

Disclosure of the fourth invention

Problems to be solved by the fourth invention

Therefore, the problem is that “multi-level synchronization signal generating means that digitally generates a staircase waveform combining an upstairs and a downstairs (using a digital circuit) is desired”.
(Task)
In view of this, the fourth aspect of the present invention aims to provide "multi-level synchronization signal generating means for digitally generating a staircase waveform combining an upstairs and a downstairs (using a digital circuit)". (Object of the fourth invention)

Means for Solving the Problems of the Fourth Invention

  That is, the fourth invention is the multilevel synchronization signal generating means according to the fifth aspect. Prepare a binary counter that repeatedly outputs the same number of counter signals in the same order as the total number of horizontal parts of the staircase waveform combining the up and down staircases. One-to-one correspondence. Specifically, an on / off driving means that operates in accordance with the counter signals is prepared. Further, between each of the first potential supply means to the Nth potential supply means (for example, N power supply lines having different potentials) and “exit means (for example, output terminal) for outputting a multilevel synchronization signal therefrom” "Pull means for pulling up or pulling down" are connected one by one. Further, the on / off drive means only drives the pull means that pulls up or down the potential of the exit means to “the potential of the horizontal portion of the staircase waveform corresponding to the output counter signal”. All the remaining pull means are driven off. As a result, the potential of the multi-level synchronization signal rises or falls stepwise according to the different counter signals output in sequence.

Effects of the fourth invention

  As a result, the potential of the multi-level synchronization signal output in accordance with the different counter signals output in sequence rises or falls in a staircase pattern. A staircase waveform combining downstairs can be generated digitally (using a digital circuit).

The best mode for carrying out each invention

  In order to explain each invention in more detail, these will be described with reference to the accompanying drawings. Note that the potential of the power supply line V0 is represented by the potential v0, the potential of the power supply line V1 is represented by the potential v1, and thereafter, similarly, the potential v2 to the potential v (n1-1) from the power supply line V2 to the power supply line V (n-1). ). Further, the potential increases in order from the potential v0 to the potential v (n-1).

The embodiment 1 shown in FIG. 1 is a five-value multivalue storage means, and N described above is 5. The constituent means in FIG. 1 correspond to the constituent means in Claim 1 as follows.
a) The potential v0 to the potential v4 are sequentially changed from the first potential to the Nth potential in the same paragraph.
b) The power supply line V0 to the power supply line V4 are sequentially supplied to the first potential supply means to the Nth potential supply means in the same paragraph.
c) The input terminal 1n and the output terminal Out are respectively connected to the inlet means and the outlet means described in the same paragraph.
d) Three rows of MOS / FETs are arranged in the vertical direction in FIG. 1, but the “connected body of the first MOS / FET row from the left in FIG. 1” is the input potential discrimination means described in the same paragraph.
e) “Non-four power supply lines V0 to V4, one binary NOT means that is not provided for each of two power supply lines adjacent to each other by number” in the same paragraph. To binary NOT means.
f) “Similarly, a connection body of eight MOS • FETs and six diodes in the center row in FIG. 1” is the first pull means group in the same paragraph.
g) “Similarly, a connection body of eight MOS · FETs and six diodes in the first column from the right in FIG. 1” is the second pull means group in the same paragraph.

  However, the “diode / NMOS / FET series circuit” and the “PMOS / FET / diode series circuit” connected to the power supply line V1 in the central row in FIG. Are connected in parallel, and this parallel circuit functions as a substantially bidirectional pulling means. For this reason, the inventor regards this parallel circuit as one pulling means. Similarly, the same bidirectional pull means is connected to each of the power supply lines V2 to V3. Similarly, in the first column from the right in FIG. 1, “diode / NMOS / FET series circuit” and “PMOS / FET / diode series circuit” connected to the power source line V1 The power supply line V1 and the output terminal Out are connected in parallel, and this parallel circuit substantially functions as a bidirectional pull means. For this reason, the inventor regards this parallel circuit as one pull means. Similarly, the same bidirectional pull means is connected to each of the power supply lines V2 to V3.

  As described above, three rows of MOS / FETs are arranged in the vertical direction in FIG. 1, but when eight MOS / FETs and six diodes in the first row from the right are removed, the circuit of FIG. Conventional multi-value storage means having a terminal (= input terminal In) (contrast: circuit in the left half of FIG. 2) ”. Further, when eight MOS · FETs and six diodes in the center column are removed, the circuit of FIG. 1 becomes multi-value buffer means (contrast: circuit on the right half of FIG. 2). Further, when the input terminal (= input terminal In) and the output terminal (= output terminal Out) of the multi-value buffer means are connected, the multi-value buffer means becomes the same as the conventional multi-value storage means. Therefore, in the embodiment of FIG. 1, in other words, when the conventional multi-value storage means and the multi-value buffer means are combined, both of the input potential discrimination means (four binary NOT means on the left side of FIG. 1 are connected). Are multi-value storage means that saves one input potential determination means.

As a result, the following effects were produced when the output terminal Out was separated and independent from the input terminal In.
a) Since one input potential discriminating means can be saved, “the number of parts is small and the configuration is simple. 』
b) By saving one input potential discriminating means, “the input capacitance and the input current (the charge / discharge current of the total gate-source capacitance) are not doubled and remain as they are. 』
c) “There is no increase in power consumption due to doubling of input capacitance and input current. 』
d) Since the input capacitance does not double and remains as it is, “the rising speed and falling speed of the input signal do not slow down. That is, there is no operation delay. 』
e) Since the multi-value transfer gate means is not yet used in the stage of the first invention, “there is no need for a sync signal or sync signal line for the multi-value storage operation (write, read). 』
f) Since no synchronization signal is required for the multi-value storage operation, “the timing for writing and reading is not limited for the synchronization operation, and there is no circuit operation delay due to timing adjustment. 』

  All MOS FETs are normally-off type, ie, enhancement mode FETs. The back gate of each PMOS • FET is connected to its source or “power supply line having a potential higher than its source potential”, while the back gate of each NMOS • FET is connected to its source or “power supply having a potential lower than its source potential”. Connected to the "line". In addition, each diode prevents the CMOS memories that are vertically related to each other from short-circuiting each power supply (not shown; between two power supply lines). Junction and various diode means such as “bipolar transistor with its collector and base directly connected”, “junction FET with its drain and source directly connected”, “bipolar mode SIT or GTBT with its drain and gate directly connected” "Normally-off type MOS FET with its gate, back gate and source connected", "Normally off type or on-type MOS FET with its gate and back gate, source and drain connected" or " Make sure that the back and back gates and the back and back gates do not conduct. Over the door to keep the potential, the drain and gate Nomaryi-off type MOS · FET connected the "can be used one at a time. Furthermore, if the on-drive voltage polarity is the same as that of each MOS • FET, a normally-off voltage-driven switching means (eg, IGBT) can be used one by one, and the on-drive voltage polarity is in each direction. If it is the same as the controllable switching means (each series circuit of MOS • FET and diode), one-way IGBT etc. can be used one by one instead.

  In the second embodiment shown in FIG. 5 (first invention), each of the unidirectional controllable switching means includes “a normal switching operation MOS-FET and a diode-like unidirectional switching action (reverse blocking action) MOS-FET. One series circuit is used at a time. Each MOS-FET that connects the back gate and source is responsible for a unidirectional switching action like the diode, and the source and drain have their functions switched depending on the applied voltage direction. The PN junction may function as a built-in diode. However, in order to reduce the ON voltage of each series circuit as much as possible, the MOS / FET of the normal switching operation is connected between the source and gate of the MOS / FET of the unidirectional switching action. For each back gate whose connection is not shown in FIG. 5, the back gate of each PMOS • FET is connected to its source or power line V3, while the back gate of each NMOS • FET is its source or power line. Connected to V0. Further, regarding the back gate of each MOS • FET that connects the back gate and the source, the back gate of each PMOS • FET may be reconnected from the source to the power supply line V3, or the back gate of each NMOS • FET may be connected to the source. May be reconnected to the power supply line V0. These back gate connections and connection changes can also be applied to Examples 3 and 4 described later.

  In the third embodiment shown in FIG. 6 (first invention), the MOS / FET having a unidirectional switching action is connected to the source side of the MOS / FET having a normal switching operation, but the former is turned on when the latter is turned off. Since both are on in both directions, the former does not prevent the latter off driving.

  In Example 4 (first invention) shown in FIG. 7, in order to further reduce the ON voltage of “each series circuit of MOS • FET of normal switching operation and MOS • FET of unidirectional switching action (reverse blocking action)” Each MOS / FET having a unidirectional switching action is actively turned on / off. Specifically, the “three connected NOT NOT elements in the first column from the left in FIG. 7” drives the reverse blocking MOS • FET on and off together with the normal operation MOS • FET.

The fifth embodiment shown in FIG. 8 (first invention) is “change from the four-value storage to the six-value storage in the fourth embodiment of FIG. 6-value storage means that achieves simplification of the above. " In the fourth embodiment shown in FIG. 7, the “series circuit of reverse blocking MOS • FET and normal switching MOS • FET” functions as bidirectional switching means. Therefore, the power supply lines V1 and V2 have “both performing the same function”. Two "MOS / FET series circuits" are connected to each other, and the same configuration is full.
Note that the back gate of each of the five MOS • FETs in the binary NOT means 5 in the first column from the left in FIG. 8 is connected to the source or “power supply line having a potential higher than the source potential”. On the other hand, the back gate of each NMOS • FET is connected to its source or “power supply line having a potential lower than its source potential”. As for the back gates of other “each MOS • FETs that connect the back gate and the source”, the back gate of the PMOS • FET may be reconnected from the source to the power supply line V5, or the back gate of the NMOS • FET may be connected. The source may be reconnected to the power supply line V0. The connection and connection change of these back gates can be similarly applied to the above-described fourth embodiment.

  The sixth embodiment (second invention) shown in FIG. 9 corresponds to the multi-value transfer gate means described in claim 2, and m is a predetermined integer satisfying the condition of 5> m> 0. Further, the first and second specific potentials in claim 2 are the same potential (= potential vm of power supply line Vm), and “connected body of three MOS • FETs grounded to power supply line Vm and one resistor” is claimed. This corresponds to the synchronization signal potential determination means in 2. Further, “PMOS • FET and NMOS • FET connected in parallel between the input terminal In and the output terminal Out” corresponds to the bidirectional switching means according to claim 2, and “the remaining MOS • FET, diode And the resistor connection body ”correspond to the on / off driving means in claim 2. For example, “multilevel synchronization signal shown in FIG. 4” is input from the synchronization signal input terminal SSin from, for example, “synchronization signal output terminal SSout of the multilevel synchronization signal generating means shown in both FIGS. .

In the multilevel transfer gate means of the sixth embodiment of FIG. 9, the potential of the multilevel synchronization signal is between “a positive on / off threshold potential and a negative on / off threshold potential based on the potential vm”. When the above-mentioned synchronization signal potential determining means determines that it is in the position, "the above-mentioned on / off driving means operating according to this discrimination output signal" drives the above-mentioned bidirectional switching means on. However, when the synchronization signal potential determining means determines that there is no interval, the on / off driving means drives the bidirectional switching means off.
The positive side on / off threshold potential is determined by the potential vm and the “on / off threshold voltage of the PMOS FET whose gate is grounded to the power supply line Vm”. Is determined by the potential vm and the “on / off threshold voltage of the PMOS FET whose source is grounded to the power supply line Vm”. In addition, when the gate signals of “PMOS • FET and NMOS • FET that are not connected in parallel between the input terminal In and the output terminal Out” are interchanged with each other, the potential of the multilevel synchronization signal is between the above threshold potentials. When it is present, the bidirectional switching means is driven off, and when it is not between, it is turned on, and the on driving and off driving are switched in opposite directions. The fact that “when both gate signals are switched with each other, the on drive and the off drive are switched in the opposite direction” is the same in the seventh to ninth embodiments (FIGS. 10 to 12) and the multi-value transfer gate means of FIG. Is true. Furthermore, since the multilevel synchronization signal of the staircase wave has an up step and a down step, there are two ON periods in one cycle or a single pulse.

  The multi-value transfer gate means of the seventh embodiment (second invention) shown in FIG. 10 uses a synchronizing signal potential discriminating means different from that of the sixth embodiment of FIG. The “connected body of three connected MOS • FETs and one resistor” corresponds to the synchronizing signal potential determining means in claim 2. When k = m + 2, the synchronization signal potential determination means indicates that the potential of the multi-level synchronization signal is “a positive on / off threshold potential and a negative on / off threshold potential with reference to potential v (m + 1)”. To determine if it is between. Therefore, the on / off threshold voltage of the PMOS / FET grounded to the power supply line Vk, that is, the power supply line V (m + 2) is large and is set slightly smaller than the potential difference between the potential v (m + 2) and the potential v (m + 1). . On the other hand, the on / off threshold voltage of the NMOS / FET grounded on the power supply line Vm is also large and is set slightly smaller than the potential difference between the potential v (m + 1) and the potential vm. By the way, it is also possible to set k = m + 3, k = m + 4, etc. For example, when k = 4 and m = 1, the synchronization signal potential determination means indicates that the potential of the multi-level synchronization signal is “referenced to potential v3. It is determined whether or not it is between the “positive side on / off threshold potential” and the “minus side on / off threshold potential with reference to the potential v2.” Also in this case, the on / off threshold voltages of both the MOS • FETs are similarly set to a large value. In any case, there are two ON periods during the cycle or single pulse.

  The multi-value transfer gate means of the eighth embodiment (second invention) shown in FIG. 11 uses the synchronization signal potential determination means in which two synchronization signal potential determination means are combined. The range of potentials to be separated can be separated into two and independent. For example, if k = 7 and m = 3, when the potential of the synchronizing signal is “potential v3 and its vicinity” or “potential v7 and its vicinity”, the bidirectional switching means is driven on, which potential However, it is driven off when neither is in the vicinity. Further, when the number of synchronizing signal potential determining means to be combined is increased, the number of potential ranges to be determined can be increased to three, four, and the like. In particular, in the case of multi-value logic circuits such as tens of values or 100 values, it is convenient and can be used effectively.

  The multi-value transfer gate means of Embodiment 9 (second invention) shown in FIG. 12 expands the range of potentials determined by the synchronization signal potential determination means in Embodiment 6 of FIG. , Normally-on-type NMOS FET with back gate and source connected one by one, each diode as diode means "normally off-type NMOS FET with gate and back gate connected, source and drain connected Is a multi-value transfer gate means replaced one by one.

An embodiment of the multi-value synchronous latch means of the third invention is the second invention at the input terminal In of any one of the multi-value storage means of Embodiments 1 to 5 (FIGS. 1 and 5 to 8) of the first invention. The output terminal Out of any one of the multi-value transfer gate means in any of the sixth to ninth embodiments (FIGS. 9 to 12) may be connected, but both multi-value numbers (N of N values. It's normal to match them.) The multi-value number of the multi-value storage means may be smaller.
The multi-value storage means may be any one of the derived embodiments of the first to fifth embodiments (FIGS. 1 and 5 to 8), and the multi-value transfer gate means may be the sixth to ninth embodiments (FIG. Any one of the derived embodiments 9 to 12) may be used.

  Here, the “derivative embodiment” means “an embodiment in which one or a plurality of constituent means is replaced with another equivalent constituent means in the original embodiment” or “symmetric with respect to the voltage direction or voltage polarity with respect to the original embodiment. Examples having a general relationship ”and the like. And, “an embodiment having a symmetric relationship with respect to the voltage direction or the voltage polarity with respect to the original embodiment” means that the power supply potentials in each of the original embodiments are opposite to each other, and each controllable switching means is “ Replaced one by one with controllable switching means (eg, PMOS FET for NMOS / FET) that are complementary to each other, and the direction of each constituent means (eg diode) is reversed. This is an example.

  An embodiment of the multi-value synchronous latch means of the third invention is shown in FIG. 13 (FIG. 13) at the input terminal In of any one of the multi-value storage means of Embodiments 1 to 5 (FIGS. 1 and 5 to 8) of the first invention. It is only necessary to connect the output terminal Out of any one of the multi-value transfer gate means of a) and (b), but both multi-value numbers are the same as described above. The multi-value storage means may be any one of the derived embodiments of Embodiments 1 to 5 (FIGS. 1 and 5 to 8), and the multi-value transfer gate means is shown in FIGS. Any one of the derivatives of the means of b) may be used.

  Here, the multi-value transfer gate means shown in FIGS. 13A and 13B will be described. Both of the multi-value transfer gate means are turned on and off at the “plus-side on / off threshold potential with reference to the lowest potential v0” as in the case of the binary transfer gate means. The multi-value transfer gate means of FIG. 13 (b) simplifies the configuration of the on / off drive means in the multi-value transfer gate means of FIG. Each of the diodes is replaced with a “normally-off type NMOS FET with a back gate and source connected”, and each diode is replaced with a “normally off type NMOS FET with a gate, back gate and source connected”. Multi-value transfer gate means replaced one by one.

  Example 12 of the multilevel synchronous latch means of the third invention. 13 (a) and 13 (b), both multi-value transfer gate means are as described above (paragraph number 0036). “Multi-value transfer gate having a symmetrical relationship with respect to the gate means in terms of voltage direction or voltage polarity” However, these derived multi-value transfer gate means are driven to be turned on and off with the “minus on / off threshold potential with reference to the highest potential v5” as a boundary. Naturally, any one of these derived multi-value transfer gate means and the above-described multi-value storage means according to the first invention and any one of the derived embodiments are combined to provide a multi-value synchronous system according to the third invention. Latch means can be configured.

  Example 13 of the multilevel synchronous latch means of the third invention. In Example 6 of FIG. 9, when the “PMOS FET having the gate grounded to the power supply line Vm”, the “NMOS FET having the drain grounded to the power supply line Vm”, and the resistance between the gate and the source are removed, the derived multi-value transfer The gate means is turned on and off at the “minus side on / off threshold potential with reference to the potential vm” as a boundary. On the other hand, when the “PMOS FET whose source is grounded to the power supply line Vm” is removed in the embodiment 6 of FIG. 9, the derived multi-value transfer gate means is “a positive on / off threshold value based on the potential vm. It is turned on and off at the “potential”. Naturally, any one of these derived multi-value transfer gate means is combined with any one of the above-described multi-value storage means of the first invention and the derived embodiment, and the multi-value synchronous system of the third invention is combined. Latch means can be configured.

  Example 14 of the multilevel synchronous latch means (master / slave type) of the third invention. “In the ninth embodiment of FIG. 12, the multi-value number is changed to 10 and k = 8 and m = 1 are set, and the ON / OFF driving of the bidirectional switching means is opposite to each other. The multi-value synchronous latch means (10 values) of the third invention, which combines the gate means (10 values) and the multi-value storage means (10 values) of the first invention, and "the multi-value number in the sixth embodiment of FIG. The multivalued synchronous latch according to the third invention, which is a combination of the multivalued transfer gate means (10 values) of the second invention and the multivalue storage means (10 values) of the first invention, which is changed to 10 and set to m = 5 Master / slave type multi-value synchronous latch means (10 values) can be configured by connecting "means (10 values)" in the preceding and succeeding stages. In the former bidirectional switching means, the potential of the multilevel synchronization signal is “a positive on / off threshold potential with reference to the potential v8” and “a negative on / off threshold potential with respect to the potential v1”. ”Is turned off when it is in between, and it is turned on when there is not. On the other hand, in the latter bidirectional switching means, the potential of the multilevel synchronization signal is between “a positive on / off threshold potential and a negative on / off threshold potential with reference to the potential v5”. When it is on, it is turned on, and when it is not, it is off. As a result, this master / slave type multi-value synchronous latch means can rewrite twice during one cycle of the synchronous staircase wave.

A fifteenth embodiment (fourth invention) shown in FIGS. 14 and 15 corresponds to the multilevel synchronization signal generating means according to the fifth aspect, and N = 6. The synchronization signal output terminal SSout corresponds to the outlet means described in the same section, and is connected to the “four bidirectional switching means in which two sources and gates of the PMOS FET are connected to each other” and “to the synchronization signal output terminal SSout. 15 corresponds to the N (= 6) pull means in the above description, and in FIG. 15, “the remaining five NMOS FETs, five resistors, and two values”. The “connected body of four OR circuits, etc.” corresponds to the on / off driving means described in the same section. The “ring counter means with initial value setting circuit 1” shown in FIG. 14 corresponds to the binary counter means described in the same section. The binary counter means may be a “ring counter means with a self-start circuit”.
Reference: “Introduction to Transistor Circuit Lecture 5: Digital Circuits” published by Ohm Co., Ltd. on May 20, 1981. p. 136-p. 149 "Ring counter etc.". Supervised and written by Yoshifumi Amemiya and others.

  In the binary ring counter means of FIG. 14, ten binary D-type flip-flops are connected in a ring shape, and ten types of counter signals u0 to u4 and d5 to d1 are formed. However, the number 10 is derived from 2 (N−1), N = 6. Only one of the 10 counter signals is a binary “1”, the rest is “0”, and the 10 counter signals are sequentially changed to “1”. The initial value setting circuit 1 is, for example, a power-on reset circuit, and sets only the “binary D-type flip-flop that outputs the counter signal u0” through the binary NOT circuit when setting the initial value, and the remaining binary D-type. Reset all flip-flops. In the case of a staircase wave (eg, FIG. 4) that combines an ascending staircase and a descending staircase, the potential is two times each other than the lowest potential and the highest potential, so the on / off driving means of FIG. Four input binary OR concave paths are used, and the on / off driving means includes four bidirectional switching means (= bidirectional pull means) connected to the power supply lines V1 to V4 in one cycle. Is turned on twice. The binary counter means used may be a 2 (N-1) base counter, an up counter, a down counter, a Johnson counter, or the like, but 2 (N-1) types of counters that are repeatedly output in order. It is necessary to discriminate the signals by a binary AND circuit or the like, and to make these counter signals correspond to N pull means.

  Embodiment 16 of the multilevel synchronization signal generating means of the fifth invention (claim 6). Synchronized signal generation of upstairs wave. In the multi-level synchronization signal generating means of the fifteenth embodiment (fourth invention) shown in FIGS. 14 and 15, the “D-type flip-flop that outputs the counter signals d4 to d1” is removed, and the counter signal d5 is directly “ "D-type flip-flop that outputs counter signal u0", four binary OR circuits are removed, and each counter signal u1 to u4 is directly input to each on / off drive NMOS FET. The synchronization signal generating means can be configured. In this case, the potential of the multilevel synchronization signal suddenly drops to the potential v0 after the potential v5. The generation of the downward staircase synchronization signal can be realized by simply switching the input of the counter signals u0 to u4 and d5 in this upward staircase multilevel synchronization signal generating means. The counter signals u0 to u4 and d5 are sequentially input to the pulling means of the potentials v0 to v5 in the case of the upward staircase wave. It can be generated by inputting to the v0 to v5 pull means.

  Finally, a supplementary explanation will be given. For convenience of explanation, it is called an input terminal, an output terminal (corresponding to an entrance means or an exit means in the claims), and an input / output terminal, but it does not actually exist as a terminal, but a simple conductor, electrode or conductive plate. In many cases. This is the same as what is called "base terminal of transistor, base electrode, base lead wire or simply base", for example. Further, it is easy to change the multi-value number (N of N values) of the multi-value storage means of the first invention. For example, in the embodiment of FIG. 1, if all the transistors and all diodes between the power supply line V1 and the power supply line V2 are removed and the power supply line V1 and the power supply line V2 are directly connected and combined into one, the quaternary storage is stored from the quinary storage. Can be changed. Further, the quaternary storage can be changed to the ternary storage by removing the component parts between the power supply line V2 and the power supply line V3 and making the power supply lines common to both power supply lines. On the contrary, in order to change from 5-value storage to 6-value storage or more, in the embodiment of FIG. 1, “one of the power supply lines V1 to V3 is converted into two power supply lines in the opposite direction, and both power supply lines. Repeating “adding similar components in the same configuration in the meantime” can increase the number of multi-values as much as possible. This change in the multi-value number can be applied to other embodiments and derivatives thereof.

  Here, the unique effect of the first invention will be supplementarily described. In the case of a normal 4-transistor binary CMOS static memory, the multilevel storage means shown in the left half of FIG. 2 has “the magnitude of the write input current of the stored contents is affected by the magnitude of the read output current capacity” There is no unique problem. Specifically, in the binary CMOS memory, the left and right 2 input / output terminals (or entry / exit means) are owned by the left and right, so one is dedicated to input, the other is dedicated to output, and the output current capacity of the output CMOS / NOT circuit If the output current capacity of the input side CMOS / NOT circuit is reduced, the write input current can be reduced and the read output current can be increased. Contrast: paragraph number (0003). Therefore, the above problem is a unique problem of the above-described multi-value storage means, and the multi-value storage means of the first invention has a unique effect that “the unique problem can be solved”. When the write input current is large, it is necessary to make the data line thick according to the size of the input current capacity, and the degree of integration of the IC decreases.

多値同期式ラッチ手段の実施例の構成要素となる多値トランスファー・ゲート手段を２つ示す回路図である。

It is a circuit diagram which shows one Example of a multi-value storage means. It is a circuit diagram which shows the circuit explaining the problem which should be solved. It is a circuit diagram showing conventional multi-value storage means and multi-value synchronous latch means. It is a wave form diagram which shows one waveform example of a multi-level synchronizing signal.

FIG. 5 is a circuit diagram showing two multi-value transfer gate means as components of an embodiment of the multi-value synchronous latch means.

Claims (6)

When 3 or 3 or more predetermined multiples are represented by N,
“First potential supply means to N potential supply means for supplying N potentials whose potential increases in order from the first potential to the Nth potential”;
“(N-1) pieces of common inlet means that are provided one by one between the two potential supply means that are adjacent to each other by number, and from which the input means for inputting input signals are combined into one. Input potential discrimination means comprising binary NOT means ",
“One is provided between each of the first potential supply means to the Nth potential supply means and the common inlet means, one of which is pulled up or pulled down based on the output signal of the input potential determination means. A first pull means group consisting of N pull means that perform a down operation,
“One exit means for outputting an output signal corresponding to the stored content from there and one each between the first potential supply means to the Nth potential supply means, and based on the output signal of the input potential determination means, Multi-value storage means characterized in that any one of them has a second pull means group consisting of N pull means that perform pull-up or pull-down operation. When 3 or 3 or more predetermined multiples are represented by N,
“First potential supply means to N potential supply means for supplying N potentials whose potential increases in order from the first potential to the Nth potential”;
“The potential of the synchronization signal of the staircase wave combining the ascending stairs and the descending stairs given from the outside is“ a negative threshold value of the first specific potential from the second potential to the (N−1) th potential ”. Synchronized signal potential determining means for determining whether the potential is between “the potential” and “the positive threshold potential of the second specified potential of the (N−1) th potential from the first specified potential” When,
"Bidirectional switching means for bidirectional switching"
“Both when operating according to the output signal of the synchronizing signal potential determining means, and when the synchronizing signal potential determining means determines that the synchronizing signal potential is between both threshold potentials or not, both Multi-value transfer gate means comprising on / off drive means for driving the directional switching means to be turned on and to be turned off when not determined. A multi-value transfer gate means or one end of a bidirectional switching means of the multi-value transfer gate means according to claim 2 is connected to the common entrance means of the multi-value storage means according to claim 1. Value synchronous latch means.   4. A multi-level synchronous latch means according to claim 3, wherein two multi-level synchronous latch means according to claim 3 are connected to each other in a front stage and a rear stage to form a master / slave type. When 3 or 3 or more predetermined multiples are represented by N,
“First potential supply means to N potential supply means for supplying N potentials whose potential increases in order from the first potential to the Nth potential”;
"Exit means for outputting a multi-level synchronization signal therefrom"
“One between each of the first potential supply means to the Nth potential supply means and the exit means, and outputs the multilevel synchronization signal by pulling up or down the potential of the exit means. N pulling means "
"Binary counter means for repeatedly outputting 2 (N-1) types of counter signals in order based on a binary synchronization signal given from the outside,"
“According to the 2 (N−1) kinds of counter signals,“ from the first potential to the Nth potential in order, and from the (N−1) th potential to the Nth potential. 2 to (N-1) stage potential in a ring-like repetitive order returning to the first potential and the 2 (N-1) types of counter signals one by one. The pull means for pulling up or pulling down the potential of the outlet means to the potential corresponding to the counter signal output from the binary counter means is turned on, and all the remaining pull means are driven off. Multi-level synchronization signal generating means characterized by having "on / off driving means". When 3 or 3 or more predetermined multiples are represented by N,
“First potential supply means to N potential supply means for supplying N potentials whose potential increases in order from the first potential to the Nth potential”;
"Exit means for outputting a multi-level synchronization signal therefrom"
“One between each of the first potential supply means to the Nth potential supply means and the exit means, and outputs the multilevel synchronization signal by pulling up or down the potential of the exit means. N pulling means "
“Binary counter means for repeatedly outputting N types of counter signals in order based on a binary synchronization signal given from the outside”;
“Operating in accordance with the N types of counter signals, the counter signal output order corresponding to the order of increasing or decreasing the order of the N potentials one by one, and the binary counter means On-off drive means for driving on the pull means for pulling up or pulling down the potential of the outlet means to the potential corresponding to the counter signal output by the power supply, and driving off all the remaining pull means. Multi-level synchronization signal generating means comprising:

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