JP4673207B2 - Multilayer printed wiring board and manufacturing method thereof - Google Patents

Description

  The present invention relates to a multilayer printed wiring board in which an electronic component (semiconductor element) such as an IC is incorporated, and more specifically, a multilayer in which electrical connection and connection reliability between a connection pad of a semiconductor element and a conductor circuit are ensured. The present invention relates to a printed wiring board and a manufacturing method thereof.

  Examples of conventional multilayer printed wiring boards with built-in semiconductor elements include those described in Patent Documents 1 and 2. The multilayer printed wiring board described in these documents is a substrate on which a recess for embedding a semiconductor element is formed, a semiconductor element embedded in the recess of the substrate, and a substrate so as to cover the semiconductor element. The insulating layer is formed, a conductor circuit formed on the surface of the insulating layer, and a via hole provided in the insulating layer so as to electrically connect the conductor circuit and the pad of the semiconductor element.

  In such a conventional multilayer printed wiring board, external connection terminals (for example, PGA, BGA, etc.) are provided on the surface of the outermost layer, and the semiconductor element built in the substrate is connected via these external connection terminals. It is designed to make an electrical connection with the outside.

Japanese Patent Application Laid-Open No. 2003-312405 describes a printed wiring board in which a plurality of semiconductor elements are embedded. Such a printed wiring board in which a plurality of semiconductor elements are embedded has a structure in which via bumps are formed on a conductor circuit, and the semiconductor elements are electrically connected via the via bumps. It has been proposed that a functionally-implemented printed wiring board for mounting components can be obtained by realizing functionalization and mounting other components on the substrate surface layer in place of semiconductor elements.
JP 2001-339165 A JP 2002-050874 A JP 2001-267490 A

  However, in the semiconductor element mounting substrate according to the related art as described above, applicable semiconductor elements are limited. In other words, due to the pad arrangement of the semiconductor element, it may not be applied as a semiconductor element mounting substrate. For example, a connection pad is arranged in a grid pattern in a region along the outer periphery of the element body, and a semiconductor element (grid type) that is not arranged near the center of the element body, and the connection pad is the whole of the element body. In some cases, the conformity may differ depending on the semiconductor element (full grid type) in which the pads are arranged in a grid pattern over the region. The grid type semiconductor element is easy to adapt, but it is difficult to adapt to the full grid type semiconductor element.

  The reason why such a full-grid type semiconductor element is difficult to be adapted is that the mounting substrate according to the prior art is paired with a pad of the semiconductor element and a conductor circuit formed on the substrate corresponding to the pad. Bumps must be formed. A full-grid type semiconductor element can correspond to a pad of a semiconductor element near the outer periphery, but cannot correspond to a pad of a semiconductor element inside.

  Many of the full grid type semiconductor elements have high performance and are driven in a high frequency region, but there is a tendency that power supply tends to be delayed. In the first place, since a plurality of semiconductor elements are embedded, the conventional technology is limited to the formation of a conductor circuit of a printed wiring board, and in particular, the conductor circuit for connecting to a plane layer such as a ground layer is also limited. The supply of power to the device seems to be delayed, which may cause problems such as malfunctions at the initial startup of the semiconductor device.

  In addition, even in the case of semiconductor elements arranged in a grid pattern, if the pitch between adjacent pads is narrow, the prior art cannot structurally arrange a conductor circuit for connection to the semiconductor element. Sometimes it could not be adapted. Further, in the reliability, a defect caused by heat (for example, early deterioration in a reliability test such as a heat cycle) may occur.

A main object of the present invention is to propose a multilayer printed wiring board for mounting a semiconductor element capable of ensuring electrical connectivity and reliability and a method for manufacturing the same.
Another object of the present invention is to propose a multilayer printed wiring board for mounting semiconductor elements which is not easily affected by signal delay and the like, and a method for manufacturing the same.

As a result of intensive studies for realizing the above object, the present inventors have incorporated a semiconductor element in a recess formed in a resin insulation layer, and another resin insulation layer formed immediately above the resin insulation layer. In addition, via holes that are electrically connected to each connection pad of the semiconductor element are formed, and other via holes or through-hole conductors that are formed in a resin insulating layer in which the semiconductor element is embedded are connected to these via holes. by be Kai pulling the surface layer of the printed wiring board through, it can increase the degree of freedom of wiring design, and finding that can ensure stability of the connection between the semiconductor element and the conductor layer, based on such findings The present invention has been completed with the following content.

That is, the present invention
(1) Via holes or all layers in which other resin insulation layers and conductor layers are alternately laminated on a resin insulation layer containing a semiconductor element, and electrical connection between these conductor layers is formed in the resin insulation layer A multilayer printed wiring board formed through a through-hole conductor layer formed through
It said semiconductor element is embedded in the resin insulating layer which is formed in the recess,
The resin insulating layer is formed of truncated conical filled vias formed from the upper and lower surfaces of the resin insulating layer and superimposed in opposite directions, and is formed between conductor layers formed on the upper and lower surfaces of the resin insulating layer. A first via hole is formed to electrically connect
In another resin insulation layer formed on the resin insulation layer containing the semiconductor element, a second via hole connected to the connection pad of the semiconductor element and a third via hole connected to the first via hole are provided. A via hole is formed, and further, a conductor circuit that electrically connects the second via hole and the third via hole, or a conductor circuit that electrically connects the second via hole to the through-hole conductor layer is formed. A multilayer printed wiring board.

  In the present invention, a ground conductor layer or a power supply conductor layer can be formed on the resin insulation layer other than the resin insulation layer in which the semiconductor element is incorporated. A conductor layer for grounding or a conductor layer for supplying power via a conductor circuit that electrically connects the via hole and the third via hole or a conductor circuit that electrically connects the second via hole to the through-hole conductor. Can be electrically connected.

  In the present invention, a plurality of recesses containing semiconductor elements are formed, and different semiconductor elements can be embedded in each recess.

  A metal layer is formed on the bottom surface of the recess in which the semiconductor element is built, and the semiconductor element can be embedded in the recess through the metal layer.

  The side surface of the recess containing the semiconductor element can be formed to have a taper such that the side surface becomes wider toward the upper side from the bottom surface.

  In the present invention, a mediation layer is formed on the connection pad of the semiconductor element, and the connection pad and the via hole can be electrically connected via the mediation layer.

Furthermore, the present invention provides
(2) Via holes in which other resin insulation layers and conductor layers are alternately stacked on a resin insulation layer containing at least one semiconductor element, and electrical connection between these conductor layers is formed in the resin insulation layer. In manufacturing a multilayer printed wiring board performed via the above, during the manufacturing process, at least the following steps (a) to (f):
(A) forming a filled via that penetrates the first insulating resin substrate and forming a metal layer on one surface of the first insulating resin substrate;
(B) a step of pressing and integrating the second insulating resin base material on one surface of the first insulating resin base material;
(C) Forming other filled vias that pass through the second insulating resin base material that has been pressure-bonded and electrically connected to the filled vias formed in the first insulating resin base material; Forming a first via hole and forming a conductor layer electrically connected to the first via hole on the surface of the second insulating resin base material,
(D) forming at least one recess reaching the surface of the metal layer from the other surface of the first insulating resin substrate;
(E) a step of housing a semiconductor element in the recess and bonding using an adhesive;
(F) After forming the resin insulating layer covering the semiconductor element, filled vias that penetrate the resin insulating layer and are electrically connected to the connection pads of the semiconductor element are formed. A via hole is formed, a filled via that penetrates the resin insulating layer and is electrically connected to the first via hole is formed, a third via hole is constituted by these filled vias, and the second via hole is further formed. Forming a conductor circuit connecting the first via hole and the third via hole;
A method for producing a multilayer printed wiring board.

The present invention also provides:
(3) Via holes in which other resin insulation layers and conductor layers are alternately laminated on a resin insulation layer containing at least one semiconductor element, and electrical connection between these conductor layers is formed in the resin insulation layer. Or, in manufacturing a multilayer printed wiring board performed through through-hole conductor layers penetrating all layers, during the manufacturing process, at least the following steps (a) to (i):
(A) forming a filled via that penetrates the first insulating resin substrate and forming a metal layer on one surface of the first insulating resin substrate;
(B) a step of pressing and integrating the second insulating resin base material on one surface of the first insulating resin base material;
(C) Forming other filled vias that pass through the second insulating resin base material that has been pressure-bonded and electrically connected to the filled vias formed in the first insulating resin base material; Forming a first via hole and forming a conductor circuit electrically connected to the first via hole on the surface of the second insulating resin substrate;
(D) forming at least one recess reaching the surface of the metal layer from the other surface of the first insulating resin substrate;
(E) a step of housing a semiconductor element in the recess and bonding using an adhesive;
(F) After forming the resin insulating layer covering the semiconductor element, filled vias that penetrate the resin insulating layer and are electrically connected to the connection pads of the semiconductor element are formed. A via hole is formed, a filled via that penetrates the resin insulating layer and is electrically connected to the first via hole is formed, a third via hole is constituted by these filled vias, and the second via hole is further formed. Producing a first multilayer printed wiring board formed with a conductor circuit connecting the first via hole and the third via hole;
(G) The process of producing a 2nd multilayer printed wiring board by repeating the process of said (a)-(f),
(H) a step of laminating the first multilayer printed wiring board and the second multilayer printed wiring board via a resin insulating layer;
(I) forming a through-hole conductor penetrating all layers of the laminated multilayer printed wiring board and forming a conductor circuit electrically connected to the second via hole;
A method for producing a multilayer printed wiring board.

In the manufacturing method according to the present invention, the concave portion containing the semiconductor element can be formed by laser irradiation, and the side surface thereof can be formed into a taper shape that becomes wider toward the upper side from the bottom surface.
In the semiconductor element, a columnar electrode or a mediation layer is formed on the connection pad in advance, and the connection pad and the via hole can be electrically connected through the columnar electrode or the mediation layer.

According to the present invention, a printed wiring board (conductor layer) per unit area can be used regardless of the pad arrangement of a semiconductor element such as a semiconductor element having a full grid connection pad or a semiconductor element having a narrow pitch connection pad. Connection points can be increased. That is, since the degree of freedom in forming a conductor circuit connected to the semiconductor element can be increased, the connection stability between the semiconductor element and the conductor layer can be secured.
In particular, it is easy to increase the number of connection points between the ground conductor layer / power source conductor layer, which is a plane layer, and it is easy to ensure electrical characteristics as a semiconductor element mounting substrate.
For example, a semiconductor element having a full-grid connection pad is an element that is highly functional and driven in a high-frequency region. This semiconductor element has a problem that it may cause a voltage drop due to insufficient power supply at the time of initial startup. Such a problem can be solved by increasing the number of connection points between the ground conductor layer / power source conductor layer, which is a plane layer, that is, power can be supplied efficiently without delay. Troubles such as malfunctions are reduced during initial startup.

  Further, in a multilayer printed wiring board in which an interlayer insulating layer and a conductor layer are alternately laminated on a substrate in which one or more semiconductor elements are embedded in a resin insulating layer, it is connected to each semiconductor element. It is necessary to form a complicated circuit such as a conductor circuit, a conductor circuit connecting between semiconductor elements, a conductor circuit connecting a semiconductor element to an external terminal, etc., but a via hole formed in a substrate in which a semiconductor element is embedded or all Since a conductor circuit connected to an embedded semiconductor element can be routed through a through-hole conductor that penetrates the layer, it is possible to easily secure a space in wiring design and increase the degree of freedom in wiring design. it can.

  In the present invention, a ground conductor layer or a power supply conductor layer is formed on a resin insulation layer other than the resin insulation layer in which the semiconductor element is embedded, and the connection pad of the semiconductor element is connected via a via hole or a through-hole conductor. Thus, it can be electrically connected to a ground conductor layer or a power supply conductor layer which is a plane layer.

  For example, among the conductor layers connected to the semiconductor element, the signal line routed in the surface layer of the interlayer insulating layer is connected to the surface conductor layer through the via hole, while the ground line / power supply line is the embedded substrate Can be connected to a ground conductor layer or a power supply conductor layer, which is a plane layer, via a via hole or a through hole conductor. As a result, the voltage drop with respect to the embedded semiconductor element is reduced, and the time until recovery is performed in a short time. Therefore, troubles such as malfunctions are likely to be reduced at the initial startup of the semiconductor element.

  On the other hand, in the prior art, although it is possible to connect to a semiconductor element, it is necessary to form a bump that is paired with a conductor circuit in forming a conductor circuit (pad), so that the degree of freedom of circuit formation is increased. I was restricted. For this reason, when the number of pads is increased or the distance between adjacent pads is narrow, it is not possible to establish connection with more semiconductor elements. Therefore, even if a full-grid semiconductor element or a semiconductor element that is a narrow-pitch pad is embedded in a printed wiring board, a conductor circuit to be connected cannot be formed or a conductor circuit for plane layer connection cannot be formed. As a result, power supply has become delayed, and electrical connectivity and reliability are likely to deteriorate.

In addition, by forming a metal layer on the bottom surface of the recess provided in the resin insulation layer of the substrate, it becomes easy to make the depth of the recess uniform, especially when the recess has a rectangular cross section, the recesses near the four corners. It becomes easy to equalize the depth.
Therefore, when the semiconductor element is accommodated in the recess, the tilt of the semiconductor element can be suppressed, so that a desired via hole can be formed even when the via hole connected to the connection pad of the accommodated semiconductor element is formed in the resin insulating layer. It can be a shape. Furthermore, since the metal layer is formed in the resin insulating layer, warping is less likely to occur due to the influence of thermal stress or external stress, and as a result, for example, connection pads of semiconductor elements and conductor circuits such as via holes Therefore, the electrical connection and the connection reliability are not easily lowered.

  In addition, since the adhesive layer formed between the semiconductor element and the metal layer can be easily made uniform in thickness, the adhesion of the semiconductor element is made uniform, and a reliability test under a heat cycle condition is performed. Even if it repeats, the adhesiveness becomes difficult to fall.

  Further, by forming the side surface of the recess for accommodating the semiconductor element into a tapered shape, the semiconductor element accommodated in the recess is subjected to stress in the side surface direction (for example, thermal stress or external stress), The stress can be relieved.

  Further, even in the adhesive for fixing the semiconductor element, the adhesive is not diffused along the side surface of the recess, and the adhesion to the bottom of the recess of the semiconductor element is hardly lowered.

Further, when the columnar electrode or the intermediate layer is formed on the pad of the semiconductor element, the electrical connection between the pad of the semiconductor element and the via hole can be easily performed.
Furthermore, by providing the intermediary layer, it is possible to easily confirm the operation of the semiconductor element and perform an electrical inspection even before or after the semiconductor element is embedded, accommodated, or accommodated in the printed wiring board.

  In the present invention, another resin insulation layer and a conductor layer are alternately laminated on a resin insulation layer in which a semiconductor element is built, and electrical connection between these conductor layers is formed in the resin insulation layer. In a multilayer printed wiring board formed through a through-hole conductor, a first via hole that electrically connects conductor layers formed on an upper surface and a lower surface is formed in a resin insulating layer containing a semiconductor element, and a semiconductor A second via hole connected to the connection pad of the semiconductor element and a third via hole connected to the first via hole are formed in the other resin insulating layer located immediately above the resin insulating layer containing the element, Further, a conductor circuit that electrically connects the second via hole and the third via hole, or the second via hole is electrically connected to the through-hole conductor. Be a multilayer printed circuit board, characterized in that a conductor circuit is formed.

  According to such a configuration, since the second via hole is formed at the position corresponding to the connection pad of the semiconductor element in the other resin insulating layer located immediately above the resin insulating layer containing the semiconductor element, The connection pad of the semiconductor element may be other than the resin insulating layer containing the semiconductor element through the second via hole, the third via hole, the first via hole, or the second via hole and the through-hole conductor. It is electrically connected to a conductor layer formed on the resin insulation layer.

  The connection pads of the respective semiconductor elements can be pulled back toward the semiconductor embedded substrate via via holes or through-hole conductors. Therefore, the degree of freedom for arranging the conductor circuit on the surface layer connected to the semiconductor element is increased. As a result, a wiring is formed along the surface layer on the interlayer insulating layer in which the via hole connected to the semiconductor element is formed, and what is pulled down toward the embedded substrate through the via hole in the interlayer insulating layer is formed. It can be made. Therefore, in the conductor circuit connected to the semiconductor element, the number of conductor circuits that can be formed per unit area can be increased.

  Regardless of the pad arrangement of a semiconductor element such as a semiconductor element having a full-grid connection pad or a semiconductor element having a narrow-pitch connection pad, all the connection pads are conductors in a state of being embedded in the recess. Can be connected to a layer.

Further, if the wiring is connected to the ground layer / power plane layer, the number of wirings to be connected to the plane layer can be increased, and the possibility of supplying power is increased. It becomes difficult to delay, power can be supplied in a timely manner even at the initial startup of the semiconductor element, and malfunction of the semiconductor element is hardly caused. Via holes or through-hole conductors in the embedded substrate can shorten the distance to the plane layer.
That is, the degree of the voltage drop of the semiconductor element at the initial start-up can be reduced, and as a result, the time until the voltage drop is recovered is shortened. .

The plane layer is desirably disposed below the position where the semiconductor element is embedded. Further, since it is desirable to arrange the plane layer at a position as close as possible to the buried region of the semiconductor element, the plane layer is desirably arranged or adjacent to the buried substrate. As a result, the distance between the plane layer and the semiconductor element can be reduced, so that the time until recovery is quicker and the delay in power supply is reduced with respect to the drop in voltage drop at the initial startup of the semiconductor element. Can do.
In addition, the conductor layer connected to the plane layer is preferably connected at a plurality of locations by via holes or through-hole conductors formed in the embedded substrate. As a result, the wiring length is not increased more than necessary, so that the voltage drop of the semiconductor element can be suppressed, and the time until recovery can be shortened.

  In the prior art, since the conductor circuit connected to the connection pad of the semiconductor element has only been formed along the surface layer, it has been subject to limitations in circuit formation. In addition, shortening the distance between the semiconductor element and the plane layer is limited. Therefore, it was easy to cause problems in electrical connection and connection reliability.

  In the present invention, the interlayer insulating layer formed on the substrate containing the semiconductor element is preferably formed using a resin that does not include a core material. This is because a via hole (second via hole) connected to the connection pad of the semiconductor element is formed in the interlayer insulating layer. For example, when a via hole is opened with a laser, the shape of the via hole is not hindered, and a small diameter via hole can be formed. This is because, in the resin contained in the core material, the core material may inhibit the formation of the via hole.

  Further, when the conductor circuit formed on the interlayer insulating layer is connected to the ground layer / power supply layer through the first via hole formed in the embedded substrate, more connections can be made. Thus, it is desirable to be connected to a via hole or a through hole conductor. In some cases, one wiring may be connected to two or more first via holes or two or more through-hole conductors formed in the embedded substrate. As a result, the probability of supplying power is improved, and the power supply to the embedded semiconductor element is performed without delay, and the amount of voltage drop is reduced, resulting in malfunction of the semiconductor element, etc. It becomes difficult to cause trouble.

Examples of the resin that does not include the core material include thermosetting resins such as epoxy resins, polyimide resins, and phenol resins, thermoplastic resins such as epoxy resins, phenoxy resins, and polyether sulfones, and photosensitive resins provided with (meth) acrylic groups. Resin or a resin composite containing two or more of these resins may be used. Among these resins, core for reinforcing is not contained.
By using these resins, the formation of via holes in contact with the portions corresponding to the pads of the semiconductor elements and the degree of freedom of the via formation are ensured. Even if the pads of the embedded semiconductor elements are arranged in a grid, a full grid However, via holes can be formed in the same way to obtain connectivity.

  In the multilayer printed wiring board according to the present invention, the embedded substrate in which the semiconductor element is embedded is composed of a plurality of layers of an insulating base material made of a resin including a core material, and the core material is contained on one or both sides of the embedded substrate. Since the structure in which the interlayer insulating layers that are not formed are stacked, that is, the interlayer insulating layer that does not include the core material, is a buffer layer, it is possible to suppress the occurrence of misalignment or cracks in the substrate during the stacking.

  The diameter of the via hole (first via hole) formed in the embedded substrate is preferably in the range of 20 to 150 μm. The via is preferably formed by photoetching or laser (CO2 laser, excimer laser, YAG laser). Since the embedded substrate is formed of a resin containing a core material, it is a limit in processing to reduce the via hole diameter to less than 20 μm. In a conductor circuit (including a via hole land) connected to the via hole, This is because the contact area tends to be small, which may cause problems in electrical connectivity. On the other hand, when the via hole diameter is larger than 150 μm, the wiring density in the embedded substrate is lowered, and the formation of the ground layer / power supply layer and the like may be restricted, and the electrical characteristics may be lowered. It is.

  Furthermore, it is desirable that the diameter of the via hole (second via hole) formed in the interlayer insulating layer provided immediately above the substrate containing the semiconductor element is 20 to 100 μm. The via is preferably formed by photoetching or laser (CO2 laser, excimer laser, YAG laser). If the via hole diameter is less than 20 μm, the contact area with the portion corresponding to the pad of the semiconductor element (columnar electrode or mediating layer) is small, which may cause problems in connectivity, while the via hole diameter exceeds 100 μm. This is because there is a possibility that a portion corresponding to the pad of the semiconductor element and a portion corresponding to another adjacent pad may come into contact with each other.

Moreover, in this invention, it is desirable to form a metal layer on the bottom face of the recessed part provided in the resin insulating layer. This is because it is easy to make the depths of the recesses uniform, particularly when the recesses have a rectangular cross section, the depths of the recesses near the four corners are easily made uniform.
Therefore, when the semiconductor element is accommodated in the recess, the tilting of the semiconductor element is suppressed, so that a desired via hole shape can be formed even when the via hole connected to the pad of the accommodated semiconductor element is formed in the resin insulating layer. It can be. Furthermore, since the metal layer is formed in the resin insulating layer, warping is less likely to occur due to the influence of thermal stress or external stress, and as a result, for example, connection pads of semiconductor elements and conductor circuits such as via holes Therefore, the electrical connection and the connection reliability are not easily lowered.

  In addition, since the adhesive layer formed between the semiconductor element and the metal layer can be easily made uniform in thickness, the adhesiveness of the semiconductor element is made uniform, and reliability tests such as heat cycle conditions are performed. Even if it performs, it becomes difficult for the adhesiveness to fall over a long period of time.

  Moreover, it is desirable to form the side surface of the recessed part for accommodating a semiconductor element in a taper shape. This is because the semiconductor element accommodated in the recess can relieve the stress even when subjected to stress in the lateral direction (for example, thermal stress or external stress).

  Further, even in the adhesive for fixing the semiconductor element, the adhesive is not diffused along the side surface of the recess, and the adhesion to the bottom of the recess of the semiconductor element is hardly lowered.

  In the present invention, it is desirable that a columnar electrode or a mediating layer is formed on the pad of the semiconductor element. This is because the electrical connection between the pad of the semiconductor element and the via hole can be easily performed.

  Semiconductor device pads are generally made of aluminum or the like, but particularly when a via hole is formed in an interlayer insulating layer by photoetching in the state of a pad of aluminum or the like in which an intermediate layer is not formed. In addition, the resin tends to remain on the surface layer of the pad after exposure and development, and in addition, the pad may be discolored due to the adhesion of the developer.

  On the other hand, when a via hole is formed by a laser, there is a risk of burning a pad made of aluminum or the like. In addition, if laser irradiation is performed under conditions that do not cause burnout, resin residue may be generated on the pad. Further, after a post-process (for example, an immersion process or various annealing processes in an acid, an oxidizing agent, or an etching solution), discoloration or dissolution of a pad of a semiconductor element may occur. Furthermore, since the pad of the semiconductor element is made with a diameter of about 40 μmφ and the via hole is made with a diameter larger than that, misalignment is likely to occur, and problems such as disconnection between the pad and the via hole occur. It becomes easy.

  On the other hand, by providing a mediating layer made of copper or the like on the pad of the semiconductor element, the problem of via hole formation is solved and the use of a solvent is possible, so that the resin residue on the pad can be prevented. In addition, the discoloration or dissolution of the pad does not occur even after the subsequent process. This makes it difficult for the electrical connectivity and connection reliability between the pad and the via hole to decrease. Furthermore, by interposing a mediation layer having a diameter larger than that of the die pad of the semiconductor element, the pad and the via hole can be reliably connected.

  Furthermore, by providing the intermediary layer, it is possible to easily confirm the operation of the semiconductor element and perform an electrical inspection even before or after the semiconductor element is embedded, accommodated, or accommodated in the printed wiring board. The reason is that since the intermediate layer larger than the pad of the semiconductor element is formed, the probe pin for inspection becomes easy to contact. As a result, whether or not the product is available can be determined in advance, and productivity and cost can be improved. Further, pad loss or scratches due to the probe are less likely to occur. Therefore, by forming the mediation layer on the pad of the semiconductor element, it is possible to suitably embed, accommodate, and accommodate the semiconductor element in the printed wiring.

  As the resin insulation layer for housing the semiconductor element used in the present invention, glass cloth epoxy resin base material, phenol resin base material, glass cloth bismaleimide triazine resin base material, glass cloth polyphenylene ether resin base material, aramid nonwoven fabric-epoxy A hard laminated substrate selected from a resin substrate, an aramid nonwoven fabric-polyimide resin substrate, and the like can be used. Other than this, what is generally used with a printed wiring board can be used. For example, a double-sided or single-sided copper-clad laminate, a resin plate without a metal film, a resin film, or a composite material thereof can also be used.

  The resin substrate preferably has a thickness in the range of 20 to 350 μm. The reason is that if the thickness is less than 20 μm, it may be difficult to ensure the insulating property of the interlayer insulating layer, and the electrical connectivity may be lowered. On the other hand, if the thickness exceeds 350 μm, it may be difficult to form via holes for interlayer connection, and electrical connectivity may be deteriorated.

  In the present invention, copper is preferably used as the metal layer formed on the bottom surface of the recess provided in the metal layer for forming the conductor circuit and the resin insulating layer. The reason is that processing by etching is easy. Therefore, the size of the metal layer can be arbitrarily changed. In addition, even if the metal layer formed on the bottom surface of the recess has electrical connectivity, it is excellent in electrical characteristics.

  As for the copper foil for forming the said conductor circuit, it is desirable that the thickness is the range of 5-20 micrometers. The reason is that if the thickness of the copper foil is less than 5 μm, the copper foil around the opening may be deformed when an opening for forming a via hole is formed in the insulating resin base material using laser processing as will be described later. This is because it is difficult to form a conductor circuit. On the other hand, when the thickness of the copper foil exceeds 20 μm, it is difficult to form a conductor circuit pattern having a fine line width by etching.

  The copper foil used in the present invention may have a thickness adjusted by a half etching process. In this case, it is desirable to adjust the thickness of the copper foil attached to the resin insulating layer so that the thickness of the copper foil after etching is 5 to 20 μm, using a thickness larger than the above-mentioned numerical value.

  Furthermore, in the case of a double-sided copper-clad laminate, the copper foil thickness is within the above range, but the thickness may be different on both sides. Thereby, the strength can be ensured and the subsequent process can be prevented from being hindered.

  Moreover, as for the thickness of the copper foil as a metal layer formed in the bottom face of the said recessed part, 5-20 micrometers is desirable. The reason is that when the thickness of the copper foil is less than 5 μm, when the cavity processing is performed, the effect of forming the metal layer may be offset by penetrating the copper foil. On the other hand, if the thickness of the copper foil exceeds 20 μm, it may be difficult to form a metal layer by etching.

  As a metal layer provided on the bottom surface of the recess, a metal such as nickel, iron, cobalt, etc. may be used in addition to copper. Moreover, the alloy containing these metals or the alloy containing 2 or more types may be sufficient.

  The insulating resin base material and the copper foil are, in particular, one side or both sides obtained by laminating an epoxy resin in a glass cloth to form a B stage and a copper foil, and heating and pressing. It is preferable to use a copper clad laminate. The reason is that the position of the wiring pattern and the via hole is not shifted during handling after the copper foil is etched, and the positional accuracy is excellent.

  In the present invention, the concave portion provided in the resin insulating layer for accommodating the semiconductor element can be formed by laser processing, counterbore processing, punching, or the like, and is particularly preferably formed by laser processing.

  When the concave portion is formed by laser processing, it is easier to obtain depth uniformity than the counterbore processing, and in particular, the depth uniformity to the metal layer is excellent. Therefore, it is possible to suppress problems such as inclination when the semiconductor element is accommodated. Further, it is possible to accurately perform a taper-shaped process as will be described later.

  Moreover, when forming a recessed part by counterbore processing, since the metal layer formed in the bottom face of a recessed part plays the role of a stopper, the depth of a recessed part can be made uniform.

  The depth of the recess is determined in accordance with the thickness of the semiconductor element itself to be accommodated and the thickness of the columnar electrode or the mediating layer that may be formed on the connection pad of the semiconductor element. Since the metal layer is formed on the entire bottom surface of the recess, it is easy to make the thickness of the adhesive layer provided between the semiconductor element and the resin insulating layer uniform.

As a result, the adhesiveness between the semiconductor element and the resin insulating layer can be maintained uniformly, so that the adhesiveness is hardly lowered even when the reliability test under the heat cycle condition is repeated.
Moreover, you may provide a roughening surface in the metal layer formed in the bottom part of this recessed part. Thereby, since a metal layer and an adhesive agent are closely_contact | adhered, it becomes easy to obtain adhesiveness.

  The recess for accommodating the semiconductor element is preferably formed in a shape having a taper that widens toward the upper side from the bottom surface. By adopting such a shape, the semiconductor element accommodated in the recess can relieve the stress even when subjected to stress in the lateral direction (for example, thermal stress or external stress). Furthermore, since the adhesive provided on the bottom surface of the semiconductor element for fixing the semiconductor element is less likely to flow along the side surface of the recess due to capillary action, the adhesion of the semiconductor element to the bottom of the recess is unlikely to decrease. Become.

  In the present invention, as shown in FIG. 1, the taper angle of the side surface of the recess is defined as an external angle formed by the side surface and the bottom surface, and the angle is desirably 60 degrees or more and less than 90 degrees, and is preferably 60 degrees to 85 degrees. A range of degrees is more desirable. The reason is that if the angle is less than 60 degrees, restraining the movement due to the stress on the side surface of the semiconductor element may be offset. For this reason, when a reliability test is performed, a connection failure in the via hole portion is caused early. It is easy to cause.

  In the present invention, as one embodiment of the insulating resin layer for housing the semiconductor element, two insulating resin substrates as described above are used, that is, a metal layer having a size related to the size of the semiconductor element on one surface. Formed of a first insulating resin base material and a second insulating resin base material laminated on the surface of the first insulating resin base material on which the metal layer is formed. A semiconductor element accommodation recess is formed on the other surface of the resin substrate by laser processing so as to reach the metal layer, and the metal layer is exposed from the recess.

  In another embodiment, a first insulating resin in which a metal layer having a size related to the size of the semiconductor element is formed on one surface, and an opening is previously formed in a region corresponding to the metal layer. Laminating the second insulating resin base material, forming a recess in a form in which one of the openings is closed, and forming a semiconductor housing substrate formed so that the metal layer is exposed from the recess Also good.

  In such an embodiment, the thickness of the first insulating resin substrate and the second insulating resin substrate is desirably 20 to 350 μm. The reason is that if the thickness is less than 20 μm, it may be difficult to ensure the insulating property of the interlayer insulating layer, and the electrical connectivity may be lowered. On the other hand, if the thickness exceeds 350 μm, it may be difficult to form via holes for interlayer connection, and electrical connectivity may be deteriorated.

  Moreover, as each insulating resin base material, the resin base material which consists of a single layer may be used, and the resin base material multilayered by two or more layers may be used.

  After the semiconductor element is embedded and accommodated in the recess of the semiconductor accommodation substrate, an interlayer resin insulation layer is formed on one or both surfaces of the semiconductor accommodation substrate, and then the electrical insulation between the semiconductor element and the interlayer resin insulation layer is formed on the interlayer resin insulation layer. After forming the conductor circuit including the via hole to be connected, the multilayer printed wiring board according to the present invention can be manufactured by alternately laminating other interlayer resin insulation layers and conductor circuits.

  As the semiconductor element embedded in the recess of the semiconductor housing substrate, either a semiconductor element in which a columnar electrode is formed in advance on the connection pad or a semiconductor element in which a mediating layer covering the connection pad is formed can be used. These semiconductor elements are electrically connected to via holes provided in the interlayer resin insulating layer via columnar electrodes or mediating layers.

Hereinafter, (1) a method for manufacturing a semiconductor element having a columnar electrode and (2) a semiconductor element having a mediating layer will be described.
(1) Manufacturing method of semiconductor element having columnar electrode The semiconductor element having a columnar electrode used in the present invention means a semiconductor element having a columnar electrode or rewiring.

  As shown in FIG. 2, a connection pad 2 made of aluminum or the like is formed on a semiconductor element 1 (silicon substrate) in a wafer state, and a protective film 3 (passivation film) is formed on the upper surface except for the central portion of the connection pad 2. Prepare the one formed. In this state, the surface of the connection pad 2 is exposed at the central portion that is not covered with the protective film 3.

Next, the base metal layer 4 is formed on the entire top surface of the semiconductor element 1. As the base metal layer, chromium, copper, nickel, or the like can be used.
Next, a plating resist layer made of a liquid resist is formed on the upper surface of the base metal layer 4, and an opening is formed in a portion corresponding to the connection pad of the semiconductor element of the plating resist layer.

  Next, columnar electrodes 5 are formed on the upper surface of the base metal layer in the opening of the plating resist layer by performing electrolytic plating using the base metal layer 4 as a plating current path. Thereafter, the plating resist layer is peeled, and further, unnecessary portions of the base metal layer are removed by etching using the columnar electrode 5 as a mask, so that the base metal layer 4 remains only under the columnar electrode.

  Further, a sealing film 6 made of epoxy resin, polyimide, or the like is formed on the upper surface side of the semiconductor element 1. In this state, when the upper surface of the columnar electrode 5 is covered with the sealing film 6, the upper surface of the columnar electrode 5 is exposed by appropriately polishing the surface. Next, through a dicing process, individual semiconductor chips (semiconductor elements having columnar electrodes) are obtained.

(2) Manufacturing Method of Semiconductor Device Having Intermediary Layer The intermediary layer used in the present invention means an intervening layer for making an electrical connection with a via hole provided on the pad of the semiconductor element.

  As shown in FIG. 3, vapor deposition, sputtering, etc. are performed on the entire surface of the built-in semiconductor element 10 to form a conductive metal layer 12 (first thin film layer) on the entire surface. As the metal, tin, chromium, titanium, nickel, zinc, cobalt, gold, copper and the like are preferable. As thickness, it is good to form between 0.001-2.0 micrometers. If it is less than 0.001 μm, it is difficult to form a metal layer having a uniform film thickness on the entire surface. On the other hand, if the thickness exceeds 2.0 μm, the film thickness may vary. In the case of chromium, a thickness of 0.1 μm is desirable.

  The connection pad 14 is covered with the first thin film layer 12, and the adhesion at the interface between the mediating layer 20 and the connection pad 14 of the semiconductor element can be improved. Further, by covering the connection pad 14 of the semiconductor element 10 with these metals, moisture can be prevented from entering the interface, the pad can be prevented from being dissolved and corroded, and the reliability can be hardly lowered.

  As the metal of the first thin film layer 12, it is desirable to use any one of chromium, nickel, and titanium. This is because the adhesion between the connection pad 14 and the metal layer 12 is good, and it is easy to prevent moisture from entering the interface.

  A second thin film layer 17 is formed on the first thin film layer 12 by sputtering, vapor deposition, or electroless plating. Examples of the metal include nickel, copper, gold, and silver. It is desirable that the second thin film layer 17 is also made of copper because the thickening layer formed in the electrical characteristics, economy, or subsequent process is mainly made of copper.

  Here, the reason why the second thin film layer 17 is provided is that it is difficult to obtain a lead for electrolytic plating for forming a thickening layer to be described later with only the first thin film layer 12. The second thin film layer 17 is used as a thick lead.

  The thickness of the second thin film layer 17 is desirably in the range of 0.01 to 5.0 μm. The reason is that if the thickness is less than 0.01 μm, it cannot serve as a lead. On the other hand, when the thickness exceeds 5.0 μm, the first thin film layer as a lower layer is etched more and a gap is formed at the time of etching, so that moisture easily enters and reliability is lowered.

  The second thin film layer 17 is thickened by electroless or electrolytic plating. Examples of the metal to be formed include nickel, copper, gold, silver, zinc, and iron. Electrical properties, economy, strength as a mediating layer, structural resistance, or the conductor layer of the build-up wiring layer formed in a later process is mainly formed from copper, so it is desirable to form it by electrolytic copper plating .

  The thickness of the thick electrolytic copper plating layer 18 is desirably in the range of 1 to 20 μm. The reason is that if the thickness is less than 1 μm, the connection reliability with the upper via hole is lowered. On the other hand, if the thickness exceeds 20 μm, an undercut occurs during etching, and a gap is generated at the interface between the formed intermediate layer and the via hole. In some cases, the first thin film layer may be directly thick-plated or further laminated in multiple layers.

  Thereafter, an etching resist is formed, and exposure and development are performed to expose portions of the metal other than the intermediate layer to perform etching, and the first thin film layer 12, the second thin film layer 17, and the thickening layer are formed on the pads of the semiconductor element. An intermediate layer 20 composed of 18 is formed.

  In addition to the method for producing the intermediate layer, the intermediate layer may be formed after the semiconductor element is built in the recess of the substrate, or a dry film resist may be formed on the metal film formed on the semiconductor element and the core substrate. After forming and removing the portion corresponding to the mediating layer and thickening by electrolytic plating, the resist can be peeled off and the mediating layer can be similarly formed on the die pad of the semiconductor element by an etching solution.

Next, an example of a method for producing a multilayer printed wiring board according to the present invention will be specifically described.
In manufacturing the multilayer printed wiring board according to the present invention, the semiconductor element housing substrate constituting the multilayer printed wiring board includes a first insulating resin base material and a first insulating resin base material in which copper foil is bonded to both surfaces of the insulating resin base material. The thing of the form which laminated | stacked two insulating resin base materials is used.

(1) The first insulating resin base material can be formed from, for example, a double-sided copper-clad laminate, and laser irradiation is performed on one surface of such a double-sided copper-clad laminate to provide a first insulating property. A via hole forming opening that penetrates one copper foil surface of the resin base material and the resin insulating layer and reaches the other copper foil (or conductor circuit pattern) is formed.

The laser irradiation is performed using a pulse oscillation type carbon dioxide laser processing apparatus. The processing conditions are as follows: the pulse energy is 0.5 to 100 mJ, the pulse width is 1 to 100 μs, the pulse interval is 0.5 ms or more, and the frequency 2000 to 2000. It is desirable that the frequency is 3000 Hz and the number of shots is in the range of 1 to 5.
The diameter of the opening for forming a via hole that can be formed under such processing conditions is desirably 50 to 250 μm.

  In addition, in order to form an opening for forming a via hole in a copper clad laminate by laser irradiation, a direct laser method in which laser irradiation is performed to simultaneously form an opening in a copper foil and an insulating resin substrate, and an opening for forming a via hole are provided. There is a conformal method in which the copper foil portion corresponding to is previously removed by etching and then the insulating resin base material is irradiated with a beam, either of which may be used.

(2) In order to remove the resin residue remaining in the opening formed in the step, it is desirable to perform a desmear process.
This desmear treatment is performed by wet treatment such as chemical treatment of an acid or an oxidizing agent (for example, chromic acid or permanganic acid), or dry treatment such as oxygen plasma discharge treatment, corona discharge treatment, ultraviolet laser treatment, or excimer laser treatment. Is called.
The method for selecting these desmear treatments is selected according to the type of insulating resin base material, the thickness, the opening diameter of the via hole, the smear amount expected to remain depending on the laser conditions, and the like.

(3) The copper foil surface of the desmear-treated substrate is subjected to an electrolytic copper plating process using the copper foil as a plating lead, and the electrolytic copper plating is completely filled in the opening to form a filled via.
In some cases, after the electrolytic copper plating treatment, the electrolytic copper plating raised above the filled via may be removed and flattened by belt sander polishing, buff polishing, etching, or the like.

(4) A resist layer is formed on both surfaces of the first insulating resin base material, and after an exposure / development process, an etching process is performed with an etchant made of cupric chloride or the like on a resist non-formed part Do. After that, by stripping the resist, a conductor circuit including a via hole land, a positioning mark for alignment, etc. are formed on one surface of the first insulating resin substrate, and a semiconductor is formed on the other surface. A metal layer having a size related to the element, a conductor circuit including a via hole land, a positioning mark for alignment, and the like are formed.

(5) A second insulating resin substrate is laminated on the surface of the first insulating resin substrate on which the metal layer is formed.
For example, a second insulating resin substrate is formed from a copper foil laminated on a prepreg as an adhesive layer, and is laminated by thermocompression bonding on one side of the first insulating resin substrate. Form the body.

(6) On the surface provided with the metal layer of the first insulating resin base material constituting the laminate, the surface of the copper foil of the second insulating resin base material is irradiated with laser in the same manner as in the above (1). An opening for forming a via hole that penetrates and passes through the resin layer and reaches the conductor circuit including the via hole land formed in the first insulating resin base material is formed.

  The processing conditions for the opening for forming the via hole are a pulse energy of 0.5 to 100 mJ, a pulse width of 1 to 100 μs, a pulse interval of 0.5 ms or more, a frequency of 2000 to 3000 Hz, and a shot number of 1 to 10. It is desirable.

  The diameter of the via hole forming opening that can be formed under the processing conditions is preferably 50 to 150 μm. This is because it is easy to ensure the interlayer connectivity and increase the wiring density.

(7) In order to remove the resin residue remaining in the via hole forming opening formed in the step (6), a desmear process is performed in the same manner as in the above (2).

(8) Next, electrolytic copper plating treatment using the copper foil as a plating lead on the copper foil surface of the desmeared substrate in a state where the surface of the first insulating resin base material is covered with a protective film. To fill the opening completely with electrolytic copper plating and form a filled via.
These filled vias are connected to the filled via formed in (3) above, and are formed on the front and back surfaces of the semiconductor element housing substrate made of the first insulating resin base material and the second insulating resin base material. Forming a first via hole for electrically connecting the two.

In some cases, after the electrolytic copper plating treatment, the electrolytic copper plating raised above the filled via may be removed and flattened by belt sander polishing, buff polishing, etching, or the like.
Moreover, you may form electroplating through electroless plating. In this case, the electroless plating film may use a metal such as copper, nickel, or silver.

(9) Next, a resist layer is formed on the electrolytic copper plating film. The resist layer may be applied or any method of pasting a film-like one in advance. A mask on which a circuit was previously drawn was placed on this resist, exposed and developed to form an etching resist layer, and the metal layer in the portion where no etching resist was formed was etched and formed in (8) above A conductor circuit including filled via lands is formed, and then the protective film attached in the step (8) is peeled off.

  As the etching solution, at least one aqueous solution selected from aqueous solutions of monohydrogen sulfate, persulfate, cupric chloride, and ferric chloride is desirable.

  As a pretreatment for etching the copper foil to form a conductor circuit, the entire surface of the copper foil may be etched in advance to adjust the thickness in order to facilitate the formation of a fine pattern.

  The via hole land as a part of the conductor circuit preferably has an inner diameter substantially the same as the via hole diameter or an outer diameter larger than the via hole diameter and a land diameter in the range of 75 to 350 μm. .

(10) Next, an opening reaching the surface of the metal layer through the resin layer by laser processing, for example, in the surface region (semiconductor element housing region) opposite to the surface on which the metal layer of the first insulating resin substrate is provided Then, a recess is formed so that the surface of the metal layer is exposed from the opening to obtain a semiconductor element housing substrate. If necessary, a recess that exposes the metal layer can be formed through a resist formation step and an etching step.

  For example, the layer of the first insulating resin base material and the second insulating resin base material is irradiated with laser using a pulse oscillation type carbon dioxide gas laser processing apparatus to form a resin layer from the surface of the first insulating resin base material. An opening reaching the surface of the metal layer through the substrate is formed to form a recess for accommodating or incorporating the semiconductor element.

The processing conditions for the recess for housing the semiconductor element are as follows: the pulse energy is 0.5 to 100 mJ, the pulse width is 1 to 100 μs, the pulse interval is 0.5 ms or more, the frequency is 2000 to 3000 Hz, and the number of shots is 1 to 10. It is desirable that
By such laser processing, a recess for incorporating the semiconductor element is formed, and a metal layer (in this case, a copper foil) is exposed on the bottom surface of the recess.

(11) A semiconductor element is embedded in the semiconductor element housing substrate obtained by the steps (1) to (10).
As the semiconductor element to be embedded, as described above, either a semiconductor element in which a columnar electrode is previously formed on a connection pad or a semiconductor element in which an intermediate layer covering the connection pad is formed can be used. Here, the case where the latter is used will be described.

  The intermediary layer is an intermediary layer provided to directly connect the connection pad of the semiconductor element and the via hole (first via hole). A thin film layer is provided on the connection pad, and the thin film layer is provided on the intermediary layer. Further, it is formed by providing a thickening layer, and is preferably formed of at least two metal layers.

Moreover, it is preferable that this mediation layer is formed in a size larger than the connection pad of the semiconductor element. Such a size facilitates alignment with the connection pad, resulting in improved electrical connectivity with the connection pad and via-holes by laser irradiation or photoetching without damaging the connection pad. Processing becomes possible. Therefore, the semiconductor element can be securely embedded, accommodated, accommodated, and electrically connected to the printed wiring board.
In addition, a metal layer that forms a conductor circuit of a printed wiring board can be directly formed on the mediating layer.

  In addition to the manufacturing method as described above, the mediating layer is a resist made of a dry film on the entire surface of the connection pad side of the semiconductor element or a metal film formed on the semiconductor element housing substrate in which the semiconductor element is embedded. After removing the portion corresponding to the mediation layer, it is thickened by electrolytic plating, and after that, the resist is peeled off and the mediation layer is similarly formed on the connection pad of the semiconductor element by the etching solution. it can.

(12) After providing an interlayer insulating layer made of a resin not impregnated with a core material on one side or both sides on a substrate in which a semiconductor element is built, By performing the same processing as (1) to (4), a via hole (second via hole) that is electrically connected to a mediating layer formed on a connection pad of a built-in semiconductor element, for accommodating a semiconductor element Via holes (third via holes) electrically connected to via holes (first via holes) respectively formed in the first and second insulating resin base materials which are the substrates, and the second via holes and the third via holes A multilayer printed wiring board formed by forming a conductor circuit connecting the via hole is produced.

  The conductor layer is connected to a via hole formed in the embedded substrate via a via hole different from that for routing the wiring on the surface layer, and is routed below the embedded substrate. The signal lines are mainly routed on the surface layer, the ground lines / power supply lines are mainly routed below the embedded substrate, and the plane layers and via holes or through-hole conductors formed below are buried. It is connected through this. As a result, the voltage drop with respect to the embedded semiconductor element is reduced and the time until recovery is shortened, so that it is difficult to cause a malfunction or the like.

Furthermore, by laminating the insulating resin layer and the copper foil and repeating the same processes as in the above (1) to (4), via holes are formed in the laminated interlayer insulating layer, and the via holes are electrically connected. A multilayer printed wiring board having a further multilayered build-up wiring layer in which another outer conductor circuit connected to the substrate is formed can be obtained.

  In the build-up wiring layer forming method described above, the insulating resin layers are multilayered by sequentially laminating the insulating resin layers. If necessary, two circuit boards each having one unit of insulating resin layer are formed. It is good also as a multilayer printed wiring board by laminating | stacking the insulating resin layer by laminating | stacking above and carrying out thermocompression bonding collectively.

(13)
Next, in the same manner as in the above (1) to (12), a plurality of concave portions, for example, two concave portions are formed in the semiconductor element housing substrate made of the first and second insulating resin base materials, and the concave portions are formed in the concave portions. Each of the different semiconductor elements is incorporated, and a via hole (second via hole) electrically connected to the intermediate layer formed on the connection pad of each semiconductor element, the first and second insulations which are semiconductor element accommodation substrates A via hole (third via hole) electrically connected to a via hole (first via hole) formed in each of the conductive resin substrates, and a circuit for connecting the second via hole and the third via hole, or the second Another multilayer printed wiring board is produced by forming a conductor circuit that electrically connects the via hole to the through-hole conductor.
Furthermore, by laminating an insulating resin layer and a copper foil and repeating the same processes as in the above (1) to (4), another multilayer printed wiring board having a multilayered build-up wiring layer can be obtained. it can.

(14) Next, a resin insulation layer made of a resin in which a core material is not impregnated between a multilayer printed wiring board in which one of the semiconductor elements is incorporated and a multilayer printed wiring board in which two semiconductor elements are incorporated. A plurality of semiconductor elements are built in the interlayer insulating layer by pressing the outermost layer of the multilayer printed wiring board in a state where the insulating resin layer and the copper foil are overlapped with each other. A laminate is produced.
In addition, as for the press-fit conditions of this collective press, it is desirable that the temperature is 80 to 250 ° C. and the press pressure is 1 to 25 kgf / cm 2.

(15) Further, a through-hole conductor forming opening penetrating all the layers of the laminate produced in (14) and a via hole forming opening reaching the conductor circuit located in the outermost layer of the laminate are formed by drilling. .
As for this processing condition, it is desirable that the number of revolutions of the drill is 100 to 300 Krpm, and the feed rate of the drill is 90 to 150 inches / minute.
The through-hole conductor forming opening is provided, for example, so as to penetrate through a conductor circuit connecting at least the second via hole and the third via hole in the multilayer printed wiring board.

(16) In the same manner as (2) to (4), a desmear process is performed to remove the resin residue remaining in the through-hole conductor forming opening and the via-hole forming opening. The copper foil surface is subjected to electrolytic copper plating treatment using copper foil as the plating lead, and the electrolytic copper plating is completely filled in the opening for forming the through-hole conductor and the opening for forming the via hole. Form.
The through-hole conductor is electrically connected to, for example, a conductor circuit connecting the second via hole and the third via hole in the multilayer printed wiring board, and the ground layer / power supply layer provided in the interlayer insulating layer is It is electrically connected to an external power source through a through-hole conductor.

(17) In the same manner as (5) above, a resist layer is formed on one or both sides of the substrate, and after an exposure / development process, an etching solution made of cupric chloride or the like is applied to the resist non-formed portion, Etching is performed.
Thereafter, by removing the resist, a conductor circuit including through-hole lands and via-hole lands is formed on one or both sides of the substrate.

(18) Next, a solder resist layer covering the outermost conductor circuit formed in (17) is formed. In this case, the solder resist composition is applied to the entire outer surface of the circuit board, the coating film is dried, and then a photomask film in which the opening of the solder pad is drawn is placed on the coating film to expose and develop. By processing, a solder pad opening exposing the conductive pad portion located immediately above the via hole of the conductor circuit is formed. In this case, an opening may be formed by attaching a solder resist layer in a dry film and exposing / developing or laser processing.

A corrosion resistant layer such as nickel-gold is formed on the solder pad exposed from the non-formation portion of the mask layer. At this time, the thickness of the nickel layer is desirably 1 to 7 μm, and the thickness of the gold layer is desirably 0.01 to 0.1 μm.
In addition, nickel-palladium-gold, gold (single layer), silver (single layer), or the like may be formed. After forming the corrosion-resistant layer, the mask layer is peeled off. As a result, a printed wiring board in which a solder pad with a corrosion-resistant layer and a solder pad without a corrosion-resistant layer are mixed is obtained.

(19) A solder body is supplied to the solder pad portion exposed immediately above the via hole from the opening of the solder resist obtained in the step (18), and solder bumps are formed by melting and solidifying the solder body, or conductive. A multilayer circuit board is formed by bonding a conductive ball or a conductive pin to a pad portion using a conductive adhesive or a solder layer.
As a method of supplying the solder body and the solder layer, a solder transfer method or a printing method can be used.

  Here, in the solder transfer method, a solder foil is bonded to a prepreg, and this solder foil is etched leaving only a portion corresponding to the opening portion, thereby forming a solder pattern to form a solder carrier film. This is a method in which a film is laminated so that a solder pattern comes into contact with a pad after a flux is applied to a solder resist opening portion of a substrate, and this is transferred by heating.

  On the other hand, the printing method is a method in which a printing mask (metal mask) having an opening at a position corresponding to a pad is placed on a substrate, a solder paste is printed, and heat treatment is performed. As solder for forming such solder bumps, Sn / Ag solder, Sn / In solder, Sn / Zn solder, Sn / Bi solder, etc. can be used, and their melting points are connected between the circuit boards to be laminated. It is desirable that the melting point of the conductive bump is lower.

(Example 1-1)
(1) Preparation of base material First, a printed circuit board constituting a semiconductor element housing substrate is manufactured. This printed circuit board includes a first insulating substrate 30 and a second insulating substrate 40, and is formed by laminating these substrates. As an example of the material of the printed circuit board, a double-sided copper clad laminate obtained by laminating a prepreg made of glass cloth with epoxy resin in a B cloth and laminating copper foil and hot pressing is used as a starting material. Use.

  As the first insulating substrate 30, a double-sided copper-clad laminate in which a copper foil 34 having a thickness of 15 μm is stuck on both surfaces of a resin insulating layer 32 having a thickness of 100 μm is used. The thickness of the copper foil may be adjusted to 15 μm by etching using a copper foil 32 having a thickness greater than 15 μm (see FIG. 4A).

(2) Formation of opening for forming via hole The surface of one copper foil of the first insulating base material 30 is irradiated with a carbon dioxide laser to penetrate the copper foil 34 and the resin insulating layer 32 to the surface of the other copper foil. A via hole forming opening 36 was formed (see FIG. 4B). Furthermore, the inside of the opening was desmeared by chemical treatment with permanganic acid.

In this embodiment, the opening 36 for forming the via hole is formed by using a high peak short pulse oscillation type carbon dioxide gas laser processing machine manufactured by Hitachi Via Co., Ltd. The foil was directly irradiated on the foil under the following irradiation conditions to form an opening for forming a 75 μmφ via hole at a speed of 100 holes / second.
(Irradiation conditions)
Pulse energy: 75mJ
Pulse width: 80μs
Pulse interval: 0.7ms
Frequency: 2000Hz

(3) Formation of electrolytic copper plating film The copper foil is used as a plating lead under the following plating conditions on the copper foil surface provided with the via hole forming opening 36 of the first insulating substrate 30 after the desmear treatment. Electrolytic copper plating treatment was performed.
[Electrolytic plating solution]
Sulfuric acid 2.24 mol / l
Copper sulfate 0.26 mol / l
Additive A (reaction accelerator) 11.0 ml / l
Additive B (reaction inhibitor) 10.0 ml / l
[Electrolytic plating conditions]
Current density 1A / dm2
Time 65 minutes Temperature 22 ± 2 ℃

  By such a plating process, the formation of the electrolytic copper plating film 38 in the opening is promoted by the additive A, and conversely, the additive B adheres mainly to the copper foil portion to suppress the formation of the plating film. Further, when the inside of the opening is filled with electrolytic copper plating and becomes almost the same height as the copper foil, the additive B is attached, so that the formation of the plating film is suppressed similarly to the copper foil portion. Thus, the electrolytic copper plating was completely filled in the opening, and the electrolytic copper plating 38 and the copper foil 34 exposed from the opening were formed almost flat (see FIG. 4C).

  Further, the thickness of the conductor layer made of the copper foil 34 and the electrolytic copper plating film 38 may be adjusted by etching. In some cases, the thickness of the conductor layer may be adjusted by a physical method of sander belt polishing and buff polishing.

(4) Formation of Conductor Circuit, Filled Via, and Metal Layer Etching resist layer (using photosensitive dry film) on copper foil 34 and copper plating film 38 of first insulating substrate 30 that has undergone step (3). (Not shown) was formed. That is, an etching resist layer was formed on the copper foil surfaces on both sides of the first insulating substrate 30. The resist layer has a thickness in the range of 15 to 20 μm, and is exposed and developed using a mask on which a conductive layer including filled via lands and a metal layer of a size related to the size of the semiconductor element are drawn, and then copper A resist non-formation part was formed on the foil.

  Next, the resist non-formed part is etched with an etching solution composed of hydrogen peroxide / sulfuric acid to remove the copper plating film and the copper foil corresponding to the non-formed part.

  Thereafter, the resist is peeled off with an alkaline solution, thereby forming a metal layer 42 that contacts the conductor circuit 41 including the land of the filled via 39 and the semiconductor element. If necessary, dummy patterns, alignment marks, product recognition symbols, and the like can be formed.

  As a result, conductor circuits 41 are formed on the front and back surfaces of the first insulative substrate 30, filled vias 39 that electrically connect these conductor circuits 41 are formed, and a metal layer that contacts the semiconductor element is further formed. A circuit board formed with 42 is obtained.

  The metal layer 42 formed on the circuit board is formed on the back surface of the first insulating substrate, and the copper foil portion on the surface of the circuit board corresponding to the region for forming the recess for housing the semiconductor element is etched. It is removed (see FIG. 4 (d)).

(5) Lamination of first insulating substrate and second insulating substrate As the second insulating substrate 40 laminated on the first insulating substrate 30, the resin insulating layer 43 having a thickness of 60 μm is used. A single-sided copper-clad laminate in which a copper foil 44 having a thickness of 15 μm is stuck on one side is used.

Such a second insulating substrate 40 is laminated in a state where the surface on which the copper foil is not formed is in contact with the surface of the first insulating substrate 30 on which the metal layer 42 is formed. Lamination of the first insulating substrate 30 and the second insulating substrate 40 is performed by thermocompression bonding the two under the following conditions (see FIG. 4 (e)).
(Crimping conditions)
Temperature: 180 ° C
Press pressure: 150kgf / cm2
Crimping time: 15 minutes

  In this embodiment, the first insulating substrate 30 and the second insulating substrate 40 are formed as a single layer, but may be formed as a plurality of layers of two or more layers.

(6) Formation of opening for forming via hole The copper foil forming surface of the second insulating substrate 40 is irradiated with a carbon dioxide gas laser to penetrate the copper foil 44 and through the resin insulating layer 43. A via hole forming opening 46 reaching the surface of the conductor circuit 41 including the via land of the filled via 39 provided in the insulating base material 30 was formed (see FIG. 4F). Further, the inside of the openings was desmeared by chemical treatment with permanganic acid.

In this example, in order to form the opening 46 for forming the via hole in the second insulating base material 40, a high peak short pulse oscillation type carbon dioxide laser processing machine manufactured by Hitachi Via was used. The second insulating substrate 40 is directly irradiated on the copper foil 44 affixed to the glass cloth epoxy resin substrate 43 with a substrate thickness of 60 μm under the following irradiation conditions, and irradiated with a laser beam at 100 holes / second. An opening 46 for forming a 75 μmφ via hole was formed at a speed.
(Irradiation conditions)
Pulse energy: 75mJ
Pulse width: 80μs
Pulse interval: 0.7ms
Frequency: 2000Hz

(7) Formation of electrolytic copper plating film After covering the surface of the first insulating base material 30 by applying a protective film, the copper foil surface of the second insulating base material 40 after finishing the desmear treatment in the opening is applied. The electrolytic copper plating process using a copper foil as a plating lead was performed under the following plating conditions.
[Electrolytic plating solution]
Sulfuric acid 2.24 mol / l
Copper sulfate 0.26 mol / l
Additive A (reaction accelerator) 11.0 ml / l
Additive B (reaction inhibitor) 10.0 ml / l
[Electrolytic plating conditions]
Current density 1A / dm2
Time 65 minutes Temperature 22 ± 2 ℃

  In such a plating process, the formation of the electrolytic copper plating film in the opening is promoted by the additive A, and conversely, the additive B adheres mainly to the copper foil portion to suppress the formation of the plating film. Further, when the inside of the opening is filled with electrolytic copper plating and becomes almost the same height as the copper foil, the additive B is attached, so that the formation of the plating film is suppressed similarly to the copper foil portion. Thereby, the electrolytic copper plating was completely filled in the opening, and the electrolytic copper plating and the copper foil exposed from the opening were formed almost flat.

  Moreover, you may adjust thickness by etching the conductor layer which consists of copper foil and an electrolytic plating film. In some cases, the thickness of the conductor layer may be adjusted by a physical method of sander belt polishing and buff polishing.

(8) Formation of Conductor Circuit and Filled Via An etching resist layer (not shown) is formed using a photosensitive dry film on the copper foil 44 and the copper plating of the second insulating substrate 40 that has undergone the step (7). did. The resist layer had a thickness in the range of 15 to 20 μm, and a resist non-formed portion was formed on the copper foil through exposure and development using a mask on which a conductor circuit including filled via lands was drawn.

  Next, the resist non-formed part is etched with an etching solution composed of hydrogen peroxide / sulfuric acid to remove the copper plating film and the copper foil corresponding to the non-formed part.

Thereafter, the resist is peeled off with an alkaline solution, and further, the protective film attached to the surface of the first insulating base material 30 in the step (7) is peeled off, so that one surface of the second insulating base material 40 is peeled off. Conductor circuits 50 are formed, and filled vias 52 that electrically connect the conductor circuits 50 to lands of the filled vias 39 provided on the first insulating base material 30 are formed (see FIG. 4G). If necessary, dummy patterns, alignment marks, product recognition symbols, and the like can be formed.
The filled via 39 provided in the first insulating base material 30 and the filled via 52 provided in the second insulating base material 40 constitute a first via hole.

(9) Formation of recess for accommodating semiconductor element Cross section reaching the surface of the metal layer through the resin layer by irradiating the resin part from which the copper foil part has been removed by etching in the step (4) with carbon dioxide laser irradiation A substantially rectangular opening is formed, and the metal layer is exposed in the opening, and a recess 54 for incorporating the semiconductor element 55 is formed by the side surface of the opening and the metal layer surface (bottom surface) (FIG. 5). (See (a)).

In this example, a high peak short pulse oscillation type carbon dioxide laser processing machine manufactured by Hitachi Via was used to form the recess 54 for housing the semiconductor element in the first insulating substrate 30. A semiconductor to be accommodated by irradiating a glass cloth epoxy resin substrate having a substrate thickness of 60 μm to a region where the copper foil on the surface of the first insulating substrate is removed by irradiating a laser beam under the following irradiation conditions A recess 54 for accommodating a semiconductor element having a substantially rectangular cross section with a depth slightly larger than the element size and a depth of about 100 μm was formed.
(Irradiation conditions)
Pulse energy: 100mJ
Pulse width: 90μs
Pulse interval: 0.7ms
Frequency: 2000Hz

  The recess 54 for housing a semiconductor element formed by laser processing is in a state in which the metal layer 42 is exposed on the bottom surface, the depth of the recess 54 is substantially uniform, and the shapes of the four corners are also arcs. There wasn't.

(10) Housing of Semiconductor Element Having Columnar Electrode As the semiconductor element 55 to be housed and built in the recess 54 of the semiconductor element housing substrate manufactured according to the steps (1) to (9), the following (a) to (a) A semiconductor element having a columnar electrode produced by the step (d) was used.

(a) Preparation of silicon substrate A connection pad is formed on a silicon substrate (semiconductor substrate) in a wafer state, and a protective film (passivation film) is formed on the upper surface except for the central portion of the connection pad. A portion whose portion is exposed through an opening formed in the protective film is prepared.

(b) Formation of base metal layer A base metal layer made of copper having a thickness of 2 μm is formed on the entire top surface of the silicon substrate by sputtering.

(c) Formation of Columnar Electrode Next, a dry film resist made of a photosensitive resin such as an acrylic resin is laminated on the upper surface of the base metal layer to form a plating resist layer having a thickness of 110 μm. The height of the columnar electrode to be formed was set to about 100 μm.

Next, an opening is formed in the resist through exposure and development using a mask in which an opening is drawn in a portion corresponding to the pad of the plating resist layer.
Furthermore, by performing electrolytic copper plating using the base metal layer as a plating current path, a columnar electrode made of copper is formed on the upper surface of the base copper layer in the opening of the plating resist layer.
Finally, when the plating resist layer is peeled off and unnecessary portions of the base metal layer are removed by etching using the columnar electrode as a mask, the base metal layer remains only under the columnar electrode.

(d) Formation of Sealing Film A sealing film that is an insulating resin made of epoxy resin, polyimide, or the like is formed on the upper surface side of the silicon substrate obtained in (c). In this state, when the upper surface of the columnar electrode is covered with the sealing film, the upper surface of the columnar electrode is exposed by appropriately polishing the surface.

  Next, individual semiconductor chips (semiconductor devices) are obtained by a dicing process. At this time, the thickness of the semiconductor element 55A having the columnar electrode was formed to 100 μm.

  On the lower surface side of the semiconductor element 55A produced by the steps (a) to (d), a thermosetting adhesive, for example, an adhesive made of a thermosetting resin in which a part of an epoxy resin is acrylated is used. And an adhesive layer having a thickness of 30 to 50 μm was formed.

  Then, after accommodating in the recessed part 54 of the board | substrate for semiconductor element accommodation, it heat-processed between 100-200 degree | times, and hardened the adhesive bond layer. As a result, a substrate 60 with a built-in semiconductor element 55A was obtained (see FIG. 5B).

  At this time, the tip of the columnar electrode 58 of the semiconductor element and the upper surface of the substrate were substantially on the same plane. That is, the semiconductor element 55A was not inclined.

(11) Laminating Step Resin insulating layers 62 and 64 made of only a resin not including a reinforcing material having a thickness of 60 μm were laminated on the front and back surfaces of the substrate 60 obtained in the above (10).

(12) Formation of via hole formation opening Via hole formation opening 70 reaching the filled via 39 formed on the first insulating base material 30 forming the semiconductor element housing substrate from the surface of the resin insulation layer 62, and on the semiconductor element A via hole forming opening 72 reaching the columnar electrode 58 provided on the pad is formed, and the filled via 52 formed on the second insulating base material 43 forming the semiconductor element housing substrate is formed from the surface of the resin insulating layer 64. A via hole forming opening 74 was formed (see FIG. 5C). The laser irradiation conditions at this time were almost the same as in the step (6). Further, the inside of the openings was desmeared by chemical treatment with permanganic acid.

(13) Formation of Electrolytic Copper Plating Film After finishing the desmear process in the opening, an electrolytic copper plating process using a conductor circuit as a plating lead was performed under the following plating conditions.
[Electrolytic plating solution]
Sulfuric acid 2.24 mol / l
Copper sulfate 0.26 mol / l
Additive A (reaction accelerator) 10.0 ml / l
Additive B (reaction inhibitor) 10.0 ml / l
[Electrolytic plating conditions]
Current density 1A / dm2
Time 65 minutes Temperature 22 ± 2 ℃

  In such a plating process, the formation of the electrolytic copper plating film in the opening is promoted by the additive A, and conversely, the additive B adheres mainly to the copper foil portion to suppress the formation of the plating film. Further, when the inside of the opening is filled with electrolytic copper plating and becomes almost the same height as the copper foil, the additive B is attached, so that the formation of the plating film is suppressed similarly to the copper foil portion. Thereby, the electrolytic copper plating was completely filled in the opening, and the electrolytic copper plating and the copper foil exposed from the opening were formed almost flat.

Moreover, you may adjust thickness by etching the conductor layer which consists of copper foil and an electrolytic plating film. In some cases, the thickness of the conductor layer may be adjusted by a physical method of sander belt polishing and buff polishing.
As a result, the openings 70 and 72 are completely filled with electrolytic copper plating.

(14) Formation of conductor circuit On the copper foil and copper plating which passed through the process of said (13), the etching resist layer was formed using the photosensitive dry film. The resist layer had a thickness in the range of 15 to 20 μm, and a resist non-formed portion was formed on the copper foil through exposure and development using a mask on which a conductor circuit including filled via lands was drawn.

(15) Next, the resist non-formed part is etched with an etching solution made of hydrogen peroxide / sulfuric acid to remove the copper plating film and the copper foil corresponding to the non-formed part.
Thereafter, the resist is peeled off with an alkaline solution, so that a filled via 76 (second via hole) electrically connected to the columnar electrode 58 provided on the pad of the semiconductor element 55 is formed on the surface of the resin insulating layer 62, A filled via 78 (third via hole) that is electrically connected to the land of the filled via 39 (first via hole) provided in the first insulating substrate 30 and a conductor circuit 80 that connects at least the filled via 76 and the filled via 78 are provided. It is formed. On the other hand, on the surface of the resin insulating layer 64, a filled via 82 (third via hole) that is electrically connected to the land of the filled via 52 (first via hole) provided in the second insulating substrate 40, or at least the filled via 82 is provided. A multilayer printed wiring board 200 in which a conductor circuit 84 connected to the substrate is formed is produced.
Note that a dummy pattern, an alignment mark, a product recognition symbol, or the like can be formed as necessary.

Furthermore, a multilayered printed wiring board can be obtained by repeating the steps (11) to (15) as necessary.
In such lamination, the via holes may be laminated in the same direction or may be laminated in the opposite direction. Moreover, you may multilayer by combinations other than these.
As a result, there is a via hole that connects the front and back, a copper foil portion that forms a conductor circuit with the via hole, and a circuit board in which a semiconductor element is embedded is obtained.
At this time, the conductor circuit on the interlayer insulating layer is formed with wiring routed on the surface layer and wiring routed toward the embedded substrate.

(16)
Next, in the same manner as in the above (1) to (15), a plurality of recesses, for example, two recesses are formed in the semiconductor element housing substrate made of the first and second insulating resin bases, and the recesses are formed in these recesses. While incorporating different semiconductor elements 55B and 55C, respectively, resin insulating layers 62 and 64 are laminated on the front and back surfaces of the semiconductor element housing substrate,
On the surface of the resin insulating layer 62, a filled via 90 (second via hole) that is electrically connected to a mediating layer formed on a connection pad of each semiconductor element, or a first insulating property that is a substrate for housing a semiconductor element. A filled via 94 (third via hole) electrically connected to a filled via 92 (first via hole) formed on the resin base material, and a conductor circuit 96 connecting at least the filled via 90 and the filled via 94 are formed. The surface of the resin insulation layer 64 is connected to the filled via 100 (third via hole) electrically connected to the land of the filled via 98 (first via hole) provided on the second insulating base, or at least to the filled via 100. Another multilayer printed wiring board 300 formed with the conductive circuit 102 to be formed is produced (see FIG. 6).

(17)
Between the multilayer printed wiring board 200 containing one semiconductor element and the multilayer printed wiring board 300 containing two semiconductor elements, a resin insulating layer 104 made of a resin not impregnated with a core material is interposed, A plurality of semiconductor elements are built in the interlayer insulating layer by pressing the outermost layers of the multilayer printed wiring boards 200 and 300 in a state where the insulating resin layer 106 and the copper foil 108 are overlapped. A laminated body is produced (see FIG. 7).
The batch pressing is performed under conditions of a temperature of 80 to 250 ° C., a pressing pressure of 1 to 25 kgf / cm 2, and a pressing time (time from the start to the end of pressing) of 1 to 15 minutes.

(18)
Further, the through-hole conductor forming opening 110 penetrating all the layers of the laminate produced in the above (17) and the via hole forming opening 112 reaching the conductor circuit 84 located in one outermost layer of the laminate are formed by drilling. Form.
The formation of the through-hole conductor forming opening 110 is preferably performed within the processing conditions such that the drill rotation speed is 100 to 300 Krpm and the drill feed rate is 90 to 150 inch / min. It is desirable that the processing conditions for the opening 112 be substantially the same as the conditions in the above (7) (see FIG. 8).
The through-hole conductor forming opening 110 is, for example, a conductor circuit 80 that connects the second via hole 76 and the third via hole 78 in the first multilayer printed wiring board and the second via in the second multilayer printed wiring board. At least a conductor circuit 96 connecting the via hole 90 and the third via hole 94 is provided.

(19) In the same manner as (2) to (4), desmear treatment was performed to remove the resin residue remaining in the through-hole conductor formation opening 110 and the via hole formation opening 112, and the desmear treatment was performed. The copper foil surface of the substrate is subjected to an electrolytic copper plating process using the copper foil as a plating lead, and the electrolytic copper plating is completely filled in the through-hole conductor forming opening 110 and the via-hole forming opening 112, The hole conductor conductor 114 and the filled via 116 are formed.
The through-hole conductor conductor 114 is electrically connected to, for example, conductor circuits 80 and 96 that connect the second via hole and the third via hole in the multilayer printed wiring board, and is connected to the ground layer / layer provided in the interlayer insulating layer. The power supply layer is electrically connected to an external power supply through the through-hole conductor conductor 114.

(20) In the same manner as in (5) above, a resist layer is formed on one or both sides of the substrate, and after an exposure / development process, an etching solution made of cupric chloride or the like is applied to the resist non-formed portion, Etching is performed.
Thereafter, the resist is removed to form the outermost conductor circuit 118 including the through hole land and the via hole land on one or both sides of the substrate (see FIG. 9).

(21) Formation of Solder Resist Layer A solder resist layer was formed on the surface of the substrate located in the uppermost layer and the lowermost layer of the multilayered substrate obtained by the steps (1) to (20). A solder resist layer formed in a thickness of 20 to 30 μm is formed on the substrate by applying a film-formed solder resist or applying a varnish whose viscosity has been adjusted in advance.

  Next, after performing a drying treatment at 70 ° C. for 20 minutes and 100 ° C. for 30 minutes, a 5 mm thick soda lime glass base slope in which a circular pattern (mask pattern) of a solder resist opening is drawn by a chromium layer, The side on which the chromium layer was formed was brought into close contact with the solder resist layer and exposed to 1000 mJ / cm 2 of ultraviolet light, and DMTG developed. Further, heat treatment is performed at 120 ° C. for 1 hour and at 150 ° C. for 3 hours to form a solder resist layer 120 (thickness 20 μm) having an opening corresponding to the pad portion (opening diameter 200 μm).

In addition, before forming a soldering resist layer on the surface of the circuit board located in the uppermost layer and lowermost layer of a multilayer board | substrate, a roughening layer can also be provided as needed.
In this case, a mask layer in the form of a dry film made of a photosensitive resin is formed on the solder resist layer. A mask layer was formed to a thickness of 10 to 20 μm on the solder resist layer by applying a film-formed mask layer or applying a varnish whose viscosity was adjusted in advance.

  Next, after performing a drying process at 80 ° C. for 30 minutes, a 5 mm thick soda lime glass base slope in which a mask layer formation pattern (mask pattern) was drawn by the chromium layer was placed on the side on which the chromium layer was formed. It was made to adhere to the solder resist layer 120 and exposed to UV light of 800 mJ / cm 2 and DMTG developed. Furthermore, it heat-processed on 120 degreeC on the conditions for 1 hour, and formed the soldering resist layer (thickness 20 micrometers).

(22) Formation of Corrosion Resistant Layer Next, the substrate on which the solder resist layer 120 is formed is electroless nickel having a pH of 5 comprising nickel chloride 30 g / 1, sodium hypophosphite 10 g / 1, and sodium citrate 10 g / 1. It was immersed in a plating solution for 20 minutes to form a nickel plating layer having a thickness of 5 μm in the opening.
Further, the substrate was placed on an electroless gold plating solution composed of 2 g / 1 gold cyanide, 75 g / 1 ammonium chloride, 50 g / 1 sodium citrate, and 10 g / 1 sodium hypophosphite at 93 ° C. It was immersed for 2 seconds to form a 0.03 μm thick gold plating layer on the nickel plating layer, and a coated metal layer (not shown) composed of the nickel plating layer and the gold plating layer was formed.

(23) Formation of Solder Layer Then, the solder pad exposed from the opening of the solder resist layer 120 covering the uppermost multilayer circuit board is made of Sn / Pb solder or Sn / Ag / Cu having a melting point of about 183 ° C. A solder layer 122 was formed by printing a solder paste and reflowing at 183 ° C.

(Example 1-2)
A multi-layer print was performed by performing the same process as in Example 1-1 except that the semiconductor element having the mediating layer produced in the following steps (a) to (c) was embedded in the recess of the semiconductor element housing substrate. A wiring board was manufactured.

(a) A chromium thin film having a thickness of 0.1 μm and a copper thin film having a thickness of 0.5 μm on the entire surface of the semiconductor element having a protective film formed on the connection pads and the wiring pattern by sputtering. Two layers of layers are formed sequentially in a vacuum chamber.

(b) Thereafter, a resist layer using a dry film is formed on the thin film layer. A mask on which a portion for forming an intermediate layer is drawn is placed on the resist layer, and a resist non-formation portion is formed through exposure and development. Electrolytic copper plating is performed to provide a thickening layer (electrolytic copper plating film) having a thickness of 10 μm in the resist non-formation portion.

(c) After removing the plating resist with an alkaline solution or the like, the metal film under the plating resist is removed with an etching solution, thereby forming an intermediate layer on the pad of the semiconductor element.
As a result, a semiconductor element having a length of 5 mm × width of 5 mm and a thickness of 100 μm was obtained.

(Example 2-1)
In the step (6) , a multilayer printed wiring board was manufactured in the same manner as in Example 1-1 except that a taper of 85 degrees was formed on the side surface of the recess for housing the semiconductor element.

(Example 2-2)
In the step (6), the same procedure as in Example 1-1 was performed except that a taper of 85 degrees was formed on the side surface of the recess for housing the semiconductor element and a semiconductor element having a mediating layer was embedded.

(Comparative Example 1-1)
A printed wiring board in which a semiconductor element was embedded was manufactured by a method as described in JP-A-2001-267490. This printed wiring board does not include a plane layer as a ground layer / power supply layer on a substrate in which a semiconductor element is embedded.

(Comparative Example 2-1)
Example 1-1, except that a substrate formed only from a resin not containing a reinforcing material was used as a substrate for embedding a semiconductor element, a recess was formed in this substrate, and a semiconductor element having a columnar electrode was embedded in the recess. Similarly, a printed wiring board was produced. This printed wiring board does not include a plane layer as a ground layer / power supply layer on a substrate in which a semiconductor element is embedded.

(Comparative Example 2-2)
Example 1-1, except that a substrate formed only from a resin not containing a reinforcing material was used as a substrate for embedding a semiconductor element, a recess was formed in this substrate, and a semiconductor element having a mediating layer was embedded in the recess. Similarly, a printed wiring board was produced. This printed wiring board does not include a plane layer as a ground layer / power supply layer on a substrate in which a semiconductor element is embedded.

  Evaluation tests of the following items A to C were performed on the printed wiring boards produced according to the above-described examples, reference examples, and comparative examples. The results of each evaluation test are shown in Table 1.

A. Voltage Drop Test FIG. 11 shows the result of simulating the change over time of the voltage of the embedded semiconductor element. In the figure, the vertical axis represents the voltage supplied to the semiconductor element, the horizontal axis represents time, and the start-up time of the semiconductor element was 0 [s]. The time required for the voltage to recover to 0 V was measured, and the time (seconds) required for the recovery was shown in Table 1.

B. Resistance measurement test The resistance values of the conductor circuits connected to the semiconductor elements embedded in the multilayer printed wiring board were measured at three locations, and the average values thereof were shown in Table 1 as measured values.

C. Reliability test 130 ° C / 3min ℃ -55 ° C / 3min heat cycle test up to 2000 cycles, 1000 cycles to 200 cycles every 200 cycles, after leaving the test for 2 hours, continuity test And the presence or absence of a circuit having a resistance change rate exceeding 20% was measured, and the number of cycles exceeding 20% was compared.

From the above test results, it was confirmed that in each of the above examples, electrical connectivity and connection reliability were easily ensured as compared with each comparative example.
Similarly, it was confirmed that electrical characteristics were easily secured as compared with the comparative examples.

  As described above, the multilayer printed wiring board of the present invention can be applied to a semiconductor element mounted printed wiring board because it secures electrical connectivity and reliability and is hardly affected by signal delay.

The schematic sectional drawing for demonstrating the taper shape of the recessed part in which the semiconductor element of the multilayer printed wiring board concerning this invention is accommodated and embedded Schematic sectional view showing a columnar electrode formed on a pad of a semiconductor element in a multilayer printed wiring board according to the present invention Schematic sectional view showing a mediation layer formed on a pad of a semiconductor element in a multilayer printed wiring board according to the present invention (a)-(g) is schematic sectional drawing which shows a part of process of manufacturing the multilayer printed wiring board concerning Example 1-1 of this invention. (a)-(d) is schematic sectional drawing which shows a part of process of manufacturing the multilayer printed wiring board concerning Example 1-1 of this invention. Schematic sectional drawing which shows a part of process of manufacturing the multilayer printed wiring board concerning Example 1-1 of this invention. Schematic sectional drawing which shows a part of process of manufacturing the multilayer printed wiring board concerning Example 1-1 of this invention. Schematic sectional drawing which shows a part of process of manufacturing the multilayer printed wiring board concerning Example 1-1 of this invention. Schematic sectional drawing which shows a part of process of manufacturing the multilayer printed wiring board concerning Example 1-1 of this invention. Schematic sectional view showing a multilayer printed wiring board according to Example 1-1 of the present invention. The figure which shows the time-dependent change of the voltage of the semiconductor element embedded in the multilayer printed wiring board concerning this invention.

Explanation of symbols

30 First Insulating Resin Base Material 32 Resin Insulating Layer 34 Copper Foil 36 Via Hole Forming Opening 38 Electrolytic Copper Plating Layer 39 Via Hole 40 Second Insulating Resin Base Material 41 Conductor Circuit (Including Via Land)
42 Metal layer 43 Resin insulating layer 44 Copper foil 46 Opening for via hole formation 50 Conductor circuit (including via land)
52 Via hole 54 Recessed part 55A to 55C Semiconductor element 58 Columnar electrode 60 Semiconductor element mounting substrate 62, 64 Resin insulation layers 70, 72, 74 Via hole forming openings 76, 78, 82 Via holes 80, 84 Conductor circuit (including via land)
90, 92, 94, 98, 100 Via hole 96, 102 Conductor circuit (including via land)
106 Resin insulating layer 108 Copper foil 110 Through-hole conductor opening 112 Via-hole opening 114 Through-hole conductor 116 Via hole 118 Conductor circuit 120 Solder resist layer 122 Solder body 200 First multilayer printed wiring board 300 Second multilayer printed wiring Board

Claims (10)

Other resin insulation layers and conductor layers are alternately stacked on the resin insulation layer containing the semiconductor element, and electrical connection between these conductor layers penetrates the via hole formed in the resin insulation layer or all layers. A multilayer printed wiring board formed through a through-hole conductor layer formed by
It said semiconductor element is embedded in the resin insulating layer which is formed in the recess,
The resin insulating layer is formed of truncated conical filled vias formed from the upper and lower surfaces of the resin insulating layer and superimposed in opposite directions, and is formed between conductor layers formed on the upper and lower surfaces of the resin insulating layer. A first via hole is formed to electrically connect
In another resin insulation layer formed on the resin insulation layer containing the semiconductor element, a second via hole connected to the connection pad of the semiconductor element and a third via hole connected to the first via hole are provided. A via hole is formed, and further, a conductor circuit that electrically connects the second via hole and the third via hole, or a conductor circuit that electrically connects the second via hole to the through-hole conductor layer is formed. A multilayer printed wiring board. The other resin insulation layer is provided with a ground conductor layer or a power supply conductor layer, and the connection pads of the semiconductor element are electrically connected to the ground conductor layer or the power supply conductor layer via the conductor circuit. The multilayer printed wiring board according to claim 1, wherein the multilayer printed wiring board is connected to the board. The multilayer printed wiring board according to claim 2, wherein a plurality of the recesses are formed, and different semiconductor elements are embedded in each recess. The multilayer printed wiring board according to any one of claims 1 to 3 , wherein a metal layer is formed on a bottom surface of the recess, and a semiconductor element is embedded in the recess via the metal layer. . 5. The multilayer printed wiring according to claim 1, wherein a side surface of the concave portion is formed to have a taper such that the side surface becomes wider toward the upper side from the bottom surface. Board. 6. A mediation layer is formed on a connection pad of the semiconductor element, and the connection pad and the via hole are electrically connected through the mediation layer. A multilayer printed wiring board according to 1. Other resin insulation layers and conductor layers are alternately laminated on the resin insulation layer containing at least one semiconductor element, and electrical connection between these conductor layers is made via via holes formed in the resin insulation layer. In manufacturing the multilayer printed wiring board to be performed, during the manufacturing process, at least the following steps (a) to (f), that is,
(A) forming a filled via that penetrates the first insulating resin substrate and forming a metal layer on one surface of the first insulating resin substrate;
(B) a step of pressing and integrating the second insulating resin base material on one surface of the first insulating resin base material;
(C) Forming other filled vias that pass through the pressure-bonded second insulating resin base material and are electrically connected to the filled vias formed in the first insulating resin base material; Forming a first via hole and forming a conductor layer electrically connected to the first via hole on the surface of the second insulating resin base material,
(D) forming at least one recess reaching the surface of the metal layer from the other surface of the first insulating resin substrate;
(E) a step of accommodating a semiconductor element in the recess and bonding using an adhesive;
(F) After forming the resin insulating layer covering the semiconductor element, filled vias that penetrate the resin insulating layer and are electrically connected to the connection pads of the semiconductor element are formed. A via hole is formed, a filled via that penetrates the resin insulating layer and is electrically connected to the first via hole is formed, a third via hole is formed by these filled vias, and the second via hole is further formed. Forming a conductor circuit connecting the first via hole and the third via hole;
A method for producing a multilayer printed wiring board, comprising: Via holes or all layers in which other resin insulation layers and conductor layers are alternately laminated on a resin insulation layer containing at least one semiconductor element, and electrical connection between these conductor layers is formed in the resin insulation layer In manufacturing a multilayer printed wiring board performed through a through-hole conductor layer penetrating through, at least the following steps (a) to (i):
(A) forming a filled via that penetrates the first insulating resin substrate and forming a metal layer on one surface of the first insulating resin substrate;
(B) a step of pressing and integrating the second insulating resin base material on one surface of the first insulating resin base material;
(C) Forming other filled vias that pass through the pressure-bonded second insulating resin base material and are electrically connected to the filled vias formed in the first insulating resin base material; Forming a first via hole and forming a conductor circuit electrically connected to the first via hole on the surface of the second insulating resin base material,
(D) forming at least one recess reaching the surface of the metal layer from the other surface of the first insulating resin substrate;
(E) a step of accommodating a semiconductor element in the recess and bonding using an adhesive;
(F) After forming the resin insulating layer covering the semiconductor element, filled vias that penetrate the resin insulating layer and are electrically connected to the connection pads of the semiconductor element are formed. A via hole is formed, a filled via that penetrates the resin insulating layer and is electrically connected to the first via hole is formed, a third via hole is formed by these filled vias, and the second via hole is further formed. Producing a first multilayer printed wiring board formed with a conductor circuit connecting the first via hole and the third via hole;
(G) The process of producing a 2nd multilayer printed wiring board by repeating the process of said (a)-(f),
(H) a step of laminating the first multilayer printed wiring board and the second multilayer printed wiring board via a resin insulating layer;
(I) forming a through-hole conductor penetrating all the layers of the laminated multilayer printed wiring board and forming a conductor circuit electrically connected to the second via hole;
A method for producing a multilayer printed wiring board, comprising: 9. The multilayer printed wiring board according to claim 7, wherein the concave portion is formed by laser irradiation, and a side surface of the concave portion is formed to have a taper that becomes wider toward the upper side from the bottom surface. Method. The semiconductor element is characterized in that a columnar electrode or a mediation layer is formed in advance on the connection pad, and the connection pad and the second via hole are electrically connected via the columnar electrode or the mediation layer. The manufacturing method of the multilayer printed wiring board of Claim 7 or 8.

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