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JP4606783B2 - Semiconductor device - Google Patents

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Publication number
JP4606783B2
JP4606783B2 JP2004175836A JP2004175836A JP4606783B2 JP 4606783 B2 JP4606783 B2 JP 4606783B2 JP 2004175836 A JP2004175836 A JP 2004175836A JP 2004175836 A JP2004175836 A JP 2004175836A JP 4606783 B2 JP4606783 B2 JP 4606783B2
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semiconductor
semiconductor device
semiconductor element
interposer
semiconductor package
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JP2005064467A (en
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啓介 上田
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Shinko Electric Industries Co Ltd
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Shinko Electric Industries Co Ltd
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

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  • Wire Bonding (AREA)

Description

本発明は、半導体素子(チップ)と半導体パッケージとの間を電気的に接続するインターポーザを用いた半導体装置に関する。 The present invention relates to a semiconductor device using an interposer that electrically connects a semiconductor element (chip) and a semiconductor package .

情報社会の発達に伴い、半導体装置には処理速度の高速化が要求されている。このような要求に応ずるために、半導体装置内の配線の長さが短く済み、インダクタンス成分が小さくなるフリップチップ型の半導体装置が開発されている。   With the development of information society, semiconductor devices are required to increase processing speed. In order to meet such demands, flip chip type semiconductor devices have been developed in which the length of the wiring in the semiconductor device is reduced and the inductance component is reduced.

フリップチップ型の半導体装置は、図1にその一例を示すように、半導体素子1と、配線基板の形態をした半導体パッケージ10と、半導体パッケージ10の半導体素子が搭載された面の対応するパッドに、半導体素子1の電極を電気的に接続するはんだ等の金属バンプ2(以下、便宜上「内部接続端子」ともいう。)と、半導体素子1と半導体パッケージ10との間の空隙を充填するアンダーフィル樹脂8と、半導体パッケージ10の半導体素子1が搭載された側と反対側の面に設けられて、本装置30をマザーボード等の実装基板に電気的に接続するはんだバンプ等の外部接続端子11とを備えている。   As shown in FIG. 1, the flip-chip type semiconductor device includes a semiconductor element 1, a semiconductor package 10 in the form of a wiring board, and pads corresponding to the surface on which the semiconductor element of the semiconductor package 10 is mounted. Underfill for filling a gap between the semiconductor element 1 and the semiconductor package 10 and a metal bump 2 such as solder (hereinafter also referred to as “internal connection terminal” for convenience) for electrically connecting the electrodes of the semiconductor element 1. Resin 8 and external connection terminals 11 such as solder bumps which are provided on the surface of the semiconductor package 10 opposite to the side on which the semiconductor element 1 is mounted and electrically connect the device 30 to a mounting substrate such as a mother board It has.

図1に示すような半導体装置30では、その内部に温度変化が生じた場合に、半導体素子1と半導体パッケージ10との熱膨張係数が異なることにより、半導体素子1及び半導体パッケージ10はそれぞれ面内方向に異なる度合いで膨張又は収縮し、半導体素子1と半導体パッケージ10との間に熱歪が生じ、半導体素子1の電極及び半導体パッケージ10のパッドの位置が相対的に変わる。この際、これらの両方に固着されている内部接続端子2に変形が生じたり、また場合によっては亀裂が生じ、そのために半導体装置30の信頼性が低下するといった問題があった。   In the semiconductor device 30 as shown in FIG. 1, when a temperature change occurs in the semiconductor device 30, the semiconductor element 1 and the semiconductor package 10 are in-plane due to different thermal expansion coefficients of the semiconductor element 1 and the semiconductor package 10. It expands or contracts at different degrees in the direction, heat distortion occurs between the semiconductor element 1 and the semiconductor package 10, and the positions of the electrodes of the semiconductor element 1 and the pads of the semiconductor package 10 change relatively. At this time, there is a problem that the internal connection terminal 2 fixed to both of them is deformed or cracked in some cases, and the reliability of the semiconductor device 30 is lowered.

かかる問題に対処するために、他の従来例として図2(a)に示すような半導体装置が提案されている(例えば、特許文献1及び特許文献2参照。)。   In order to cope with such a problem, a semiconductor device as shown in FIG. 2A has been proposed as another conventional example (see, for example, Patent Document 1 and Patent Document 2).

この半導体装置40では、弾性シート6の半導体素子1の電極に対応する位置に、導体柱7が貫通して埋め込まれたインターポーザ5を、半導体素子1と半導体パッケージ10との間に介在させて、導体柱7の両端に接続された内部接続端子2及び3を介して半導体素子1の電極を半導体パッケージ10のパッドに電気的に接続している。   In this semiconductor device 40, an interposer 5 in which a conductor pillar 7 is embedded in a position corresponding to the electrode of the semiconductor element 1 of the elastic sheet 6 is interposed between the semiconductor element 1 and the semiconductor package 10, The electrodes of the semiconductor element 1 are electrically connected to the pads of the semiconductor package 10 through the internal connection terminals 2 and 3 connected to both ends of the conductor pillar 7.

図2(a)に示すような半導体装置40では、温度変化が生じると、図1に示した半導体装置と同様に、半導体素子1と半導体パッケージ10との間に熱歪が生じるが、この熱歪による変位をインターポーザ5が伸縮することにより吸収するので、内部接続端子2に変形や亀裂が生じにくくなる。しかしながら、この場合には、内部接続端子2は変形せずに導体柱7と一体化し、内部接続端子2が固着されている半導体素子1の電極と内部接続端子2との接合部近傍(以下、便宜上「内部接続端子2の基部」という。)を支点として動くために、内部接続端子2と導体柱7とのモーメントが大きくなる。この際、図2(a)中のA部を拡大した図2(b)に示すように、内部接続端子2の基部の近傍に位置する半導体素子1の内部の層間絶縁膜21や配線層22にモーメントによる応力が加わり、これらを損傷してしまう。   In the semiconductor device 40 as shown in FIG. 2A, when a temperature change occurs, thermal distortion occurs between the semiconductor element 1 and the semiconductor package 10 as in the semiconductor device shown in FIG. Since the interposer 5 absorbs the displacement due to the strain by expanding and contracting, the internal connection terminal 2 is less likely to be deformed or cracked. However, in this case, the internal connection terminal 2 is integrated with the conductor pillar 7 without being deformed, and in the vicinity of the junction between the electrode of the semiconductor element 1 to which the internal connection terminal 2 is fixed and the internal connection terminal 2 (hereinafter, For convenience, it is referred to as “base portion of the internal connection terminal 2”), and the moment between the internal connection terminal 2 and the conductor column 7 is increased. At this time, as shown in FIG. 2B in which the portion A in FIG. 2A is enlarged, the interlayer insulating film 21 and the wiring layer 22 inside the semiconductor element 1 located in the vicinity of the base portion of the internal connection terminal 2. Stress due to the moment is applied to it, and these are damaged.

層間絶縁膜21は一般に酸化シリコン(SiO2 )等からなるが、今後更なる処理速度の高速化を図るためには、層間絶縁膜21をいわゆるLow−k材料(低誘電率材料)に置き換えることが十分に予想される。しかしながら、一般に、Low−k材料は酸化シリコンと比べて強度的に低い(弱い)材料であるために、上述の熱歪による損傷といった問題が一層顕著に表れる。
WO96/09645号公報 特開平10−22351号公報
The interlayer insulating film 21 is generally made of silicon oxide (SiO 2 ) or the like, but in order to further increase the processing speed in the future, the interlayer insulating film 21 should be replaced with a so-called Low-k material (low dielectric constant material). Is fully expected. However, since the low-k material is generally a material having a lower strength (weaker) than silicon oxide, the above-described problem of damage due to thermal strain appears more remarkably.
WO96 / 09645 publication Japanese Patent Laid-Open No. 10-22351

本発明は、上記の従来技術における課題に鑑み創作されたもので、インターポーザを用いた半導体装置において、熱歪による半導体素子の内部の層間絶縁膜や配線層等の損傷を抑制し、ひいては半導体装置の信頼性の向上に寄与することを目的とする。 The present invention was created in view of the above-mentioned problems in the prior art, and in a semiconductor device using an interposer , damage to an interlayer insulating film, a wiring layer, and the like inside a semiconductor element due to thermal strain is suppressed, and thus the semiconductor device The purpose is to contribute to the improvement of reliability.

上記の従来技術の課題を解決するため、本発明の一形態によれば、半導体素子と、半導体パッケージと、前記半導体素子と前記半導体パッケージとの間に介在されたインターポーザであって、弾性を有する板状絶縁体と、該板状絶縁体の厚さ方向に貫通して埋め込まれた複数の導体と、前記板状絶縁体の前記半導体素子を搭載する側の面に設けられ、該半導体素子と同程度の熱膨張係数を有する第1のシート状部材とを有する当該インターポーザとを備え、前記半導体素子と前記半導体パッケージとが、前記複数の導体を介して電気的に接続されるとともに、前記半導体素子が第1の内部接続端子を介して当該導体の一端に接続されていることを特徴とする半導体装置が提供される。 In order to solve the above-described problems of the prior art, according to one aspect of the present invention, a semiconductor element, a semiconductor package, and an interposer interposed between the semiconductor element and the semiconductor package, and having elasticity A plate-like insulator, a plurality of conductors embedded in the thickness direction of the plate-like insulator, and a surface of the plate-like insulator on the side on which the semiconductor element is mounted; An interposer having a first sheet-like member having a similar thermal expansion coefficient, wherein the semiconductor element and the semiconductor package are electrically connected via the plurality of conductors, and the semiconductor A semiconductor device is provided in which an element is connected to one end of the conductor through a first internal connection terminal .

また、この半導体装置において、前記インターポーザは、前記板状絶縁体の前記半導体素子を搭載する側と反対側の面に設けられ、前記半導体パッケージと同程度の熱膨張係数を有する第2のシート状部材をさらに有していてもよい。 Further, in the semiconductor device, the interposer, the plate-like the insulator to the side for mounting the semiconductor element provided on a surface opposite to a second sheet having a thermal expansion coefficient comparable to the semiconductor package You may have a member further.

本発明の一形態に係る半導体装置の構成によれば、半導体素子と半導体パッケージとの間に介在されたインターポーザにおいて、その板状絶縁体の半導体素子を搭載する側の面に、該半導体素子と同程度の熱膨張係数を有する第1のシート状部材が設けられている。従って、この半導体装置において温度変化が生じると、半導体素子と第1のシート状部材との間には熱膨張係数の差がほとんどないため、半導体素子と第1のシート状部材は、対向するそれぞれの面に平行な方向に一様に膨張又は収縮し、これらの間に熱歪はほとんど生じない。そのため、板状絶縁体の厚さ方向に貫通して埋め込まれた各導体は、当該導体の一端が第1の内部接続端子を介して接続される側の半導体素子の面を支点として動くことはなく、半導体素子の面に大きなモーメントやせん断力が発生しにくくなり、第1のシート状部材より板状絶縁体側の部分の導体が、第1のシート状部材と板状絶縁体との界面を支点として動くことになる。これにより、半導体素子に加わる応力が緩和され、半導体素子の内部の層間絶縁膜や配線層は損傷しにくくなるので、半導体装置の信頼性を向上させることができる。 According to the configuration of the semiconductor device according to one aspect of the present invention , in the interposer interposed between the semiconductor element and the semiconductor package, the semiconductor element is mounted on the surface of the plate-like insulator on the side on which the semiconductor element is mounted. A first sheet-like member having a similar thermal expansion coefficient is provided. Therefore, when a temperature change occurs in this semiconductor device, there is almost no difference in thermal expansion coefficient between the semiconductor element and the first sheet-like member, so that the semiconductor element and the first sheet-like member face each other. It expands or contracts uniformly in the direction parallel to the plane of the film, and there is almost no thermal strain between them. Therefore, each of the conductors embedded through the thickness direction of the plate-like insulator, the one end of the conductor moves the surface of the semiconductor device side connected via the first internal connection terminals as a fulcrum Therefore, a large moment or shearing force is hardly generated on the surface of the semiconductor element, and the conductor on the plate-like insulator side from the first sheet-like member forms the interface between the first sheet-like member and the plate-like insulator. It will move as a fulcrum. Thereby, the stress applied to the semiconductor element is relaxed, and the interlayer insulating film and the wiring layer inside the semiconductor element are hardly damaged, so that the reliability of the semiconductor device can be improved.

また、上記の形態に係る半導体装置において、インターポーザの板状絶縁体の、半導体素子を搭載する側と反対側の面に、半導体パッケージと同程度の熱膨張係数を有する第2のシート状部材を設けた場合には、この第2のシート状部材と半導体パッケージは、対向するそれぞれの面に平行な方向に一様に膨張又は収縮するために、これらの間も熱歪がほとんど生じない。そのため、板状絶縁体の厚さ方向に貫通して埋め込まれた各導体は、各々の他端が接続される側の半導体パッケージの面を支点として動くことはなく、第2のシート状部材より板状絶縁体側の部分の導体が、第2のシート状部材と板状絶縁体との界面を支点として動くことになる。これにより、半導体パッケージに加わる応力も同時に緩和され、半導体パッケージの内部の多層構造も損傷しにくくなるので、さらに半導体装置の信頼性を向上させることができる。 In the semiconductor device according to the above aspect, a second sheet-like member having a thermal expansion coefficient comparable to that of the semiconductor package is provided on the surface of the interposer plate-like insulator opposite to the side on which the semiconductor element is mounted. When provided, the second sheet-like member and the semiconductor package are uniformly expanded or contracted in the direction parallel to the opposing surfaces, so that almost no thermal distortion occurs between them. Therefore, each conductor embedded penetrating in the thickness direction of the plate-like insulator does not move with the surface of the semiconductor package on the side to which the other end is connected as a fulcrum. The conductor on the plate-like insulator side moves with the interface between the second sheet-like member and the plate-like insulator as a fulcrum. Thereby, the stress applied to the semiconductor package is also alleviated and the multilayer structure inside the semiconductor package is hardly damaged, so that the reliability of the semiconductor device can be further improved.

以下、添付した図面を参照して、本発明の実施の形態について説明する。   Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

図3は、本発明の一実施形態に係るインターポーザ及びこれを用いた半導体装置の構成を断面図の形態で示したものである。   FIG. 3 is a cross-sectional view showing a configuration of an interposer and a semiconductor device using the interposer according to an embodiment of the present invention.

本実施形態に係る半導体装置50は、例えば図2(b)に示したような多層構造を有する半導体素子51と、配線基板の形態を有する半導体パッケージ60と、半導体素子51と半導体パッケージ60との間に介在されたインターポーザ55と、半導体素子51とインターポーザ55との間、及びインターポーザ55と半導体パッケージ60との間をそれぞれ電気的に接続するはんだバンプ等の内部接続端子52及び53と、半導体素子51とインターポーザ55との間及びインターポーザ55と半導体パッケージ60との間にそれぞれ充填されたアンダーフィル樹脂58及び59と、半導体パッケージ60の、インターポーザ55が実装されている側と反対側の面に設けられて、本装置50をマザーボード等の実装基板に電気的に接続するはんだボール等の外部接続端子61とを備えている。 The semiconductor device 50 according to the present embodiment includes, for example, a semiconductor element 51 having a multilayer structure as shown in FIG. 2B, a semiconductor package 60 having the form of a wiring board, and the semiconductor element 51 and the semiconductor package 60. An interposer 55 interposed therebetween, internal connection terminals 52 and 53 such as solder bumps for electrically connecting between the semiconductor element 51 and the interposer 55, and between the interposer 55 and the semiconductor package 60, and the semiconductor element between 51 and interposer 55, and the underfill resin 58 and 59 which are filled respectively between the interposer 55 and the semiconductor package 60, the semiconductor package 60, on the surface opposite to the side where the interposer 55 is mounted The device 50 is electrically connected to a mounting board such as a mother board. And an external connection terminal 61 such as solder balls.

また、インターポーザ55は、絶縁性の弾性シート56(板状絶縁体)と、この弾性シート56の半導体素子51を搭載する側の面に設けられた剛性シート70(第1のシート状部材)と、弾性シート56の半導体素子51の電極に対応する部分においてその厚さ方向に貫通して埋め込まれた複数の導体柱57とを有している。弾性シート56は、エポキシ樹脂、ポリイミド系樹脂等の高分子材料からなる。また、剛性シート70は半導体素子51と同程度の熱膨張係数を有する。例えば、半導体素子51を構成する主な材料がシリコン(Si)である場合には、剛性シート70は、Si、ガラス、セラミックス、36合金(Fe(鉄)−36重量%Ni(ニッケル))、42合金(Fe−42重量%Ni)等の材料からなる。このインターポーザ55は、例えば、レーザの照射により弾性シート56に貫通孔を形成し、めっき法を用いて銅(Cu)又は錫銅(SnCu)を貫通孔に埋め込んで導体柱57を形成した後に、導体柱57の配置に対応させて導体柱57と接触しない程度の直径の貫通孔を設けた剛性シート70を弾性シート56の一方の面に接着させることにより得ることができる。 The interposer 55 includes an insulating elastic sheet 56 (plate-like insulator) and a rigid sheet 70 (first sheet-like member) provided on the surface of the elastic sheet 56 on which the semiconductor element 51 is mounted. The elastic sheet 56 has a plurality of conductor columns 57 that are embedded in the thickness direction at portions corresponding to the electrodes of the semiconductor element 51 . The elastic sheet 56 is an epoxy resin, a polymer material such as polyimide resin. The rigid sheet 70 has a thermal expansion coefficient comparable to that of the semiconductor element 51 . For example, when the main material constituting the semiconductor element 51 is silicon (Si), the rigid sheet 70 is made of Si, glass, ceramics, 36 alloy (Fe (iron) -36 wt% Ni (nickel)), It consists of materials, such as 42 alloy (Fe-42 weight% Ni). The interposer 55 is formed, for example, by forming a through hole in the elastic sheet 56 by laser irradiation and embedding copper (Cu) or tin copper (SnCu) in the through hole using a plating method to form the conductor column 57 . by bonding the rigid sheet 70 having a through-hole of the degree of diameter not to correspond to the arrangement of the conductor posts 57 contact the conductor columns 57 on one surface of the elastic sheet 56 can be obtained.

図3に示す半導体装置50は、内部接続端子52及び53をはんだバンプとし、外部接続端子61をはんだボールとした場合は、以下のようにして製造することができる。   The semiconductor device 50 shown in FIG. 3 can be manufactured as follows when the internal connection terminals 52 and 53 are solder bumps and the external connection terminal 61 is a solder ball.

まず、内部接続端子52を設けた半導体素子51と内部接続端子53を設けた半導体パッケージ60との間にインターポーザ55を挟んでリフロー炉により加熱処理を行い、半導体素子51、インターポーザ55及び半導体パッケージ60を接合する。次に、半導体素子51とインターポーザ55の間の空隙、及びインターポーザ55と半導体パッケージ60の間の空隙にアンダーフィル樹脂58及び59を充填し、恒温炉により加熱処理を行い、アンダーフィル樹脂58及び59を硬化させる。最後に、半導体パッケージ60の、半導体素子が搭載された側と反対側の面の所定の位置に、外部接続端子61を配置し、再度リフロー炉により加熱処理を行い、半導体パッケージ60と外部接続端子61を接合することにより、半導体装置50を得ることができる。   First, an interposer 55 is sandwiched between the semiconductor element 51 provided with the internal connection terminal 52 and the semiconductor package 60 provided with the internal connection terminal 53, and heat treatment is performed in a reflow furnace, whereby the semiconductor element 51, the interposer 55, and the semiconductor package 60. Join. Next, the underfill resins 58 and 59 are filled in the gap between the semiconductor element 51 and the interposer 55 and the gap between the interposer 55 and the semiconductor package 60, and heat treatment is performed in a constant temperature furnace. Is cured. Finally, the external connection terminal 61 is arranged at a predetermined position on the surface of the semiconductor package 60 opposite to the side on which the semiconductor element is mounted, and heat treatment is performed again in a reflow furnace, so that the semiconductor package 60 and the external connection terminal By bonding 61, the semiconductor device 50 can be obtained.

また、内部接続端子52は、はんだバンプに限らず、例えば、めっき法によりCuを成長させて柱状に形成した突起、ワイヤボンディング法を利用して形成した金(Au)からなるスタッドバンプに代替可能である。これらの場合、内部接続端子52及び53にペースト状のはんだ又は導電性粒子を含む樹脂を塗布することにより、上述の製造方法と同じ製造工程を経て半導体装置50を得ることができる。   Further, the internal connection terminal 52 is not limited to a solder bump, but can be replaced by, for example, a protrusion formed by growing Cu by a plating method and a stud bump made of gold (Au) formed by using a wire bonding method. It is. In these cases, the semiconductor device 50 can be obtained through the same manufacturing process as that described above by applying paste-like solder or resin containing conductive particles to the internal connection terminals 52 and 53.

本実施形態に係るインターポーザ55の構成によれば、インターポーザ55の半導体素子51を搭載する側の面に、半導体素子51と同程度の熱膨張係数を有する剛性シート70を設けている。このインターポーザ55を用いた半導体装置50では、半導体装置50の内部に温度変化が生じた際に、剛性シート70と半導体パッケージ60との熱膨張係数はある程度の差があるため、これらの間では熱歪が生じるが、半導体素子51と剛性シート70との熱膨張係数は差がほとんどないため、これらの間では半導体素子51の面内方向に一様に膨張又は収縮するために熱歪がほとんど生じない。従って、内部接続端子52と導体柱57は一体化して内部接続端子52の基部を支点として動くことはなく、剛性シート70より下の部分の導体柱57が剛性シート70と弾性シート56との界面を支点として動くことになる。これにより、半導体素子51に加わる応力が緩和され、半導体素子51の内部の層間絶縁膜や配線層は損傷しにくくなるので、半導体装置50の信頼性を向上させることができる。   According to the configuration of the interposer 55 according to the present embodiment, the rigid sheet 70 having the same thermal expansion coefficient as that of the semiconductor element 51 is provided on the surface of the interposer 55 on the side where the semiconductor element 51 is mounted. In the semiconductor device 50 using the interposer 55, when a temperature change occurs in the semiconductor device 50, the thermal expansion coefficient between the rigid sheet 70 and the semiconductor package 60 has a certain degree of difference. Although distortion occurs, there is almost no difference in the coefficient of thermal expansion between the semiconductor element 51 and the rigid sheet 70. Therefore, thermal expansion is almost generated between the semiconductor element 51 and the rigid sheet 70 because the semiconductor element 51 is uniformly expanded or contracted in the in-plane direction. Absent. Therefore, the internal connection terminal 52 and the conductor column 57 are integrated and do not move with the base portion of the internal connection terminal 52 as a fulcrum, and the conductor column 57 below the rigid sheet 70 is the interface between the rigid sheet 70 and the elastic sheet 56. Will move as a fulcrum. Thereby, the stress applied to the semiconductor element 51 is relaxed, and the interlayer insulating film and the wiring layer inside the semiconductor element 51 are hardly damaged, so that the reliability of the semiconductor device 50 can be improved.

本発明者は、上述の効果を確認すべく、シミュレーションにより半導体装置の内部に生じる応力の解析を行った。   In order to confirm the above-described effect, the present inventor analyzed the stress generated in the semiconductor device by simulation.

本シミュレーションではシミュレーションソフトとしてABAQUS6.31を使用した。本実施形態に係る半導体装置50(図3)と従来例に係る半導体装置40(図2)との内部応力の違いを比較するために、これら2つの半導体装置の各々について、シミュレーションモデル(以下、単に「モデル」という。)を作成した。各々のモデルにおいて、内部接続端子の材料はCuとし、導体柱の材料はSnCuとし、半導体パッケージのコア部の材料は36合金とし、弾性シートの材料はエポキシ樹脂とした。また、本実施形態に係る半導体装置50のモデルにおいて、剛性シートはSiとした。これら2つのモデルについて、内部応力が発生しない温度をアンダーフィル樹脂のキュア温度である180℃とし、温度を常温である25℃にした際の内部応力の解析を行った。   In this simulation, ABAQUS6.31 was used as simulation software. In order to compare the difference in internal stress between the semiconductor device 50 according to the present embodiment (FIG. 3) and the semiconductor device 40 according to the conventional example (FIG. 2), a simulation model (hereinafter referred to as a simulation model) is used for each of these two semiconductor devices. Simply called "model"). In each model, the material of the internal connection terminals was Cu, the material of the conductor pillars was SnCu, the material of the core portion of the semiconductor package was 36 alloy, and the material of the elastic sheet was epoxy resin. In the model of the semiconductor device 50 according to the present embodiment, the rigid sheet is Si. With respect to these two models, the internal stress was analyzed when the temperature at which no internal stress was generated was 180 ° C., which is the cure temperature of the underfill resin, and the temperature was 25 ° C., which is normal temperature.

図4はシミュレーション結果を示す断面図であり、図中、(a)は本実施形態に係る半導体装置のモデルによるシミュレーション結果、(b)は従来例に係る半導体装置のモデルによるシミュレーション結果をそれぞれ示している。ここでは、図4(a),(b) に示す各部位に、図3及び図2に示した各部位と対応する参照番号を付している。 4A and 4B are cross-sectional views showing simulation results, in which FIG. 4A shows a simulation result based on the model of the semiconductor device according to the present embodiment, and FIG. 4B shows a simulation result based on the model of the semiconductor device according to the conventional example. ing. Here, reference numerals corresponding to the respective parts shown in FIGS. 3 and 2 are given to the respective parts shown in FIGS. 4 (a) and 4 (b).

従来例では(図4(b)参照)、内部接続端子2及び導体柱7が、半導体素子1の半導体パッケージ60と対向する側の面(以下、便宜上「半導体素子1の主面」という。)に対して垂直方向から角度をなして、熱歪による変位に追随している。これに対して、本発明では(図4(a)参照)、剛性シート70より半導体パッケージ70側の導体柱57は熱歪による変位に追随しているが、剛性シート70より半導体素子51側の部分の導体柱57及び内部接続端子52は、半導体素子51の主面に対して垂直に固着された状態を保持しており、熱歪による変位にほとんど追随していない。これらの結果から、従来例に係る半導体装置では、導体柱7及び内部接続端子2がほぼ一体化して内部接続端子2の基部を支点として動き、本実施形態に係る半導体装置では、導体柱57及び内部接続端子52は一体化して動かず、剛体シート70と弾性シート56との界面付近を支点として、剛体シート70より半導体パッケージ70側の部分の導体柱57が動くことが確認された。   In the conventional example (see FIG. 4B), the internal connection terminal 2 and the conductor pillar 7 are surfaces on the side facing the semiconductor package 60 of the semiconductor element 1 (hereinafter referred to as “main surface of the semiconductor element 1” for convenience). The angle from the vertical direction is followed to the displacement due to thermal strain. On the other hand, in the present invention (see FIG. 4A), the conductor pillar 57 on the semiconductor package 70 side of the rigid sheet 70 follows the displacement due to thermal strain. The partial conductor pillars 57 and the internal connection terminals 52 are held in a state of being fixed perpendicular to the main surface of the semiconductor element 51 and hardly follow displacement due to thermal strain. From these results, in the semiconductor device according to the conventional example, the conductor pillar 7 and the internal connection terminal 2 are substantially integrated and move with the base portion of the internal connection terminal 2 as a fulcrum. In the semiconductor device according to the present embodiment, the conductor pillar 57 and It was confirmed that the internal connection terminal 52 does not move as a unit, and the conductor column 57 in the portion closer to the semiconductor package 70 than the rigid sheet 70 moves using the vicinity of the interface between the rigid sheet 70 and the elastic sheet 56 as a fulcrum.

これら2つのモデルのシミュレーションの結果の違いをより明確にするために、それぞれのモデルについてインターポーザから内部接続端子及び半導体素子に加わる応力をそれぞれ解析した。図5はその解析結果を示したものであり、右側に本実施形態に係る半導体装置のモデルの応力解析の結果を、左側に従来例に係る半導体装置のモデルの応力解析の結果をそれぞれ示している。   In order to clarify the difference between the simulation results of these two models, the stress applied from the interposer to the internal connection terminal and the semiconductor element was analyzed for each model. FIG. 5 shows the result of the analysis. The result of the stress analysis of the model of the semiconductor device according to this embodiment is shown on the right side, and the result of the stress analysis of the model of the semiconductor device according to the conventional example is shown on the left side. Yes.

これらの応力解析の結果によれば、本実施形態に係る半導体装置のモデルでは、従来例に係る半導体装置のモデルと比較して、パッケージ側から内部接続端子に加わる等価応力は約87%低減し、また、半導体素子に加わる最大応力は約63%低減することが確認された。つまり、本インターポーザの介在により、外部から半導体素子に加わる応力の殆どが絶たれることが確認された。   According to the results of these stress analyses, the equivalent stress applied to the internal connection terminal from the package side is reduced by about 87% in the model of the semiconductor device according to the present embodiment compared to the model of the semiconductor device according to the conventional example. In addition, it was confirmed that the maximum stress applied to the semiconductor element was reduced by about 63%. That is, it was confirmed that most of the stress applied to the semiconductor element from the outside is removed by the interposer.

このように、本実施形態に係るインターポーザを用いた半導体装置では、従来例に係るインターポーザを用いた半導体装置よりも内部接続端子及び半導体素子に加わる応力が大幅に軽減されることがシミュレーションにより明らかになった。なお、少なくとも弾性シートより剛性シートの熱膨張係数の方が半導体素子の熱膨張係数に近ければ、従来例の半導体装置よりもある程度の応力の低減を図ることができる。   As described above, the simulation clearly shows that the stress applied to the internal connection terminals and the semiconductor element is significantly reduced in the semiconductor device using the interposer according to the present embodiment as compared with the semiconductor device using the interposer according to the conventional example. became. If at least the thermal expansion coefficient of the rigid sheet is closer to the thermal expansion coefficient of the semiconductor element than the elastic sheet, the stress can be reduced to some extent as compared with the conventional semiconductor device.

図6〜図8は、上述した実施形態に係るインターポーザ及び半導体装置(図3)の各種変形例を示したものである。   6 to 8 show various modifications of the interposer and the semiconductor device (FIG. 3) according to the above-described embodiment.

図6は、上述した実施形態の第1の変形例に係るインターポーザ及びこれを用いた半導体装置の構成を断面図の形態で示したものである。   FIG. 6 shows the configuration of an interposer according to a first modification of the above-described embodiment and a semiconductor device using the same in the form of a cross-sectional view.

本変形例の半導体装置50aは、図3に示した半導体装置50と比較して、インターポーザ55aが複数の絶縁性の樹脂フィルム56aを積層して形成され、各々の樹脂フィルムに56aの厚さ方向に貫通して形成された導体柱を積み重ねて1本の導体柱57aを構成した点において異なる。このインターポーザ55aは、図3に示したインターポーザ55と同様に、各々の弾性フィルム又はシート56aの同じ位置に導体柱を形成し、弾性フィルム56aを重ねて熱圧着することにより得ることができる。本変形例の半導体装置50aについても、図3に示した半導体装置50と同様の効果を奏することが理解されるであろう。   Compared with the semiconductor device 50 shown in FIG. 3, the semiconductor device 50 a of this modification is formed by stacking a plurality of insulating resin films 56 a on the interposer 55 a, and each resin film has a thickness direction of 56 a. Are different in that one conductor pillar 57a is formed by stacking conductor pillars formed so as to penetrate through the conductor pillars. Similar to the interposer 55 shown in FIG. 3, the interposer 55a can be obtained by forming a conductive column at the same position of each elastic film or sheet 56a, and superposing the elastic films 56a and thermocompression bonding. It will be understood that the semiconductor device 50a of this modification also has the same effect as the semiconductor device 50 shown in FIG.

図7は、第2の変形例に係るインターポーザ及びこれを用いた半導体装置の構成を断面図の形態で示したものである。   FIG. 7 is a cross-sectional view showing the configuration of an interposer according to a second modification and a semiconductor device using the interposer.

本変形例の半導体装置50bは、第1の変形例の半導体装置50aと比較して、インターポーザ55bが複数の絶縁性の弾性フィルム56bを積層して形成されている点において同じであるが、導体柱57aではなく、半導体素子51の電極パッドの配置と半導体パッケージ60の電極パッドの配置とのずれを調整する配線層57bを設けた点において異なる。このインターポーザ55bは、各々の弾性フィルム56bの所望の位置に、導体柱と、インターポーザ55bに組み込まれた際に導体柱間を電気的に接続する導体パターンとを形成し、弾性フィルム56bを重ねて熱圧着することにより得ることができる。本変形例の半導体装置50bについても、図3に示した半導体装置50と同様の効果を奏することが理解されるであろう。   The semiconductor device 50b according to the present modification is the same as the semiconductor device 50a according to the first modification in that the interposer 55b is formed by laminating a plurality of insulating elastic films 56b. The difference is that a wiring layer 57b for adjusting a shift between the arrangement of the electrode pads of the semiconductor element 51 and the arrangement of the electrode pads of the semiconductor package 60 is provided instead of the pillar 57a. This interposer 55b forms conductor columns and conductor patterns that electrically connect the conductor columns when they are incorporated in the interposer 55b at desired positions of the respective elastic films 56b, and overlaps the elastic films 56b. It can be obtained by thermocompression bonding. It will be understood that the semiconductor device 50b of this modification also has the same effect as the semiconductor device 50 shown in FIG.

図8は、第3の変形例に係るインターポーザ及びこれを用いた半導体装置の構成を断面図の形態で示したものである。   FIG. 8 shows the configuration of an interposer according to a third modification and a semiconductor device using the interposer in the form of a cross-sectional view.

本変形例の半導体装置50cは、図3に示した半導体装置50と比較して、インターポーザ55cの半導体素子51を搭載する側と反対側の面にも剛性シート71を設けた点において異なる。この場合、剛性シート71の材料としては半導体パッケージ60と同程度の熱膨張係数を有する材料を選択する。例えば、半導体パッケージ60のコア材が42合金(Fe−42重量%Ni)である場合、剛性シート71の材料もコア材と同様に42合金とすればよい。半導体パッケージのコア材としては、この他に36合金(Fe−36重量%Ni)が挙げられる。   The semiconductor device 50c of this modification is different from the semiconductor device 50 shown in FIG. 3 in that a rigid sheet 71 is provided on the surface of the interposer 55c opposite to the side on which the semiconductor element 51 is mounted. In this case, a material having a thermal expansion coefficient comparable to that of the semiconductor package 60 is selected as the material of the rigid sheet 71. For example, when the core material of the semiconductor package 60 is 42 alloy (Fe-42 wt% Ni), the material of the rigid sheet 71 may be 42 alloy similarly to the core material. Another example of the core material of the semiconductor package is 36 alloy (Fe-36 wt% Ni).

このようにすれば、半導体素子51と剛性シート70との間だけでなく、剛性シート71と半導体パッケージ60との間も熱歪がほとんど生じなくなる。つまり、内部接続端子52,53及び導体柱57が一体化して内部接続端子52の基部と内部接続端子53の基部(即ち、内部接続端子53と半導体パッケージ60との接合部)を支点として動くことはなく、剛性シート70及び71との間の部分の導体柱57が、剛性シート70と弾性シート56との界面、及び弾性シート56と剛体シート71との界面を支点として動くことになる。これにより、半導体パッケージ60の半導体素子51が搭載された側の面に加わる応力も緩和され、半導体パッケージ60の内部の多層構造も損傷しにくくなるので、半導体装置50cの信頼性をさらに向上させることができる。   In this way, thermal distortion hardly occurs not only between the semiconductor element 51 and the rigid sheet 70 but also between the rigid sheet 71 and the semiconductor package 60. That is, the internal connection terminals 52 and 53 and the conductor column 57 are integrated to move using the base portion of the internal connection terminal 52 and the base portion of the internal connection terminal 53 (that is, the joint portion between the internal connection terminal 53 and the semiconductor package 60) as a fulcrum. Rather, the portion of the conductive column 57 between the rigid sheets 70 and 71 moves with the interface between the rigid sheet 70 and the elastic sheet 56 and the interface between the elastic sheet 56 and the rigid sheet 71 as fulcrums. As a result, the stress applied to the surface of the semiconductor package 60 on which the semiconductor element 51 is mounted is relieved, and the multilayer structure inside the semiconductor package 60 is less likely to be damaged, thereby further improving the reliability of the semiconductor device 50c. Can do.

従来形の一例としてのフリップチップ型半導体装置の構成を示す断面図である。It is sectional drawing which shows the structure of the flip chip type semiconductor device as an example of the conventional type. 従来形の他の例としてのフリップチップ型半導体装置の構成を示す断面図である。It is sectional drawing which shows the structure of the flip chip type semiconductor device as another example of the conventional type. 本発明の一実施形態に係るインターポーザ及びこれを用いた半導体装置の構成を示す断面図である。It is sectional drawing which shows the structure of the interposer which concerns on one Embodiment of this invention, and a semiconductor device using the same. 図3の実施形態に係る半導体装置のモデルによるシミュレーション結果を、従来例に係る半導体装置の場合と対比させて示した断面図である。It is sectional drawing which showed the simulation result by the model of the semiconductor device which concerns on embodiment of FIG. 3 in contrast with the case of the semiconductor device which concerns on a prior art example. 図4のモデルを用いてシミュレーションを行ったときの各部の応力解析の結果を示す図である。It is a figure which shows the result of the stress analysis of each part when simulation is performed using the model of FIG. 図3の実施形態の第1の変形例に係るインターポーザ及びこれを用いた半導体装置の構成を示す断面図である。It is sectional drawing which shows the structure of the interposer which concerns on the 1st modification of embodiment of FIG. 3, and a semiconductor device using the same. 図3の実施形態の第2の変形例に係るインターポーザ及びこれを用いた半導体装置の構成を示す断面図である。It is sectional drawing which shows the structure of the interposer which concerns on the 2nd modification of embodiment of FIG. 3, and a semiconductor device using the same. 図3の実施形態の第3の変形例に係るインターポーザ及びこれを用いた半導体装置の構成を示す断面図である。It is sectional drawing which shows the structure of the interposer which concerns on the 3rd modification of embodiment of FIG. 3, and a semiconductor device using the same.

符号の説明Explanation of symbols

50,50a,50b,50c…半導体装置、
51…半導体素子(チップ)、
52,53…内部接続端子(はんだバンプ)、
55,55a,55b,55c…インターポーザ、
56…弾性シート(板状絶縁体)、
56a,56b…樹脂フィルム、
57,57a…導体柱、
57b…配線層、
58,59…アンダーフィル樹脂、
60…半導体パッケージ、
61…外部接続端子、
70,71…剛性シート(シート状部材)。
50, 50a, 50b, 50c ... semiconductor device,
51. Semiconductor element (chip),
52, 53 ... internal connection terminals (solder bumps),
55, 55a, 55b, 55c ... interposer,
56 ... elastic sheet (plate-like insulator),
56a, 56b ... resin film,
57, 57a ... Conductor column,
57b ... wiring layer,
58, 59 ... Underfill resin,
60 ... Semiconductor package,
61 ... External connection terminal,
70, 71: Rigid sheet (sheet-like member).

Claims (6)

半導体素子と、
半導体パッケージと、
前記半導体素子と前記半導体パッケージとの間に介在されたインターポーザであって、弾性を有する板状絶縁体と、該板状絶縁体の厚さ方向に貫通して埋め込まれた複数の導体と、前記板状絶縁体の前記半導体素子を搭載する側の面に設けられ、該半導体素子と同程度の熱膨張係数を有する第1のシート状部材とを有する当該インターポーザとを備え、
前記半導体素子と前記半導体パッケージとが、前記複数の導体を介して電気的に接続されるとともに、前記半導体素子が第1の内部接続端子を介して当該導体の一端に接続されていることを特徴とする半導体装置。
A semiconductor element;
A semiconductor package;
An interposer interposed between the semiconductor element and the semiconductor package, having a plate-like insulator having elasticity, and a plurality of conductors embedded in the thickness direction of the plate-like insulator, The interposer having a first sheet-like member provided on the surface of the plate-like insulator on the side on which the semiconductor element is mounted and having a thermal expansion coefficient comparable to that of the semiconductor element;
The semiconductor element and the semiconductor package are electrically connected via the plurality of conductors, and the semiconductor element is connected to one end of the conductor via a first internal connection terminal. A semiconductor device.
前記インターポーザは、前記板状絶縁体の前記半導体素子を搭載する側と反対側の面に設けられ、前記半導体パッケージと同程度の熱膨張係数を有する第2のシート状部材をさらに有することを特徴とする請求項1に記載の半導体装置。   The interposer further includes a second sheet-like member provided on a surface of the plate-like insulator opposite to the side on which the semiconductor element is mounted and having a thermal expansion coefficient comparable to that of the semiconductor package. The semiconductor device according to claim 1. 前記板状絶縁体は、複数の樹脂フィルムが積層されてなり、前記導体は、前記複数の樹脂フィルムの各々の厚さ方向に貫通して形成され積み重ねられた複数の導体柱からなることを特徴とする請求項に記載の半導体装置。 The plate-like insulator is formed by laminating a plurality of resin films, and the conductor is composed of a plurality of conductive pillars that are formed through and stacked in the thickness direction of each of the plurality of resin films. The semiconductor device according to claim 1 . 前記半導体素子を構成する主たる材料はシリコンからなり、前記第1のシート状部材はシリコン、ガラス、セラミックス、36合金及び42合金のうちいずれかにより形成されていることを特徴とする請求項1から3のいずれか一項に記載の半導体装置。   2. The main material constituting the semiconductor element is made of silicon, and the first sheet-like member is formed of any one of silicon, glass, ceramics, 36 alloy and 42 alloy. 4. The semiconductor device according to any one of 3. さらに、前記半導体パッケージが第2の内部接続端子を介して前記導体の他端に接続され、前記半導体素子と前記インターポーザとの間、及び前記インターポーザと前記半導体パッケージとの間にそれぞれ樹脂が充填されていることを特徴とする請求項1に記載の半導体装置。 Further, the semiconductor package is connected to the other end of the conductor via a second internal connection terminal, and resin is filled between the semiconductor element and the interposer, and between the interposer and the semiconductor package, respectively. The semiconductor device according to claim 1, wherein: 前記半導体パッケージの、前記インターポーザが実装されている側と反対側の面に、複数の外部接続端子が設けられていることを特徴とする請求項1に記載の半導体装置。   The semiconductor device according to claim 1, wherein a plurality of external connection terminals are provided on a surface of the semiconductor package opposite to a side on which the interposer is mounted.
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