JP4611666B2 - Scan conversion device and scan conversion method - Google Patents

Description

  The present invention relates to a scan conversion apparatus and a scan conversion method, and more particularly, generates interlaced scan data and sequential scan data synchronized with each other in order to simultaneously drive each of display apparatuses using different scanning methods. The present invention relates to a scan conversion device and a scan conversion method.

  Polymorphic display devices (eg, TVs, computer monitors, etc.) typically use one of two display methods: an interlaced scanning method and a sequential scanning method. Of these two methods, the image is separated into a number of scan lines. In the interlace scanning method, odd-numbered scan lines and even-numbered scan lines are alternately displayed.

The odd-numbered scan lines of the video are also called odd fields or top fields. An even-numbered scan line of an image is also called an even field or a bottom field.
The top field and the bottom field are alternately displayed at a high speed so as to be seen as one synthesized screen.
Images are displayed one by one by the sequential scanning method. That is, all scan lines are displayed.

Interlaced scan data is based on fields or frames. The following is an example of frame-based interlaced scanning data. Here, T indicates a top field, B indicates a bottom field, and t indicates time.
T _t , B _t , T _{t + 1} , B _{t + 1} , T _{t + 2} , B _{t + 2,.} . .
As described above, the frame-based interlaced scanning data includes the top field and the bottom field of the same time video. If the top field and the bottom field at the same time are combined, a frame of sequentially scanned data is generated.

The following is an example of field-based interlaced scanning data.
T _t , B _{t + 1} , T _{t + 2} , B _{t + 3,.} . .

When compared with frame-based interlaced scanning data, field-based interlaced scanning data does not include the same time top field and bottom field.
Combining the top and bottom fields of field-based interlaced scan data to produce frames of progressive scan data can reduce the quality of low-quality video, especially when there is a significant amount of motion in the video. Reduce.

Different video generation apparatuses (for example, a computer, a DVD player, a video tape player, etc.) generate video data by either the interlace scanning method or the sequential scanning method.
The video generator cannot generate video data in a manner consistent with the scanning scheme expected by the desired display device.

  Therefore, the technical problem to be solved by the present invention is an apparatus and method capable of converting progressive scan data into interlaced scan data and / or an apparatus capable of converting interlaced scan data into progressive scan data. And to provide a way.

A scanning change device for achieving the technical problem includes a first converter for converting input interlaced scanning data into sequential scanning data, and interleaving the sequential scanning data output from the first converter. A second converter for converting into scan data.
The first converter converts the interlaced scan data into the progressive scan data based on a selected technique among different techniques.

  The different techniques include spatial interpolation techniques including performing spatial interpolation on a current field of the interlaced scan data to generate a complementary scan data field indicating a frame of the progressive scan data along with the current field; An alternative field output technique for alternately outputting two consecutive fields of the input interlaced scan data in units of scan lines in order to generate a frame of progressive scan data; and The current field, at least one previous field and at least one successive field are combined with temporal interpolation to perform directional adaptive spatial interpolation, and complementary to indicate the frame of the progressive scan data along with the current field And a spatial / temporal interpolation technique that includes generating a field of scan data.

The second converter is output from the first converter so that the interlaced scan data output from the second converter can be synchronized with the progressive scan data output from the first converter. The progressive scan data is converted into the interlaced scan data.
The second converter includes a counter for generating the count value at a sequential scanning frequency so that the count value is related to a period of the sequential scanning data, a memory, and the sequential scanning data based on an output of the counter A write address generator for generating a write address for writing to the memory, and a read address for outputting the sequential scan data written in the memory as the interlaced scan data based on the output of the counter A read address generator.

The second converter further includes an address controller for supplying one of a write address generated from the write address generator and a read address generated from the read address generator to the memory.
The address controller controls the supply of the write address and the read address so that interlaced scan data for one scan line can be read from the memory while sequential scan data for one scan line is written to the memory. .

  The counter generates the count value related to different periods of the sequential scanning data based on whether the sequential scanning data is converted from any one of an odd field and an even field of the interlaced scanning data. .

The counter generates the count value associated with an odd scan line and a next even scan line of the sequential scan data when the sequential scan data is converted from an odd field of the interlaced scan data, and When scan data is converted from the even field of the interlaced scan data, the count value associated with the even scan line and the next odd scan line of the sequential scan data is generated.
The counter generates the count value associated with two consecutive scan lines of the progressive scan data.

  The write address generator generates a first write address associated with the first scan line of the two consecutive scan lines based on the count value, and based on the count value A second write address generator for generating a second write address associated with a second scan line of the two consecutive scan lines, and the sequential scan data is stored in an odd field and an even field of the interlaced scan data. A write address controller that selectively outputs one of the first write address and the second write address based on which one of them is converted.

  The write address controller receives a control signal indicating which one of the odd and even fields of the interlaced scan data is converted from the progressive scan data.

  The read address generator converts the count value into a read address associated with one scan line of the interlaced scan data.

  The second converter includes a memory, a timer that displays the timing of two consecutive scanning lines of the progressive scan data, and a control signal that instructs the two consecutive scanning lines to be written into the memory. A write address generator for receiving, and a read address generator for generating a read address so as to read a scan line written from the memory, the write address generator displaying based on the timing displayed by the timer The read address generator starts generating the read address based on the timing indicated by the timer.

  A scanning conversion apparatus for achieving the technical problem includes an interlaced-sequential converter and a sequential-interlaced converter connected to the interlaced-sequential converter, and the sequential-interlaced converter. Generates interlaced scan data synchronized with the progressive scan data output by the interlace-sequential converter.

  A sequential-interlaced scan data converter for achieving the technical problem includes a counter for generating the count value at a sequential scan frequency so that the count value is related to a period of the sequential scan data, a memory, A write address generator that generates a write address for writing the progressive scan data to the memory based on the output of the counter, and a scan data that skips the sequential scan data written to the memory based on the output of the counter. And a read address generator for generating a read address for output as.

  The sequential-interlaced scan data converter includes an address controller for supplying one of a write address generated from the write address generator and a read address generated from the read address generator to the memory. Is further provided.

  The address controller supplies the write address and the read address so that interlaced scan data for one scan line can be read from the memory while sequential scan data for one scan line is written to the memory. Control.

  The counter generates the count value related to different periods of the sequential scanning data based on whether the sequential scanning data is converted from any one of an odd field and an even field of the interlaced scanning data. .

The counter generates the count value associated with an odd scan line and a next even scan line of the sequential scan data when the sequential scan data is converted from an odd field of the interlaced scan data, and When scan data is converted from the even field of the interlaced scan data, the count value associated with the even scan line and the next odd scan line of the sequential scan data is generated.
The counter generates the count value associated with two consecutive scan lines of the progressive scan data.

  The write address generator generates a first write address associated with the first scan line of the two consecutive scan lines based on the count value, and based on the count value A second write address generator for generating a second write address associated with a second scan line of the two consecutive scan lines, and the sequential scan data is stored in an odd field and an even field of the interlaced scan data. A write address controller that selectively outputs one of the first write address and the second write address based on which one of them is converted.

  The write address controller receives a control signal indicating which one of the odd and even fields of the interlaced scan data is converted from the progressive scan data.

  The read address generator converts the count value into a read address associated with one scan line of the interlaced scan data.

  A sequential-interlaced scan data converter for achieving the technical problem comprises a memory, a timer for displaying the timing of two consecutive scanning lines of sequential scanning data, and the two consecutive scanning lines. A write address generator for receiving a control signal instructing to write to the memory; and a read address generator for generating a read address so as to read a scan line written from the memory, the write address generator comprising: A write address for the displayed scan line is generated based on the timing displayed by the timer, and the read U-address generator starts generating the read address based on the timing displayed by the timer.

A scan conversion method for achieving the technical problem includes a step of converting input interlaced scan data into sequential scan data and a step of converting the progressive scan data into output interlaced scan data.
The output interlaced scan data is synchronized with the progressive scan data.

  The method of converting the progressive scan data to the interlaced scan data to achieve the technical problem includes generating the count value at a sequential scan frequency so that the count value is related to a period of the progressive scan data; Based on the count value, generating a write address for storing the progressive scan data in a memory, and generating a read address for outputting the sequential scan data written in the memory as interlaced scan data Storing the progressive scan data in the memory based on the generated write address, and outputting the sequential scan data from the memory based on the generated read address.

  Since the scanning conversion apparatus and the scanning conversion method according to the present invention simultaneously drive display apparatuses using different scanning methods, it is possible to generate interlaced scanning data and sequential scanning data synchronized with each other.

For a full understanding of the invention, its operational advantages, and the objectives achieved by the practice of the invention, reference should be made to the accompanying drawings and the accompanying drawings illustrating preferred embodiments of the invention. Must.
Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. The same reference numerals in the drawings denote the same members.

  FIG. 1 shows a scan converter according to an embodiment of the present invention. As shown in FIG. 1, an interlaced-to-progressive converter (IPC) 210 receives interlaced sequential data IDATA generated by a video generation device (eg, a video tape player, a DVD player, etc.) at a terminal 201. And the interlaced scan data IDATA is sequentially converted into scan data PDATA. The generated progressive scan data PDATA output via the terminal 203 forms one output of the scan converter 200.

  A progressive-to-interlaced converter (PIC) 220 converts the generated sequential scanning data PDATA into interlaced scanning data IDATA '. The generated interlaced scan data IDATA 'output through the terminal 205 forms one output of the scan converter 200.

  Since the generated interlaced scan data IDATA ′ is generated from the generated progressive scan data PDATA, the synchronization existing between the generated progressive scan data PDATA and the generated interlaced scan data IDATA ′ is the original This is superior to the synchronization existing between the interlaced scan data IDATA and the generated progressive scan data PDATA.

  FIG. 2 shows the relationship between the original interlaced scan data IDATA of FIG. 1 and the generated sequential scan data PDATA. Referring to FIG. 2, the current field X of the interlaced scan data IDATA includes scan lines i-1, i + 1 with respect to the reference scan line i, and the previous field X-1 includes scan lines i-2, i, i + 2. The next field X + 1 includes scan lines i-2, i, i + 2.

  Also, after being converted by the IPC 210, a progressive scan data frame having scan lines i-2 ', i-1', i 'is generated. The relationship between the scan lines of the interlaced scan field and the scan lines of the progressive scan frame will be described in more detail by explaining the operation of the IPC 210.

IPC of scan converter
FIG. 3 shows an example of the IPC shown in FIG. As shown in FIG. 3, the IPC 210 includes a first memory 2, a second memory 4, and a third memory 6. The first memory 2 stores a continuous line (or data) of the current field of the interlaced scan data IDATA. For example, using the relationship set in FIG. 2, the first memory 2 starts from the field X with at least the (i−1) th scanning line (i−1th scanning line data) and the (i + 1) th scanning line (i + 1th scanning line). Scan line data) is stored respectively.

  The second memory 4 and the third memory 6 store at least one scan line between consecutive scan lines stored in the first memory 2 for the previous field and the next field, respectively. For example, using the relationship set in FIG. 2, each of the second memories 4 stores at least the i-th scanning line from the field X-1, and the third memory 6 stores at least the i-th scanning line from the field X + 1. Save.

The number of scan lines stored by the first memory 2 through the third memory 6 will become more apparent from the detailed description below.
The interpolator 10 uses two consecutive scan lines stored in the first memory 2 to generate an interpolated scan line. Interpolation performed by the interpolator 10 is spatial interpolation. A simple spatial interpolation will be described in detail with reference to FIG. 4A using the relationship set in FIG. FIG. 4A shows a pixel P (n, i-1, X). Here, n indicates the position of the scanning line, i-1 indicates the scanning line located on the pixel, and X indicates the field including the pixel.

4A further shows the corresponding pixel P (n, i + 1, X) along the direction (dir0) of the next scan line i + 1 of field X. FIG. As shown in FIG. 4A, the direction (dir0) is perpendicular to the scan line. If the scan data is pixel P (n, i-1, X) and pixel P (n, i + 1, X), it becomes interpolated sequential scan data. (N, i ′) is located on the scanning line i ′ in the direction (dir0).
For example, P (n, i ′) = (P (n, i−1, X) + P (n, i + 1, X)) / 2.

Motion Adaptive Converter The motion adaptive converter 12 of FIG. 3 receives scan lines stored in the first memory 2 and receives scan lines stored in the second and third memories 4 and 6. The motion adaptive converter 12 analyzes the current amount of motion in the video represented by the interlaced scanning data, and generates pixel data for the sequential scanning lines based on the analysis. Next, this process will be described in detail.

The motion adaptive converter 12 will be described as follows. x ⁿ _k (i, j) represents the k-th pixel value in the block (i, j) of the n-th field. X ⁿ (i, j) represents the pixel value of the block (i, j) in the nth field. FIG. 4B shows an example of the block (i, j).

The motion adaptive converter 12 performs the previous field x ⁿ⁻¹ _k (i, j) and the next field x ^{n + 1} _k (i, j) by the block-like method shown in FIG. SAD (Sum of Absolute Difference) is calculated through motion detection.

動き適応変換器１２は数式３の標準によって動き検出スレッショルドを決定する。

The motion adaptive converter 12 determines the motion detection threshold according to the standard of Equation 3.

Here, T _M1 and T _M2 are design values set by the designer through empirical research. For example, _TM1 can be set to 8 and _TM2 can be set to 16. STD _m (i, j) is a standard deviation of 4 * 8 pixels covering the pixel of interest in the 2 upper blocks and 2 lower blocks of the current field X according to FIG. STD _m (i, j) is called a so-called simplification change.

If SAD (i, j) ≧ TH _M (i, j), the pixel of interest has a global motion and a motion change value mj (i, j) = 1, otherwise m _j (I, j) = 0.
The motion adaptive converter 12 then derives the space-time interpolation variable defined by equations 5-14.

Connection with the above _variables, a design value set by the system designer based on empirical studies the _{T l1,} T l2, T _s1 and _{T s2.} For example, T _l1 can be set to 50, T _l2 can be set to 306, T _s1 can be set to 10, and T _s2 can be set to 18. The variable S (i, j) indicates the complexity of the video in the block (i, j).

A relatively large variable S (i, j) indicates a more complex image, and a relatively small variable S (i, j) indicates a less complex image. M _l (i, j) is a 4-bit quantized value, and 0 ≦ Ml (i, j) ≦ 31. (Numbers greater than 31 are rounded down to 31.)

The last space-time interpolation pixel value Y _ST (i, j) is determined by a weighted average of Y _S (i, j) and Y _T (i, j) expressed in Equation 15.

Here, Y _S (i, j) is an interpolated pixel value, and Y _T (i, j) is a temporally calculated pixel value, as will be described in detail below. . Y _T (i, j) is expressed as follows.

Motion adaptive converter 12 space based on the amount of motion in the video - performing one of a temporal interpolation Y _ST and temporal interpolation Y _T.
If there are no motion, or if little, it is applied temporal interpolation Y _T, the space otherwise - time interpolation Y _ST is applied.

More specifically, if one or more of the adjacent motion oscillators m _j (i, j) are “1”, space-time interpolation Y _ST (i, j) is applied. If none of the adjacent motion oscillators m _j (i, j) is “1”, the time interpolation Y _T (i, j) is applied.

  Referring to FIG. 4C, the shaded block covering the block (i, j) containing the pixel of interest represents a possible example of an adjacent block. Therefore, the motion oscillator of such an adjacent block is regarded as an adjacent motion oscillator.

Next, generation of a directional interpolation pixel value will be described in detail. First, vertical low-pass filtering g _n (i, j) is performed to remove vertical noise as shown in FIG.

The 7-way correlation is calculated by weighted SADs having weights (1, 1, 2, 1, 1) on the filtered data as shown in FIG. 4E, where each SAD is dir = 0, ± 1, ± 2. , ± 3 having WSAD _dir (i, j).
The global and local top directions are given as follows.

The reliability improvement for DIR _GLOBAL and DIR _LOCAL is obtained by Equation 20 and Equation 21.

The pixel value interpolated by DIR _GLOBAL is indicated by direction “A”, and the upper / lower pixel values are indicated by direction “B” and direction “C” by DIR _LOCAL , respectively. The motion adaptive converter 12 determines a directional interpolated pixel value Y _{DIR_OPT} as shown in Equation 22.

  In order to protect the vertical edge of the image, the measured value of the vertical edge D is calculated through FIG.

The edge-oriented adaptive spatial interpolation pixel value Y _S is obtained by a weighted average of Y _{DIR_OPT} and Y _DIR0 . This means that the soft-decision between the pixel value having the optimal direction and the pixel value having the vertical direction is determined by the motion adaptive converter 12 according to equations 24 and 25.

Here, T ₁ and T ₂ are design values set by the designer through empirical research. For example, T ₁ can be set to 434 and T ₂ can be set to 466.
Referring to FIG. 3, the multiplexer (MUX) 14 receives the scanning line from the first memory, receives the output signal of the interpolator 10, and receives the output signal of the motion adaptive converter 12.

Controller 16 controls MUX 14 so that one of the signals received by MUX 14 can be selectively output. The controller 16 controls the operation of the motion adaptive converter 12.
The controller 16 controls the MUX 14 and the motion adaptive converter 12 based on the received video information. The video information is header information obtained from the video stream received by the scan conversion device.

  As is well known, the video information is interlaced scan data IDATA, whether it is the first field of the video stream, whether it is a top field or bottom field, or frame-based or field-based interlaced scanning data. Instruct whether or not there is.

  Controller 16 receives video information for current field X, next field X + 1, and previous field X-1. When the field just received is the first field of the video stream, the controller 16 interrupts the processing performed by the motion adaptive converter 12. This is because the motion adaptive controller 12 does not have sufficient information.

  As described in the background art, frame-based or field-based interlaced scan data alternately indicates a top field and a bottom field. However, substantially received interlaced scan data misses one field, such as two or more top fields or two or more bottom fields, received sequentially. When the current field precedes or lags the field of the same form (for example, the top field or the bottom field), the controller 16 outputs the scan line i-1 output from the first memory 2 to the generated sequential scan data PDATA. Output as scan line (i-1) '. The output outputted from the interpolator 10 is outputted as the scanning line i ′ of the sequential scanning data PDATA, and the scanning line i + 1 outputted from the first memory 2 is subsequently outputted as the scanning line i + 1 of the sequential scanning data PDATA. The MUX 14 is controlled to output as Generating the i-th scanning line by such a method is called a BOB technique. That is, with this BOB technique, a frame of progressive scan data is generated from the current field and the field of complementary scan data generated by the interpolator 10. A complementary field along with the current field indicates a frame of sequentially scanned data.

  If the video stream is frame-based interlaced scan data without losing the previous field or the next field, the controller 16 receives the i-th scan line of the X-1 field received from the second memory 4. And the motion adaptive converter 12 is controlled so that the motion adaptation process cannot be performed.

  The controller 16 outputs the scanning line i-1 output from the first memory 2 as the scanning line i-1 of the generated sequential scanning data PDATA, and the i-th scanning line output from the X-1 field. The sequential scanning data PDATA is output as a scanning line i ′. Further, the MUX 14 is controlled so that the scanning line i + 1 output from the first memory 2 is sequentially output as the scanning line i + 1 of the scanning data PDATA. Generating the i'th scan line by such a method is called a weave technique.

  As an example, assume that the previous field X-1 and the current field X are identical in time. However, the next field X + 1 is a field related to the same field in time as the current field. In this situation, the next field is selected for output. That is, in the weave technique, two consecutive fields of interlaced scan data related to the same point in time are alternately output on a scan line basis to generate a frame of scan data sequentially.

  If the video stream is field-based interlaced scan data without losing the previous field or the next field, the controller 16 controls the motion adaptive converter 12 to perform a motion adaptation process.

  The controller 16 outputs the scanning line i-1 output from the first memory 2 as the scanning line i-1 of the sequential scanning data PDATA, and outputs the output of the motion adaptive converter 12 to the scanning line i 'of the sequential scanning data PDATA. Output as. Next, the MUX 14 is controlled so that the scanning line i + 1 output from the first memory 2 is sequentially output as the scanning line i + 1 of the scanning data PDATA. Generating the i'th scan line by such a method is called a motion adaptation technique. That is, with the motion adaptation technique, a frame of progressive scan data is generated from the current field and the field of complementary scan data generated by the motion adaptive converter 12. A complementary field along with the current field indicates a frame of sequentially scanned data.

When the interlaced scan data IDATA is frame-based, generating the progressive scan data PDATA by the weave technique generates virtually all frames of data with no motion artifacts.
However, when the interlaced scan data IDATA is field-based, the weave technique produces an undesired bad video when a substantial amount of time occurs in the motion of the video.

  Such a phenomenon must be particularly noted when a still image is displayed. By using motion adaptation techniques for field-based interlaced scan data, a much improved image can be obtained. Furthermore, when there is insufficient data to perform a weave or motion adaptation technique, a frame of progressive scan data PDATA can still be generated by the BOB technique.

FIG. 5 shows a second embodiment of the IPC 210 shown in FIG. The IPC 210 includes first to third memories 2, 4, and 6 for storing scan lines as described in the embodiment of FIG.
The controller 26 controls the operations of the spatial processor 20, the temporal processor 22 and the mode device 24 based on the same video information received by the controller 16 shown in FIG.

The spatial processor 20 receives the scanning line output from the first memory 2 and directly outputs the spatial interpolation or scanning line under the control of the controller 26.
When performing the spatial interpolation process, the spatial processor 20 performs the interpolation performed by the interpolator 10 or generates the spatially interpolated pixel value Y _S generated as described for the motion adaptive converter 12. To do. The spatial processing performed is controlled by the controller 26.

The time processor 22 receives scanning lines from the first to third memories 2, 4, 6. The time processor 22 outputs the i-th scan line of the X-1 field received from the second memory 4 under the control of the controller 26, or was generated as described above for the motion adaptive converter 12. and outputs a temporally interpolated pixel value Y _T.

  The mode device 24 uses the output of the spatial processor 20 and the output of the time processor 22 to generate the progressive scan data PDATA by any one of BOB, weave and motion adaptation techniques. The mode device 24 operates with the spatial processor 20 and the time processor 22 under the control of the controller 26.

  If the current field precedes or follows the field having the same configuration, the controller 26 turns off the time processor 22 and allows the mode device 24 to output the output received from the time processor 20. To control.

  Further, the controller 26 controls the spatial processor 20 so that the scanning line i-1 received from the first memory 2 can be output as the scanning line i-1 of the generated sequential scanning data PDATA. Next, the spatial processor 20 performs control so that the scanning lines generated by the same spatial interpolation as the spatial interpolation performed by the interpolator 10 can be sequentially output as the scanning line i of the scanning data PDATA. Further, the spatial processor 20 performs control so that the scanning line i + 1 output from the first memory 2 can be sequentially output as the scanning line i + 1 of the scanning data PDATA. Therefore, the frame of progressive scan data is generated by the BOB technique.

  If the video stream is frame-based interlaced scan data without losing the previous field or the next field, the controller 26 can output the scan line received from the first memory 2 so as to output the scan line. And the spatial processor 20 is controlled so that the scanning line i received from the second memory 4 can be output.

  The controller 26 outputs the scanning line i-1 output from the first memory 2 as the scanning line i-1 of the sequential scanning data PDATA, and then outputs the scanning line i output from the X-1 field to the sequential scanning data. Output as the PDATA scanning line i ′. Thereafter, the mode device 24 is controlled so that the scanning line i + 1 output from the first memory 2 is sequentially output as the scanning line i + 1 of the scanning data PDATA. Therefore, the frame of progressive scan data is generated by the weave technique.

If the video stream is field-based interlaced scan data without losing the previous or next field, the controller 26 can output the scan line received from the first memory 2 and the space. The spatial processor 20 is controlled so that the automatically interpolated pixel value Y _S can be generated.

The controller 26 also controls the time processor 22 so that a temporally interpolated pixel value YT can be generated. Controller 26 combines the spatially interpolated pixel value Y _S and the temporally interpolated pixel value Y _T and is spatially-temporally interpolated in the manner described for motion adaptive converter 12. The mode device 24 is controlled so that the pixel value _YST can be generated.

The controller 26 outputs the scan line i-1 output from the first memory 2 as the scan line i-1 of the sequential scan data PDATA, and the spatially-temporally interpolated pixel value _YST as the sequential scan data. Output as the PDATA scanning line i ′. Thereafter, the mode device 24 is controlled so that the scanning line i + 1 output from the first memory 2 is sequentially output as the scanning line i + 1 of the scanning data PDATA. Accordingly, a frame of progressive scan data is generated by a motion adaptation technique.

  Thus, the embodiment of FIG. 5 generates progressive scan data PDATA by BOB, weave and motion adaptation techniques to obtain the same advantages as described with reference to FIG.

PIC of scan converter
The PIC 220 will be described in detail with reference to FIGS. FIG. 6 shows an example of the PIC 220. The PIC 220 includes a synchronization signal generator 690 used for TV. As illustrated, the synchronization signal generator 690 generates a field identification signal field_id, an odd horizontal synchronization signal odd_hsync, and an even horizontal synchronization signal even_hsync.

  The field identification signal field_id indicates whether the current interlaced scan data field generated from the sequential scan data PDATA is an even field or an odd field. FIG. 7C shows an example of the field identification signal field_id. As shown in FIG. 7C, an odd field is generated when the field identification signal field_id is high, and an even field is generated when the field identification signal field_id is low. FIG. 7B shows the horizontal synchronization signal hsync (p) sequentially. Each pulse of the sequential horizontal synchronization signal hsync (p) represents one scanning line of pixel data. FIG. 7A shows the vertical synchronization signal vsync (p) sequentially. Each pulse of the sequential vertical sync signal vsync (p) indicates the start of a new frame of sequentially scanned pixel data.

  Accordingly, the number of pulses of the sequential horizontal synchronization signal hsync (p) between the continuous sequential vertical synchronization signals vsync (p) indicates the number of scanning lines in the frame of the sequential scanning data.

  FIG. 7E shows an example of the odd horizontal synchronization signal odd_hsync (p), and FIG. 7F shows the even horizontal synchronization signal even_hsync (p) derived from the sequential horizontal synchronization signal hsync (p) of FIG. 7B. ) Is an example. As shown in the figure, the odd and even horizontal synchronization signals odd_hsync (p) and even_hsync (p) sequentially have half the frequency of the horizontal synchronization signal hsync (p).

  Furthermore, the odd horizontal synchronization signal odd_hsync (p) and the even horizontal synchronization signal are sequentially shifted from each other by about one cycle of the horizontal synchronization signal hsync (p). As shown, the odd horizontal synchronization signal includes a pulse at the beginning of the odd field generation period, and the even horizontal synchronization signal includes a pulse from the start of the even field generation period.

  Before describing the structure of the PIC, the horizontal and vertical blanking intervals of interlaced scanning data and sequential scanning data will be described. Scanning one horizontal line of interlaced data is performed at 13.5 MHz. While scanning a line with interlaced scan data at a frequency of 13.5 MHz, 858 clock pulses of the video data clock are generated. Of the 858 clock pulses, the first 138 clock pulses indicate a horizontal blanking interval. The time corresponding to the horizontal blanking interval is the time taken for the scanner to move from the end of one scan line to the start of the next scan line.

  The next 720 clock pulse indicates the pixel being scanned along the scan line. The sequential horizontal scanning frequency is twice as high as the interlaced horizontal scanning frequency. That is, the sequential horizontal scanning frequency is 27 MHz. Thus, 2 × 858 progressive scan video clock pulses are generated at the same time. This is the same as scanning two sequential horizontal scanning lines at the same time as one interlaced horizontal scanning line is scanned.

  Referring again to FIG. 6, the reset MUX 610 selectively outputs one of the odd horizontal synchronization signal odd_hsync and the even horizontal synchronization signal even_hsync as a reset signal based on the field identification signal field_id. The counter 620 counts the pulses of the first clock signal CLK1, and sequentially generates clock pulses at the video data rate of the scan data (for example, 858 pulses per scan line) until it is reset by the reset signal. The count value is related to the period of the progressive scan data.

  Although the embodiments of the present invention are described as a video data rate of 858 clock pulses per scan line, those skilled in the art to which the present invention pertains will understand that the present invention applies to other video data rates. Wax

  FIG. 7D shows an example of the first clock signal CLK1. As understood from FIG. 7D and as described above, the counter 620 is reset only by the pulse of the odd horizontal synchronization signal odd_hsync during the odd field generation period indicated by the field identification signal field_id. Similarly, during the even field generation period indicated by the field identification signal field_id, the counter 620 is reset only by the pulse of the even horizontal synchronization signal odd_hsync.

  FIG. 7G shows the signal output by counter 620 for the scan line while odd fields are generated. Referring to FIG. 7G, the counter 620 sequentially generates a count value cnt at a rate of the scanning frequency. The count value cnt is related to the cycle of the progressive scan data. That is, the counter 620 generates a count value associated with each cycle of the sequential scan data depending on which one of the odd field and the even field of the scan data is converted.

  For example, when the sequential scan data is converted from the odd field of the scan data, the counter 620 generates a count value cnt associated with the odd scan line and the next even scan line of the scan data, and the counter 620 sequentially When the scan data is converted from the even field of the interlaced scan data, the count value cnt associated with the even scan line and the next odd scan line of the sequential scan data is generated. In this manner, the counter 620 serves as a timer that indicates the timing of two consecutive scanning lines of sequential scanning data.

  The subtractor that generates the pixel value receives the count value cnt generated by the counter 620. The pixel value is the same as the count value cnt minus 138 (ie, the horizontal blanking interval). Thus, the pixel value indicates the pixel of the display that scans sequentially as the scan line is scanned. FIG. 7H shows the pixel value output from the subtracter.

  The second MUX 6307 selectively outputs one of the pixel value and “0” based on the control signal received from the first comparator 6301. The first comparator 6301 determines whether the count value cnt is equal to 138 or greater than 859. If the count value cnt is equal to 138 or greater than 859, the first comparator 6301 generates a control signal (eg, 1) so that the second MUX 6307 outputs a pixel value. If the count value cnt is less than 138 or equal to or greater than 859, the first comparator 6301 generates a control signal (eg, 0) so that the second MUX 6307 outputs a “0” value. . FIG. 7I shows the output of the second MUX 6307.

  The first latch 6309 generates the write address WA based on the signal output from the second MUX 6307. In particular, the first latch 6309 stores the output of the second MUX 6307 according to the first clock signal CLK1. FIG. 7L shows the write address WA generated by the first latch 6309. When an odd field scan line is generated, a write address is generated for the beginning of two consecutive scan lines. Since a “0” value is generated when the count value cnt exceeds 858, the write address becomes 0 for the next scan line after the counter 620 is reset. The same operation occurs when generating scan lines for even fields. However, since the counter 620 is reset by the even horizontal synchronization signal even_hsync instead of the odd horizontal synchronization signal odd_sync, the scan line for generating the write address generates the write address when generating the write address for the odd field. Is shifted by one scanning line with respect to the scanning line.

  The count value cnt output from the first counter 620 is received by the calculation circuit 6503. The calculation circuit 6503 subtracts 276 from the count value cnt and divides the subtraction result by 2 to generate an interlaced pixel value. The value 276 indicates two horizontal blanking intervals (2 × 138 = 276). The reason for dividing the subtraction result when scanning the interlaced data line is to generate a value indicating the pixel value. FIG. 7J shows interlaced pixel values.

  The third MUX 6505 selectively outputs one of the interlaced pixel value and the zero value based on the control signal received from the second comparator 6501. The second comparator 6501 determines whether the count value cnt is equal to or larger than 276. If the count value cnt is equal to or greater than 276, the second comparator 6501 generates a control signal (eg, 1), and the third MUX 6505 outputs the interlaced pixel value. If the count value cnt is equal to or not larger than 276, the second comparator 6501 generates a control signal (eg, 0), so that the third MUX 6505 outputs a 0 value. FIG. 7K shows the output of the third MUX 6505.

  The second latch 6507 generates a read address RA based on the signal output from the third MUX 6505. In particular, the second latch 6507 stores the output of the third MUX 6507 according to the second clock signal CLK2. The second clock signal CLK2 has clock pulses at the video data rate of the interlaced scan data. FIG. 7M shows the second clock signal CLK2. The frequency of the second clock signal CLK2 shown in FIG. 7 (M) is half the frequency of the first clock signal CLK1 (p) shown in FIG. 7 (D). FIG. 7N shows the read address RA generated by the second latch 6507. As shown in FIG. 7N, even if the third MUX 6507 generates a number such as 358, 358.5, 359, 359.5, 360, the second latch 6507 has a small number of interlaced pixel values. Truncate the part. As a result, the second latch 6507 generates the same read address for two consecutive values of sequential pixel values and one value of interlaced pixel values. That is, the second latch 6507 generates the read address RA at the interlaced video data rate.

  The fourth MUX 6701 selectively outputs one of the write address received from the first latch 6309 and the read address received from the second latch 6507 based on the write signal WR received from the memory 6703. FIG. 7O shows an example of a write signal. As shown in FIG. 7O, the write signal WR is a clock signal having the same frequency as the first clock signal CLK1. When the write signal WR is high, the fourth MUX 6701 outputs the write address, and the memory 6703 stores the pixels of the scan data sequentially. When the write signal WR is low, the fourth MUX 6701 outputs the same read address for two consecutive pulses of the write signal WR, and the memory 6703 skips the stored pixel data in response to the read address. And output as scan data IDATA '.

  Although the above description has focused on the generation of scan lines for odd fields of interlaced scan data, the generation of scan lines for even fields of interlaced scan data is readily understood from the above description.

Writing the sequential scan data to the memory 6703 and reading the interlaced scan data from the memory 6703 are based on the same signal, that is, the write signal WR.
Furthermore, the generation of the write address and the read address is based on the first clock signal CLK1 and the second clock signal CLK2 having a fixed relationship. As a result, the generated interlaced scan data IDATA ′ is synchronized with the generated sequential scan data PDATA.

  Another embodiment of the PIC 220 will be described with reference to FIGS. FIG. 8 shows an embodiment of PIC 220. The embodiment shown in FIG. 8 is the same as the embodiment shown in FIG. 6 except for the parts described in detail below. Since most of the embodiment shown in FIG. 8 is almost the same as the embodiment shown in FIG. 6, only the different parts will be described briefly.

  In the embodiment of FIG. 8, the counter 620 is reset based on one of the odd horizontal synchronization signal odd_hsync or the even horizontal synchronization signal even_hsync. As a result, there is no timing for resetting the counter 620 depending on whether an even field or an odd field occurs. Instead, the PIC 220 provides a third subtractor 6303, a first comparator 6301 'and a 22nd MUX 6307' for achieving such timing changes.

  As shown in FIG. 8, the third subtractor 6303 subtracts the value 996 from the count value cnt to generate an even field scan line pixel value. The value 996 is the same value as 858 (first scanning line) +138 (horizontal blanking interval of the next scanning line). The first subtracter generates odd field scan line pixel values.

  The first comparator 6301 ′ determines whether an odd field or top field has been generated, and whether the count value indicates pixel data for odd scan lines, whether an even field or bottom field has been generated, and the count value. Determines whether it represents pixel data for even scan lines. In particular, the first comparator 6301 ′ generates a control signal of “1” when the field identification signal field_id indicates the top or odd field and the count value cnt is equal to or greater than 138 and less than 859. The first comparator 6301 ′ generates a control signal “2” when the field identification signal field_id indicates an even number or a bottom field and the count value cnt is equal to or larger than 996. When the count value cnt is smaller than 138, the first comparator 6301 ′ generates a control signal that is “0”.

  The first MUX 6307 ′ outputs the even scan line pixel value when the first comparator 6301 ′ generates the control signal “2”, and the odd scan when the first comparator 6301 ′ generates the control signal “1”. The line pixel value is output, and 0 is output when the first comparator 6301 ′ generates a control signal of “0”.

  Each of FIG. 9A to FIG. 9O shows the same waveform as that shown in FIG. 7A to FIG. FIG. 9P shows the even field pixel value generated by the third subtractor 6303.

  The embodiment according to the present invention shown in FIG. 8 provides the same synchronization as the generated sequential scan data PDATA described with reference to FIG. 6 and the generated interlaced scan data IDATA '.

  Although the present invention has been described with reference to one illustrated embodiment, this is by way of example only, and various modifications and equivalent other embodiments can be made by those skilled in the art. Will be understood. Therefore, the true technical protection scope of the present invention is determined by the technical idea of the claims.

  The scan conversion apparatus and scan conversion method according to the present invention can be used for various types of display devices (for example, TVs, computer monitors, etc.).

1 illustrates a scan conversion apparatus according to an embodiment of the present invention. The relationship between the original interlaced scan data IDATA of FIG. 1 and the generated sequential scan data PDATA is shown. An example of IPC shown in FIG. 1 is shown. An example of spatial interpolation is shown. An example of a block of pixels (i, j) is shown. An example of an adjacent block of block (i, j) is shown. Fig. 4 shows vertical low-pass filtering to remove vertical noise. 7-way correlation is shown. It is a figure for demonstrating calculation of a vertical edge. 2 shows another example of the IPC shown in FIG. An example of PIC shown in FIG. 1 is shown. The input / output waveform of the component of PIC shown in FIG. 6 is shown. Another example of PIC shown in FIG. 1 is shown. The input / output waveform of the component of PIC shown in FIG. 8 is shown.

Explanation of symbols

200 Scan Conversion Device 201, 203, 205 Terminal 210 IPC
220 PIC

Claims (26)

A first converter for converting input interlaced scanning data into sequential scanning data;
A second converter for converting the progressive scan data output from the first converter into interlaced scan data ;
The second converter includes:
A memory for storing the progressive scan data and generating a write signal;
A scan conversion apparatus comprising: an address controller that selectively applies a write address and a read address to the memory based on the write signal output from the memory .   The scan conversion apparatus according to claim 1, wherein the first converter converts the interlaced scan data into the progressive scan data based on a technique selected from different techniques. The different technologies are:
A spatial interpolation technique including performing spatial interpolation on a current field of the interlaced scan data to generate a complementary scan data field indicating a frame of the sequential scan data together with the current field;
An alternative field output technique for alternately outputting two consecutive fields of the interlaced scan data in units of scan lines to generate the frame of the progressive scan data;
Combined with temporal interpolation using the current field of the input interlaced scan data, at least one previous field and at least one continuous field to perform directional adaptive spatial interpolation, along with the current field, the sequential A scan conversion apparatus according to claim 2, including a space / time interpolation technique including generating a field of complementary scan data indicative of a frame of scan data.   The second converter outputs the interlaced scan data output from the second converter so that the interlaced scan data output from the first converter can be synchronized with the progressive scan data output from the first converter. The scanning conversion apparatus according to claim 1, wherein sequential scanning data is converted into the interlaced scanning data. The second converter includes:
A counter for generating the count value at a sequential scan frequency so that the count value is related to a period of the progressive scan data ;
Based on the output of the previous SL counters, a write address generator for the generating said write addresses for writing sequential scanning data to said memory,
Based on an output of said counter, according to claim 1, characterized in that it comprises a read address generator for generating the read address for sequentially outputs scan data written in the memory as the interlaced scanning data Scan conversion device. The address controller controls the supply of the write address and the read address so that interlaced scan data for one scan line can be read from the memory while sequential scan data for one scan line is written to the memory. The scan conversion apparatus according to claim 1 .   The counter generates the count value related to different periods of the sequential scanning data based on whether the sequential scanning data is converted from one of an odd field and an even field of the interlaced scanning data. The scan conversion apparatus according to claim 5. The counter generates the count value associated with an odd scan line and a next even scan line of the sequential scan data when the sequential scan data is converted from an odd field of the interlaced scan data, and the sequential scan is performed. when the data is converted from the even field of the interlaced scan data, according to claim 7, characterized in that to produce the count value associated with the even scan lines and the next odd scan lines of the progressively scanned data Scan conversion device.   6. The scan conversion apparatus of claim 5, wherein the counter generates the count value associated with two successive scan lines of the progressive scan data. The write address generator is
A first write address generator for generating a first write address associated with a first scan line of the two consecutive scan lines based on the count value;
A second write address generator for generating a second write address associated with a second scan line of the two consecutive scan lines based on the count value;
Based on which one of the odd field and the even field of the interlaced scan data is converted from the one of the first write address and the second write address, The scan conversion apparatus according to claim 9 , further comprising a write address controller that selectively outputs. The write address controller according to claim 1 0, characterized in that receiving a control signal indicating whether the sequential scan data has been converted from any one of one of the odd and even fields of the interlaced scan data The scan conversion device described in 1. 10. The scan conversion apparatus according to claim 9 , wherein the read address generator converts the count value into a read address associated with one scan line of the interlaced scan data. The second converter includes:
Memory,
A timer that displays the timing of two consecutive scan lines of the progressive scan data;
A write address generator for receiving a control signal instructing to write the two consecutive scan lines to the memory;
A read address generator for generating a read address so as to read the scanning line written from the memory;
The write address generator generates a write address for the displayed scan line based on the timing displayed by the timer;
The scan conversion apparatus according to claim 1, wherein the read address generator starts generating the read address based on the timing displayed by the timer. Jump-to-sequential converter,
A sequential-interlaced converter connected to the interlaced-sequential converter,
The progressive-interlaced converter generates interlaced scan data synchronized with the progressive scan data output by the interlaced-sequential converter ;
The sequential-to-interlace converter is
A memory for storing the progressive scan data and generating a write signal;
An address controller that selectively applies a write address and a read address to the memory based on the write signal output from the memory . In sequential-interlaced scan data converter,
A counter for generating the count value at a sequential scan frequency so that the count value is related to the period of the progressive scan data;
A memory for generating a write signal ;
A write address generator for generating a write address for writing the progressive scan data to the memory based on the output of the counter;
A read address generator for generating a read address for outputting the sequential scan data written in the memory as the scan data based on the output of the counter ;
A sequential-interlaced scan data converter , comprising: an address controller that selectively applies the write address and the read address to the memory based on the write signal output from the memory . The address controller controls supply of the write address and the read address so that interlaced scan data for one scan line can be read from the memory while sequential scan data for one scan line is written to the memory. 16. The sequential-interlaced scan data converter according to claim 15 , wherein: The counter generates the count value related to different periods of the sequential scanning data based on whether the sequential scanning data is converted from one of an odd field and an even field of the interlaced scanning data. interlaced scan data converter - sequentially according to claim 1 5, characterized in. The counter generates the count value associated with an odd scan line and a next even scan line of the sequential scan data when the sequential scan data is converted from an odd field of the interlaced scan data, and the sequential scan is performed. when the data is converted from the even field of the interlaced scan data, to claim 1 7, characterized in that to generate the count values associated with said sequential and even scan lines of the scan data and the next odd scan lines A sequential-interlaced scan data converter as described. The sequential-interlaced scan data converter of claim 15 , wherein the counter generates the count value associated with two consecutive scan lines of the progressive scan data. The write address generator is
A first write address generator for generating a first write address associated with a first scan line of the two consecutive scan lines based on the count value;
A second write address generator for generating a second write address associated with a second scan line of the two consecutive scan lines based on the count value;
Based on which one of the odd field and the even field of the interlaced scan data is converted from the one of the first write address and the second write address, The sequential-interlaced scan data converter according to claim 19 , further comprising a write address controller for selectively outputting. The write address controller according to claim 2 0, wherein receiving a control signal indicating whether the sequential scan data has been converted from any one of one of the odd and even fields of the interlaced scan data A sequential-interlaced scan data converter as described in 1. 20. The sequential-interlaced scan data converter according to claim 19 , wherein the read address generator converts the count value into a read address associated with one scan line of the interlaced scan data. In sequential-interlaced scan data converter,
A memory for generating a write signal ;
A timer that displays the timing of two consecutive scan lines of progressive scan data;
A write address generator that receives a control signal instructing to write the two consecutive scan lines into the memory and generates a write address for the displayed scan line based on the timing displayed by the timing When,
A read address generator for generating a read address so as to read a scanning line written from the memory, and starting generation of the read address based on a timing displayed by the timer ;
And an address controller for selectively applying the write address and the read address to the memory based on the write signal output from the memory . Converting input interlaced scanning data into sequential scanning data;
Converting the progressive scan data into output interlaced scan data ,
The step of converting the progressive scan data into output interlaced scan data includes:
Writing the progressive scan data to the memory and reading the progressive scan data stored from the memory based on a write address and a read address selectively applied to the memory;
The scan conversion method, wherein the write address and the read address are selectively applied to the memory based on a write signal output from the memory . Scan conversion method according to claim 2 4, wherein the output interlaced data, characterized in that is synchronized with the sequential scanning data, In a method of converting progressive scan data into interlaced scan data,
Generating the count value at a sequential scan frequency such that the count value is related to a period of the progressive scan data;
Generating a write address for storing the progressive scan data in a memory based on the count value;
Generating a read address to output the sequential scan data written in the memory as interlaced scan data;
Selectively applying the write address and the read address to the memory based on a write signal generated from the memory;
Storing the progressive scan data in the memory based on the generated write address;
Outputting the progressive scan data from the memory based on the generated read address, and converting the progressive scan data into interlaced scan data.

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