JP4630019B2 - Manufacturing method of semiconductor device - Google Patents

Description

  The present invention relates to a method for manufacturing a semiconductor device using a group III nitride semiconductor layer.

  In recent years, gallium nitride compound semiconductors (GaN, AlGaN, InGaN, etc.) containing gallium and nitrogen as constituent elements have high frequency or high output performance in addition to application to short wavelength light emitting devices such as blue lasers. Has attracted attention in its application. In these elements, when miniaturization, high speed, and high efficiency are realized, or when high integration of these elements is realized, the peripheral portion of the element, between the elements adjacent to each other, or the element It is necessary to electrically isolate the elements by forming a high resistance region between the substrate and the substrate.

  A conventional method for manufacturing a semiconductor device having a structure for electrically separating elements will be described below with reference to FIGS.

  First, a method for manufacturing a semiconductor device according to a first conventional example will be specifically described with reference to FIG. 9 (see, for example, Non-Patent Documents 1 and 2).

  As shown in FIG. 9, a deposited layer 101 is formed on a semiconductor substrate 100 by laminating gallium nitride compound semiconductor layers 101A and 101B. An ion-implanted region 102 in which ions are implanted into the deposited layer 101 is selected by ion-implanting ions such as He or Ne into a portion of the deposited layer 101 other than the element formation region on the semiconductor substrate 100. Form. By forming the gate electrode 103, the source electrode 104, and the drain electrode 105 in the element formation region partitioned by the ion implantation region 102 in the deposition layer 101, the gate electrode 103, the source electrode 104, and the drain are formed on the semiconductor substrate 100. An element including a transistor including the electrode 105 is formed. In this manner, as shown in FIG. 9, the inactive region is formed as a high resistance region by selective ion implantation in a region other than the device formation region on the semiconductor substrate 100, thereby electrically separating the devices. .

  Next, a method for manufacturing a semiconductor device according to a second conventional example will be specifically described with reference to FIG.

  As shown in FIG. 10, a deposited layer 201 in which gallium nitride-based compound semiconductor layers 201 </ b> A and 201 </ b> B are stacked is formed on a semiconductor substrate 200. By performing wet etching or dry etching (plasma etching) on a portion of the deposited layer 201 in a region other than the element formation region on the semiconductor substrate 200, the etched region 202 in which the deposited layer 201 is etched is selectively selected. Form. A gate electrode 203, a source electrode 204, and a drain electrode 205 are formed in an element formation region partitioned by the etching region 202 in the deposited layer 201, whereby the gate electrode 203, the source electrode 204, and the drain electrode are formed on the semiconductor substrate 200. An element including a transistor made of 205 is formed. In this manner, as shown in FIG. 10, the elements are electrically separated by forming a gap as a high resistance region by etching in a region other than the element formation region on the semiconductor substrate 200.

  Next, a method for manufacturing a semiconductor device according to a third conventional example will be specifically described with reference to FIG. 11 (see, for example, Non-Patent Document 3).

As shown in FIG. 11, a deposited layer 301 is formed on a semiconductor substrate 300 by laminating gallium nitride compound semiconductor layers 301A and 301B. The oxidized region 302 in which the deposited layer 301 is oxidized is selectively formed by performing heat treatment in a specific atmosphere on a portion of the deposited layer 301 other than the element formation region on the semiconductor substrate 300. Here, the oxide region 302 can be selectively formed by protecting the element formation region over the semiconductor substrate 300 with an insulating film or the like. A gate electrode 303, a source electrode 304, and a drain electrode 305 are formed in an element formation region partitioned by the oxidized region 302 in the deposition layer 301, whereby the gate electrode 303, the source electrode 304, and the drain electrode are formed on the semiconductor substrate 300. An element including a transistor 305 is formed. In this manner, as shown in FIG. 11, elements are electrically isolated from each other by forming an oxide region as a high resistance region by heat treatment in a region other than the element formation region on the semiconductor substrate 300.
Zolper et al, "Status of implantationdoping and isolation of III-V nitrides", ECS Proceedings volume 95-21,144 Binari et. Al, "He and N implant isolation of n-type GaN", APL 78 (5) 3008 News Release December 13, 2000 Matsushita Electronics Co., Ltd. “Development of selective thermal oxidation technology for gallium nitride semiconductors”

  However, according to the semiconductor device manufacturing methods according to the first to third conventional examples, the following problems have occurred.

  In the case of the semiconductor device manufacturing method according to the first conventional example shown in FIG. 9, the ion implantation region 102 formed as the element isolation region is inferior in thermal stability. For example, in the process after the ion implantation region 102 is formed, the ion implantation region 102 is activated as the temperature rises due to a heat treatment such as annealing, so that the specific resistance in the ion implantation region 102 decreases and the like. Stability deteriorates. Therefore, according to the semiconductor device manufacturing method of the first conventional example, the elements cannot be sufficiently electrically separated.

  In the case of the semiconductor device manufacturing method according to the second conventional example shown in FIG. 10, the gallium nitride compound semiconductor is originally chemically stable. Therefore, it is very difficult to perform wet etching and dry etching (plasma etching) with high accuracy. In addition, damage due to plasma etching occurs on the surface of the deposited layer 201 that has been subjected to plasma etching. For this reason, the leakage current increases in the etching region 202 formed as the element isolation region. Therefore, according to the semiconductor device manufacturing method according to the second conventional example, the elements cannot be sufficiently separated electrically.

  In the case of the method of manufacturing the semiconductor device according to the third conventional example shown in FIG. 11, the oxide is generally excellent in thermal stability, so that the oxidized region 302 formed by performing the heat treatment is Excellent thermal stability. However, the reaction for forming an oxide by heat treatment generally starts with a crystal defect present in a region to be oxidized. That is, the reaction for forming the oxidized region 302 depends on the density of crystal defects in the deposited layer 301. For this reason, the formation of the oxidized region 302 changes depending on the density of crystal defects in the deposited layer 301. For example, in the case of the deposited layer 301 having a low crystal defect density, as compared with the deposited layer 301 having a large crystal defect density, the deposited layer 301 made of a gallium nitride compound semiconductor is simply subjected to heat treatment. The oxidation region 302 cannot be easily formed only by promoting oxidation. Therefore, according to the semiconductor device manufacturing method of the third conventional example, the elements cannot be sufficiently electrically separated.

  In view of the above, an object of the present invention is to manufacture a semiconductor device that can easily form a high-resistance region with excellent thermal stability and low leakage current in a semiconductor device using a group III nitride semiconductor layer. Is to provide a method. Thus, a method for manufacturing a semiconductor device is provided which has an excellent element isolation structure and can realize element miniaturization, high speed, high efficiency, and high integration.

  In order to solve the above-described problem, a method for manufacturing a semiconductor device according to the present invention is a method for manufacturing a semiconductor device for forming an insulating oxide film that separates element formation regions in a group III nitride semiconductor layer. Forming a modified region of the group III nitride semiconductor layer in the group III nitride semiconductor layer so as to partition an element formation region in the nitride semiconductor layer; and oxidizing the modified region to thereby form an insulating oxide film Forming the step.

  According to the semiconductor device manufacturing method of the present invention, the oxidation treatment is performed on the modified region of the group III nitride semiconductor layer, so that the oxidation reaction in the modified region of the group III nitride semiconductor layer can be promoted. Therefore, the insulating oxide film can be easily formed. Thereby, an insulating oxide film can be formed as a high resistance region capable of suppressing leakage current. For this reason, a high-resistance region having excellent thermal stability can be formed. Accordingly, a semiconductor device having an excellent element isolation structure that can electrically isolate elements from each other by an insulating oxide film that is a high resistance region can be manufactured, so that element miniaturization, high speed, and high efficiency are achieved. It is possible to provide a semiconductor device using a group III nitride semiconductor layer that can be realized with high integration and high integration.

  In the method for manufacturing a semiconductor device according to the present invention, the step of forming the modified region includes the step of forming the modified region by damaging the group III nitride semiconductor layer to form crystal defects. Is preferred.

  Thus, by forming the modified region having crystal defects, the oxidation reaction on the modified region can be promoted. Thereby, an insulating oxide film can be easily formed in the modified region of the group III nitride semiconductor layer. That is, since the formation of the insulating oxide film starts mainly with crystal defects existing in the modified region of the group III nitride semiconductor layer, the oxidation reaction on the modified region can be promoted.

  In the method for manufacturing a semiconductor device according to the present invention, the step of forming the modified region preferably includes a step of forming the modified region by performing dry etching on the group III nitride semiconductor layer.

  In this way, a modified region having, for example, a crystal defect or the like can be easily formed in the group III nitride semiconductor layer.

  In the method of manufacturing a semiconductor device according to the present invention, the step of forming the modified region preferably includes a step of forming the modified region by performing ion implantation on the group III nitride semiconductor layer.

  In this way, a modified region having, for example, a crystal defect or the like can be easily formed in the group III nitride semiconductor layer.

  In the method of manufacturing a semiconductor device according to the present invention, the ion implantation is preferably performed using ions made of aluminum, gallium, or titanium.

  In this case, the ions made of aluminum (Al) or gallium (Ga) contain the same kind of element as that contained in the group III nitride semiconductor layer (for example, GaN, AlGaN, InGaN, etc.). When the modified region of the nitride semiconductor layer is oxidized, a good insulating oxide film of the same type as the oxidized group III nitride semiconductor layer can be formed. Since all of these ions have excellent oxidizability, they do not remain as metal after oxidizing the modified region of the group III nitride semiconductor layer. Can be formed.

  In the method of manufacturing a semiconductor device according to the present invention, the ion implantation is preferably performed using ions made of magnesium or carbon.

In this case, for example, in the modified region, N vacancies (N vacancy points) become dominant, and when the insulating oxide film formed by oxidizing this region acts as an n ⁻ -type impurity, Since these ions are p ⁻ type impurities, after the modified region of the group III nitride semiconductor layer is oxidized, the n ⁻ type impurities in the insulating oxide film can be compensated.

  In the method for manufacturing a semiconductor device according to the present invention, the step of forming the modified region includes forming the modified region by performing wet etching using an alkaline solution or a phosphoric acid solution on the group III nitride semiconductor layer. It is preferable to include a process.

  In this way, a modified region having, for example, a crystal defect or the like can be easily formed in the group III nitride semiconductor layer.

  In the method of manufacturing a semiconductor device according to the present invention, the step of forming the modified region includes the step of forming the modified region by performing a heat treatment after forming a metal oxide film on the surface of the group III nitride semiconductor layer. It is preferable to include.

  In this case, the metal in the metal oxide film formed on the surface of the group III nitride semiconductor layer reacts with the nitride in the group III nitride semiconductor layer, so that the modified region is formed in the group III nitride semiconductor layer. Can be formed.

  In the method for manufacturing a semiconductor device according to the present invention, the step of forming the modified region preferably includes a step of forming the modified region by immersing the group III nitride semiconductor layer in an electrolyte solution and energizing it.

  In this way, a modified region having, for example, a crystal defect or the like can be easily formed in the group III nitride semiconductor layer.

  In the method for manufacturing a semiconductor device according to the present invention, the step of forming the modified region preferably includes a step of forming the modified region while adjusting the degree of modification.

  In this case, the modified region is formed in a desired range and a desired strength, so that an insulating oxide film having a desired location and a desired shape can be formed. For example, when a crystal defect is formed as the modified region, an insulating oxide film having a desired region and a desired film thickness can be easily formed by adjusting the density at which the crystal defect is formed.

  In the method of manufacturing a semiconductor device according to the present invention, the step of forming the modified region includes a step of forming a plurality of modified regions in the group III nitride semiconductor layer, and the step of forming the insulating oxide film includes a plurality of steps. It is preferable to include a step of forming a plurality of insulating oxide films by oxidizing the modified region.

In this manner, by forming a plurality of modified regions in the group III nitride semiconductor layer, it becomes possible to form insulating oxide films having different film thicknesses in the same process. For this reason, simplification of a process can be achieved. For example, in the case of forming an oxide film made of SiO ₂ , a plurality of steps are required to form oxide films having different thicknesses in a plurality of regions. By oxidizing a plurality of regions having different degrees of modification, insulating oxide films having different film thicknesses can be formed in the same process.

  In the method for manufacturing a semiconductor device according to the present invention, the step of forming the insulating oxide film preferably includes a step of forming the insulating oxide film by oxidizing the modified region while masking the element forming region.

  In this way, since only the modified region in the group III nitride semiconductor layer can be oxidized, an insulating oxide film can be easily formed in a region other than the element formation region in the group III nitride semiconductor layer. Can do.

  In the method for manufacturing a semiconductor device according to the present invention, the step of forming the modified region includes the step of forming the modified region by etching the group III nitride semiconductor layer, and the etching is performed by group III nitriding. It is preferable to remove the group III nitride semiconductor layer so that the surface height of the portion existing in the element formation region in the oxide semiconductor layer is the same as the surface height of the insulating oxide film.

  Thus, since the modified region is formed while reducing the thickness of the group III nitride semiconductor layer by etching, after oxidizing the modified region, the surface of the region where the modified region is oxidized, Compared to the surface of the non-oxidized region, it is possible to prevent a convex state. As described above, the difference between the surface height of the portion existing in the element formation region in the group III nitride semiconductor layer and the surface height of the insulating oxide film can be reduced and flattened. For this reason, it becomes possible to increase the resolution in the photolithography process, which is a subsequent process, and facilitate the multilayer wiring process.

  According to the semiconductor device manufacturing method of the present invention, the oxidation treatment is performed on the modified region of the group III nitride semiconductor layer, so that the oxidation reaction in the modified region of the group III nitride semiconductor layer can be promoted. Therefore, the insulating oxide film can be easily formed. Thereby, an insulating oxide film can be formed as a high resistance region capable of suppressing leakage current. For this reason, a high-resistance region having excellent thermal stability can be formed. Accordingly, a semiconductor device having an excellent element isolation structure that can electrically isolate elements from each other by an insulating oxide film that is a high resistance region can be manufactured, so that element miniaturization, high speed, and high efficiency are achieved. It is possible to provide a semiconductor device using a group III nitride semiconductor layer that can be realized with high integration and high integration.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(First embodiment)
A method for manufacturing a semiconductor device according to the first embodiment of the present invention will be described below with reference to FIGS. 1 (a) to (c) and FIGS. 2 (a) to (c).

  1 (a) to 1 (c) and FIGS. 2 (a) to 2 (c) are cross-sectional views showing main steps of a manufacturing process of a semiconductor device according to the first embodiment of the present invention having an oxide region as a high resistance region. FIG.

  First, as shown in FIG. 1A, after a first region 11A made of a gallium nitride compound semiconductor is formed on a semiconductor substrate 10, a gallium nitride compound is formed on the first region 11A. A second region 11B made of a semiconductor is formed. In this manner, the deposition layer 11 made of a gallium nitride compound semiconductor in which the first region 11A and the second region 11B are stacked is formed. As a material of the semiconductor substrate 10, for example, sapphire, SiC, Si, or GaN can be used. In addition, an HFET can be configured by using GaN as the first region 11A and using AlGaN as the second region 11B. Further, by using i-type GaN as the first region 11A and using n-type GaN as the second region 11B, a MESFET can be configured.

Next, as shown in FIG. 1B, a selective mask layer 12 having a desired pattern is formed on the deposited layer 11. As the material of the selection mask layer 12, a photosensitive resist, an insulating film such as SiO ₂ or SiN, a metal film such as Al or Ti, or Si can be used.

  Specifically, as a method for forming the selective mask layer 12 having a desired pattern, a lift-off method or an etching method described below can be given.

  First, when the lift-off method is used, first, a photosensitive resist is uniformly applied to the entire surface of the deposition layer 11, and then the photosensitive resist is patterned to form a photosensitive resist having a desired pattern. Form. Next, a selective mask layer 12 is deposited on the entire surface of the deposited layer 11 and the photosensitive resist having a desired pattern. Thereafter, an excess portion of the selective mask layer 12 is removed, and further, the photosensitive resist is removed, thereby forming the selective mask layer 12 having a desired pattern.

  As described above, when the selective mask layer 12 having a desired pattern is formed using the lift-off method, the method for depositing the selective mask layer 12 is appropriately selected according to the material used for the selective mask layer 12. When a photosensitive resist is used as the material of the selective mask layer 12, the photosensitive resist is uniformly applied to the entire surface of the deposition layer 11 by spin coating, and the selective mask layer 12 made of the photosensitive resist is deposited. On the other hand, when an insulating film, a metal film, Si, or the like is used as the material of the selection mask layer 12, selection is made of an insulating film, a metal film, Si, or the like on the entire surface of the deposition layer 11 by a vacuum vapor deposition method or a plasma CVD method. A mask layer 12 is deposited.

  Second, in the case of using the etching method, first, a selective mask layer 12 is deposited on the entire surface of the deposition layer 11, and then a photosensitive resist is uniformly applied on the entire surface of the selective mask layer 12. Next, an opening for exposing the selective mask layer 12 is formed by forming a desired pattern on the photosensitive resist applied to the entire surface of the selective mask layer 12. Subsequently, the opening that exposes the selection mask layer 12 is etched to remove a portion of the selection mask layer 12 that exists in the opening, thereby forming the selection mask layer 12 having a desired pattern. In this step, the etching may be performed so that the portion of the selective mask layer 12 existing in the opening is not completely removed but remains. In this case, in the next step shown in FIG. 1C, when the modified region 13 is formed, the remaining portion of the selective mask layer 12 and the deposited layer 11 are damaged and the modified region is formed. 13 may be formed.

  The etching method includes a wet etching method or a dry etching method. When the dry etching method is used, the selective mask layer is formed by performing dry etching on the opening exposing the selective mask layer 12. It is also possible to form the modified region 13 by excessively dry-etching the portion of the deposition layer 11 that is not protected by the selective mask layer 12 after removing the portion existing in the opening portion in FIG. It is.

  As described above, when the selective mask layer 12 having a desired pattern is formed using the etching method, the method for depositing the selective mask layer 12 is appropriately selected according to the material used for the selective mask layer 12. When a photosensitive resist is used as the material of the selective mask layer 12, the photosensitive resist is uniformly applied to the entire surface of the deposition layer 11 by spin coating, and the selective mask layer 12 made of the photosensitive resist is deposited. On the other hand, when an insulating film, a metal film, Si, or the like is used as the material of the selection mask layer 12, selection is made of an insulating film, a metal film, Si, or the like on the entire surface of the deposition layer 11 by a vacuum vapor deposition method or a plasma CVD method. A mask layer 12 is deposited.

  Next, as shown in FIG. 1C, a modified region 13 is formed by damaging a portion of the deposited layer 11 that is not protected by the selective mask layer 12 to form crystal defects. . Examples of the method of giving damage include ion implantation, wet etching using a phosphoric acid solution or an alkaline solution, plasma etching, ion milling, electron beam, sputtering, or the like in which an electric current is immersed in an electrolyte solution.

  Here, when the modified region 13 is formed by ion implantation, ions used for ion implantation will be specifically described.

  As the implanted ions, ions made of aluminum, gallium, or titanium are preferably used. This is because ions made of aluminum (Al) or gallium (Ga) contain the same kind of element as that contained in a gallium nitride-based compound semiconductor (for example, GaN, AlGaN, InGaN, etc.). This is because when oxidized, a good oxidized region 14 of the same type as the oxidized gallium nitride compound semiconductor can be formed. In addition, since all of these ions have excellent oxidizability, they do not remain as metal after the modified region 13 is oxidized, so that an oxide film having good insulating properties can be formed. It is.

In addition, ions made of magnesium, carbon, or calcium are preferably used as the implanted ions. This is because N vacancies (N vacancy points) dominate in the modified region 13, and when the oxidized region 14 formed by oxidizing this region acts as an n ⁻ -type impurity, these ions Is a p ⁻ -type impurity, and therefore, after oxidizing the modified region 13, it is possible to compensate for the n ⁻ -type impurity in the oxidized region 14.

  Next, conditions for ion implantation will be specifically described.

  For example, when the modified region 13 is formed by performing ion implantation with an acceleration voltage of 0 keV on the deposited layer 11 made of GaN, a specific process is performed in a step shown in FIG. By performing heat treatment on the modified region 13 in an atmosphere (in an oxygen atmosphere, 1000 ° C.), the oxidized region 14 having a thickness of 100 nm can be formed. Further, when the modified region 13 is formed by performing ion implantation on the deposited layer 11 made of GaN by changing the acceleration voltage from 0 keV to 1000 keV, a specific atmosphere (in an oxygen atmosphere, 1000 ° C. ), The oxidized region 14 having a film thickness of 110 nm can be formed.

  In this way, the modified region 13 is formed while adjusting the degree of modification by adjusting the acceleration voltage in ion implantation. Thereby, the modified region 13 is formed in a desired range and a desired strength, so that the oxidized region 13 having a desired location and a desired shape can be formed. For example, when a crystal defect is formed as the modified region 13, the oxide region 14 having a desired region and a desired film thickness can be easily formed by adjusting the density at which the crystal defect is formed.

  Next, as shown in FIG. 2 (a), a portion of the deposited layer 11 in the element formation region is protected by the selective mask layer 12, and a heat treatment is performed on the modified region 13 in a specific atmosphere. An oxidized region 14 is formed in which the modified region 13 is oxidized. Here, heat treatment is performed in an oxygen atmosphere at 1000 ° C. Thereby, since only the modified region 13 in the deposited layer 11 can be oxidized, the oxidized region 14 can be easily formed in a portion in the region other than the element formation region in the deposited layer 11. If the selective mask layer 12 formed in the previous step shown in FIG. 1B is not suitable for the heat treatment performed in this step, the selective mask layer 12 is removed before the heat treatment, A selective mask layer suitable for heat treatment needs to be formed again using the method described above.

  Next, as shown in FIG. 2B, after the selective mask layer 12 is removed, a source electrode 15 and a drain electrode 16 are formed in the element formation region partitioned by the oxidation region 14 in the deposition layer 11 and heat treatment is performed. To obtain ohmic contact.

  Next, as shown in FIG. 2C, a gate electrode 17 is formed in the element formation region partitioned by the oxidation region 14 in the deposition layer 11. In this embodiment, the method for forming the source electrode 15, the drain electrode 16, and the gate electrode 17 is performed in the same manner as in the ordinary method for manufacturing a semiconductor device.

  As described above, according to the manufacturing method of the semiconductor device according to the first embodiment of the present invention, the modified region 13 made of the group III nitride semiconductor layer formed in the deposition layer 11 is subjected to the oxidation treatment. Since the oxidation reaction in the modified region 13 of the deposited layer 11 can be promoted, the oxidized region 14 can be easily formed. Thereby, the oxidation region 14 as a high resistance region capable of suppressing the leakage current can be formed. For this reason, a high-resistance region having excellent thermal stability can be formed.

  In addition, a modified region 13 having, for example, a crystal defect is formed by damaging a portion in a region other than the element formation region in the deposited layer 11 in advance. Thereby, since the oxidation reaction with respect to the modified region 13 can be promoted, the oxidized region 14 can be easily formed in the modified region 13 of the deposited layer 11. That is, since the formation of the oxidized region 14 starts mainly with crystal defects existing in the modified region 13 of the deposited layer 11, the oxidation reaction on the modified region 13 can be promoted.

Further, as shown in FIG. 1 (c), by forming a plurality of modified regions 13 on the deposited layer 11, oxidized regions having different film thicknesses in the next step shown in FIG. 2 (a). 14 can be formed in the same process. For this reason, simplification of a process can be achieved. For example, in the case of forming an oxide film made of SiO ₂ , a plurality of steps are required to form oxide films having different thicknesses in a plurality of regions. By oxidizing a plurality of regions having different degrees of modification, oxidized regions 14 having different film thicknesses can be formed in the same process.

  As described above, a semiconductor device having an excellent element isolation structure that can electrically isolate elements from each other by the oxidized region 14 that is a high resistance region can be manufactured. It is possible to provide a semiconductor device using a group III nitride semiconductor layer that can realize high efficiency, high efficiency, and high integration.

(Second Embodiment)
A method for manufacturing a semiconductor device according to the second embodiment of the present invention will be described below with reference to FIGS. 3 (a) to (c) and FIGS. 4 (a) to (c).

  3 (a) to 3 (c) and FIGS. 4 (a) to 4 (c) are cross-sectional views showing main steps of a manufacturing process of a semiconductor device according to the second embodiment of the present invention having an oxide region as a high resistance region. FIG.

  First, as shown in FIG. 3A, after a first region 31A made of a gallium nitride compound semiconductor is formed on a semiconductor substrate 30, a gallium nitride compound is formed on the first region 31A. A second region 31B made of a semiconductor is formed. In this manner, the deposition layer 31 made of a gallium nitride compound semiconductor in which the first region 31A and the second region 31B are stacked is formed. For example, sapphire, SiC, Si, or GaN can be used as the material of the semiconductor substrate 30. Further, an HFET can be configured by using GaN as the first region 31A and using AlGaN as the second region 31B. Further, by using i-type GaN as the first region 31A and using n-type GaN as the second region 31B, a MESFET can be configured.

Next, as shown in FIG. 3B, a selective mask layer 32 having a desired pattern is formed on the deposited layer 31. As the material of the selection mask layer 32, a photosensitive resist, an insulating film such as SiO ₂ or SiN, a metal film such as Al or Ti, or Si can be used.

  Specifically, as a method for forming the selective mask layer 32 having a desired pattern, a lift-off method or an etching method described below can be given.

  First, when the lift-off method is used, first, a photosensitive resist is uniformly applied to the entire surface of the deposition layer 31, and then the photosensitive resist is patterned to form a photosensitive resist having a desired pattern. Form. Next, a selective mask layer 32 is deposited on the entire surface of the deposited layer 31 and the photosensitive resist having a desired pattern. Thereafter, an excess portion of the selective mask layer 32 is removed, and further, the photosensitive resist is removed, thereby forming the selective mask layer 32 having a desired pattern.

  As described above, when the selective mask layer 32 having a desired pattern is formed using the lift-off method, the method for depositing the selective mask layer 32 is appropriately selected according to the material used for the selective mask layer 32. In the case where a photosensitive resist is used as the material of the selective mask layer 32, the photosensitive resist is uniformly applied to the entire surface of the deposition layer 31 by spin coating, and the selective mask layer 32 made of the photosensitive resist is deposited. On the other hand, in the case where an insulating film, a metal film, Si, or the like is used as the material of the selection mask layer 32, a selection made of an insulating film, a metal film, Si, or the like on the entire surface of the deposition layer 31 by a vacuum evaporation method, a plasma CVD method, or the like. A mask layer 32 is deposited.

  Second, in the case of using an etching method, first, a selective mask layer 32 is first deposited on the entire surface of the deposition layer 31, and then a photosensitive resist is uniformly applied to the entire surface of the selective mask layer 32. Next, an opening for exposing the selective mask layer 32 is formed by forming a desired pattern on the photosensitive resist applied to the entire surface of the selective mask layer 32. Subsequently, the opening that exposes the selection mask layer 32 is etched to remove a portion of the selection mask layer 32 that exists in the opening, thereby forming the selection mask layer 32 having a desired pattern. As a method for etching, a wet etching method, a dry etching method or the like can be given.

  As described above, when the selective mask layer 32 having a desired pattern is formed using the etching method, the method for depositing the selective mask layer 32 is appropriately selected according to the material used for the selective mask layer 32. In the case where a photosensitive resist is used as the material of the selective mask layer 32, the photosensitive resist is uniformly applied to the entire surface of the deposition layer 31 by spin coating, and the selective mask layer 32 made of the photosensitive resist is deposited. On the other hand, in the case where an insulating film, a metal film, Si, or the like is used as the material of the selection mask layer 32, a selection made of an insulating film, a metal film, Si, or the like on the entire surface of the deposition layer 31 by a vacuum vapor deposition method or a plasma CVD method. A mask layer 32 is deposited.

Next, as shown in FIG. 3C, a metal oxide film 33A made of TiO _x is formed on the surface of the portion of the deposited layer 31 that is not protected by the selective mask layer 32. Thereafter, heat treatment is performed on the metal oxide film 33A in a specific atmosphere, so that the metal in the metal oxide film 33A formed on the surface of the deposited layer 31 and the deposited layer 31 are formed as shown in FIG. The modified nitride region 33 is formed in the deposited layer 31 by reacting with the nitride therein. Here, heat treatment is performed in an atmosphere of 500 ° C. in a nitrogen atmosphere. Further, if the modified region 33 is formed while adjusting the degree of modification, the modified region 33 can be formed in a desired range and a desired strength. Therefore, in the next step shown in FIG. The oxidized region 34 having a desired location and a desired shape can be formed. In this step, the case where TiO _x is used as the material of the metal oxide film 33A has been described, but other MO _x may be used as the material. M represents a metal element, and specific examples include Ta or Mo.

  Next, as shown in FIG. 4 (a), the portion in the element formation region in the deposition layer 31 is protected by the selective mask layer 32, and the modified region 33 is subjected to heat treatment in a specific atmosphere. The modified region 33 forms an oxidized region 34 that is oxidized. Here, heat treatment is performed in an oxygen atmosphere at 1000 ° C. Thereby, since only the modified region 33 in the deposited layer 31 can be oxidized, the oxidized region 34 can be easily formed in a portion in the region other than the element formation region in the deposited layer 31. If the selective mask layer 32 formed in the previous step shown in FIG. 3B is not suitable for the heat treatment performed in this step, the selective mask layer 32 is removed before the heat treatment, A selective mask layer suitable for heat treatment needs to be formed again using the method described above.

  Next, as shown in FIG. 4B, after the selective mask layer 32 is removed, a source electrode 35 and a drain electrode 36 are formed in the element formation region partitioned by the oxidation region 34 in the deposition layer 31, and heat treatment is performed. To obtain ohmic contact.

  Next, as shown in FIG. 4C, a gate electrode 37 is formed in the element formation region partitioned by the oxidation region 34 in the deposition layer 31. In this embodiment, the method for forming the source electrode 35, the drain electrode 36, and the gate electrode 37 is performed in the same manner as a method for manufacturing a normal semiconductor device.

  As described above, according to the manufacturing method of the semiconductor device according to the second embodiment of the present invention, the modified region 33 made of the group III nitride semiconductor layer formed in the deposition layer 31 is subjected to the oxidation treatment. Since the oxidation reaction in the modified region 33 of the deposited layer 31 can be promoted, the oxidized region 34 can be easily formed. Thereby, the oxidation region 34 as a high resistance region capable of suppressing the leakage current can be formed. For this reason, a high-resistance region having excellent thermal stability can be formed.

  Further, the modified region 33 is formed by the reaction of the metal in the metal oxide film 33 </ b> A and the nitride in the deposited layer 31 on the surface of the portion of the deposited layer 31 other than the element formation region. Thereby, since the oxidation reaction with respect to the modified region 33 can be promoted, the oxidized region 34 can be easily formed in the modified region 33 of the deposition layer 31.

Further, as shown in FIG. 3 (c), by forming a plurality of modified regions 33 in the deposited layer 31, in the next step shown in FIG. 4 (a), oxidized regions having different film thicknesses. 34 can be formed in the same process. For this reason, simplification of a process can be achieved. For example, in the case of forming an oxide film made of SiO ₂ , a plurality of steps are required to form oxide films having different thicknesses in a plurality of regions. The oxidized regions 34 having different film thicknesses can be formed in the same process by oxidizing a plurality of regions having different degrees of modification.

  As described above, it is possible to manufacture a semiconductor device having an excellent element isolation structure that can electrically isolate elements from each other by the oxide region 34 that is a high resistance region. It is possible to provide a semiconductor device using a group III nitride semiconductor layer that can realize high efficiency, high efficiency, and high integration.

(Third embodiment)
A method for manufacturing a semiconductor device according to the third embodiment of the present invention will be described below with reference to FIGS. 5 (a) to (c) and FIGS. 6 (a) to (c).

  5 (a) to 5 (c) and FIGS. 6 (a) to 6 (c) are cross-sectional views showing main steps of the manufacturing process of the semiconductor device according to the third embodiment of the present invention having an oxide region as a high resistance region. FIG.

  First, as shown in FIG. 5A, after a first region 51A made of a gallium nitride compound semiconductor is formed on a semiconductor substrate 50, a gallium nitride compound is formed on the first region 51A. A second region 51B made of a semiconductor is formed. In this way, the deposition layer 51 made of a gallium nitride compound semiconductor in which the first region 51A and the second region 51B are stacked is formed. As a material of the semiconductor substrate 50, for example, sapphire, SiC, Si, or GaN can be used. Further, by using GaN as the first region 51A and using AlGaN as the second region 51B, an HFET can be configured. Further, by using i-type GaN as the first region 51A and using n-type GaN as the second region 51B, a MESFET can be configured.

Next, as shown in FIG. 5B, a selective mask layer 52 having a desired pattern is formed on the deposited layer 51. As a material for the selection mask layer 52, a photosensitive resist, an insulating film such as SiO ₂ or SiN, a metal film such as Al or Ti, or Si can be used.

  Specifically, as a method for forming the selective mask layer 52 having a desired pattern, a lift-off method or an etching method described below can be given.

  First, when the lift-off method is used, first, a photosensitive resist is uniformly applied to the entire surface of the deposition layer 51, and then the photosensitive resist is patterned to form a photosensitive resist having a desired pattern. Form. Next, a selective mask layer 52 is deposited on the entire surface of the deposited layer 51 and the photosensitive resist having a desired pattern. Thereafter, an excess portion of the selective mask layer 52 is removed, and further, the photosensitive resist is removed, thereby forming the selective mask layer 52 having a desired pattern.

  As described above, when the selective mask layer 52 having a desired pattern is formed using the lift-off method, the method for depositing the selective mask layer 52 is appropriately selected according to the material used for the selective mask layer 52. When a photosensitive resist is used as the material of the selective mask layer 52, the photosensitive resist is uniformly applied to the entire surface of the deposition layer 51 by spin coating, and the selective mask layer 52 made of the photosensitive resist is deposited. On the other hand, when an insulating film, a metal film, Si, or the like is used as a material for the selection mask layer 52, a selection made of an insulating film, a metal film, Si, or the like on the entire surface of the deposition layer 51 by a vacuum vapor deposition method, a plasma CVD method, or the like. A mask layer 52 is deposited.

  Secondly, when the etching method is used, first, a selective mask layer 52 is deposited on the entire surface of the deposition layer 51, and then a photosensitive resist is uniformly applied to the entire surface of the selective mask layer 52. Next, an opening for exposing the selective mask layer 52 is formed by forming a desired pattern on the photosensitive resist applied to the entire surface of the selective mask layer 52. Subsequently, the opening that exposes the selection mask layer 52 is etched to remove a portion of the selection mask layer 52 that exists in the opening, thereby forming the selection mask layer 52 having a desired pattern. The etching method includes a wet etching method or a dry etching method. When the dry etching method is used, the selective mask layer is formed by performing dry etching on the opening exposing the selective mask layer 52. It is also possible to form the modified region 53 by excessively dry-etching the portion of the deposition layer 51 that is not protected by the selective mask layer 52 after removing the portion existing in the opening in 52. It is.

  As described above, when the selective mask layer 52 having a desired pattern is formed using an etching method, the method for depositing the selective mask layer 52 is appropriately selected according to the material used for the selective mask layer 52. When a photosensitive resist is used as the material of the selective mask layer 52, the photosensitive resist is uniformly applied to the entire surface of the deposition layer 51 by spin coating, and the selective mask layer 52 made of the photosensitive resist is deposited. On the other hand, when an insulating film, a metal film, Si, or the like is used as a material for the selection mask layer 52, a selection made of an insulating film, a metal film, Si, or the like on the entire surface of the deposition layer 51 by a vacuum vapor deposition method, a plasma CVD method, or the like. A mask layer 52 is deposited.

  Next, as shown in FIG. 5 (c), a portion of the deposited layer 51 that is not protected by the selective mask layer 52 is removed by dry etching while forming a crystal defect by damaging the modified region. 53 is formed. Specific examples of dry etching performed in this step include plasma etching, sputter etching, ion milling, and the like.

  Here, when the modified region 53 is formed by dry etching, conditions for dry etching will be specifically described.

  For example, when the modified region 53 is formed by performing dry etching with a power of 0 W on the deposited layer 51 made of GaN, a specific atmosphere is used in the process shown in FIG. By subjecting the modified region 53 to heat treatment under the oxygen atmosphere (1000 ° C.), an element isolation oxide region 54A having a thickness of 100 nm can be formed. Further, when the modified region 53 is formed by changing the power from 0 W to 100 W and performing dry etching on the deposited layer 51 made of GaN, in a specific atmosphere (in an oxygen atmosphere, 1000 ° C.). Thus, by subjecting the modified region 53 to heat treatment, an element isolation oxide region 54A having a film thickness of 105 nm can be formed. Further, when the modified region 53 is formed by changing the power from 100 W to 300 W and performing dry etching on the deposited layer 51 made of GaN, it is in a specific atmosphere (in an oxygen atmosphere, 1000 ° C.). Thus, by subjecting the modified region 53 to heat treatment, an element isolation oxide region 54A having a film thickness of 120 nm can be formed.

  In this way, the modified region 53 is formed while adjusting the degree of modification by adjusting the power in dry etching. Thereby, the modified region 53 is formed in a desired range and a desired strength, so that the element isolation oxide region 54A having a desired location and a desired shape can be formed. For example, when a crystal defect is formed as the modified region 53, an element isolation oxide region 54A having a desired region and a desired film thickness can be easily formed by adjusting the density at which the crystal defect is formed. .

  Next, as shown in FIG. 6A, the selective mask layer 52 is patterned so as to expose a portion in a region other than the source electrode and drain electrode formation regions in the element formation region in the deposition layer 51. Thus, the selective mask layer 52 having a desired pattern is formed. The selective mask layer 52 having a desired pattern can be formed using the method described above.

  Next, of the portion in the element formation region in the deposition layer 51, the portion in the source electrode and drain electrode formation region is protected by the selective mask layer 52, and the modified layer 53 and the deposition layer in the opening are formed in a specific atmosphere. By performing heat treatment on 51, an element isolation oxide region 54A in which the modified region 53 is oxidized is formed, and at the same time, a MOS oxide region 54B in which a portion existing in the opening in the deposited layer 51 is oxidized is formed. Here, heat treatment is performed in an oxygen atmosphere at 1000 ° C. Thereby, since only the modified region 53 in the deposited layer 51 can be oxidized, the element isolation oxidized region 54A can be easily formed in a portion of the deposited layer 51 in a region other than the element forming region. If the selective mask layer 52 formed in the previous step shown in FIG. 5B is not suitable for the heat treatment performed in this step, the selective mask layer 52 is removed before the heat treatment, A selective mask layer suitable for heat treatment needs to be formed again using the method described above.

  Next, as shown in FIG. 6B, after the selective mask layer 52 is removed, the source electrode 55 and the drain electrode 56 are formed in the element formation region partitioned by the element isolation oxide region 54A in the deposition layer 51. The ohmic contact is obtained by applying heat treatment.

  Next, as shown in FIG. 6C, the gate electrode 57 is formed in the element formation region partitioned by the element isolation oxide region 54A in the deposition layer 51. In this embodiment, the method for forming the source electrode 55, the drain electrode 56, and the gate electrode 57 is performed in the same manner as in a normal method for manufacturing a semiconductor device.

  As described above, according to the manufacturing method of the semiconductor device according to the third embodiment of the present invention, the modified region 53 made of the group III nitride semiconductor layer formed in the deposition layer 51 is subjected to the oxidation treatment. Since the oxidation reaction in the modified region 53 of the deposited layer 51 can be promoted, the element isolation oxidized region 54A can be easily formed. Thereby, the element isolation oxide region 54A as a high resistance region capable of suppressing the leakage current can be formed. For this reason, a high-resistance region having excellent thermal stability can be formed.

  Further, a modified region 53 having, for example, a crystal defect is formed while a portion of the deposited layer 51 in a region other than the element formation region is previously removed by dry etching. Thereby, since the oxidation reaction with respect to the modified region 53 can be promoted, the element isolation oxidized region 54 </ b> A can be easily formed in the modified region 53 of the deposition layer 51. That is, since the formation of the element isolation oxide region 54A starts mainly with crystal defects existing in the modified region 53 of the deposited layer 51, the oxidation reaction on the modified region 53 can be promoted.

  Further, as shown in FIG. 5C, the modified region 53 is formed in the portion of the deposited layer 51 in the region other than the element formation region while reducing the film thickness of the deposited layer 51 by dry etching. Thus, after the modified region 53 is oxidized, the surface of the region where the modified region 53 is oxidized can be prevented from becoming a convex state as compared with the surface of the non-oxidized region. In this manner, the difference between the surface height of the portion of the deposited layer 51 existing in the element formation region and the surface height of the element isolation oxide region 54A can be reduced and flattened. For this reason, it becomes possible to increase the resolution in the photolithography process, which is a subsequent process, and to facilitate the multilayer wiring process.

Further, as shown in FIG. 6A, by forming a plurality of modified regions 53 in the deposited layer 51, element isolation having different film thicknesses is performed in the next step shown in FIG. 6B. It is possible to form the oxidized region 54A in the same process. For this reason, simplification of a process can be achieved. For example, in the case of forming an oxide film made of SiO ₂ , a plurality of steps are required to form oxide films having different thicknesses in a plurality of regions. By oxidizing a plurality of regions having different degrees of modification, element isolation oxide regions 54A having different film thicknesses can be formed in the same process.

  Further, as shown in FIG. 6A, the deposited layer 51 has two regions that are oxidized by a heat treatment performed in a later step. One of the two regions is a region in which the deposited layer 51 is modified in advance by dry etching. Another region to be oxidized is a region that is not protected by the selective mask layer 52 in the portion of the deposited layer 51 in the element formation region.

  When these regions are heat-treated in a specific atmosphere (in an oxygen atmosphere, 1000 ° C.) as shown in FIG. 6B, an element isolation oxide region 54A is formed, and a MOS oxide region is formed. 54B is formed. Thus, the element isolation oxide region 54A is formed by oxidizing the modified region 53, while the MOS oxide region 54B is formed by oxidizing the deposited layer 51. For this reason, since the element isolation oxide region 54A promotes the oxidation of the deposited layer 51 as compared with the MOS oxide region 54B, an oxide region having a large film thickness can be formed. In this way, by oxidizing a plurality of regions having different degrees of modification, oxidized regions having different film thicknesses can be formed in the same process.

  As described above, a semiconductor device having an excellent element isolation structure capable of electrically isolating elements can be manufactured by the element isolation oxide region 54A which is a high resistance region. In addition, a semiconductor device using a group III nitride semiconductor layer capable of realizing high speed, high efficiency, and high integration can be provided.

(Fourth embodiment)
A semiconductor device manufacturing method according to the fourth embodiment of the present invention will be described below with reference to FIGS. 7 (a) to (c) and FIGS. 8 (a) to (c).

  FIGS. 7A to 7C and FIGS. 8A to 8C are cross-sectional views showing main steps of a manufacturing process of a semiconductor device according to the fourth embodiment of the present invention having an oxide region as a high resistance region. FIG.

  First, as shown in FIG. 7A, after a first region 71A made of a gallium nitride compound semiconductor is formed on a semiconductor substrate 70, a gallium nitride compound is formed on the first region 71A. A second region 71B made of a semiconductor is formed. In this manner, the deposited layer 71 made of a gallium nitride compound semiconductor in which the first region 71A and the second region 71B are stacked is formed. As a material of the semiconductor substrate 70, for example, sapphire, SiC, Si, or GaN can be used. Further, by using GaN as the first region 71A and using AlGaN as the second region 71B, an HFET can be configured. Further, by using i-type GaN as the first region 71A and using n-type GaN as the second region 71B, a MESFET can be configured.

Next, as shown in FIG. 7B, a selective mask layer 72 having a desired pattern is formed on the deposited layer 71. As a material for the selection mask layer 72, a photosensitive resist, an insulating film such as SiO ₂ or SiN, a metal film such as Al or Ti, or Si can be used.

  Specifically, as a method for forming the selective mask layer 72 having a desired pattern, a lift-off method or an etching method described below can be given.

  First, when the lift-off method is used, first, a photosensitive resist is uniformly applied to the entire surface of the deposition layer 71, and then the photosensitive resist is patterned to form a photosensitive resist having a desired pattern. Form. Next, a selective mask layer 72 is deposited on the entire surface of the deposited layer 71 and a photosensitive resist having a desired pattern. Thereafter, an excess portion of the selective mask layer 72 is removed, and further, the photosensitive resist is removed, thereby forming the selective mask layer 72 having a desired pattern.

  Thus, when forming the selective mask layer 72 having a desired pattern using the lift-off method, the method for depositing the selective mask layer 72 is appropriately selected according to the material used for the selective mask layer 72. When a photosensitive resist is used as the material of the selective mask layer 72, the photosensitive resist is uniformly applied to the entire surface of the deposition layer 71 by spin coating, and the selective mask layer 72 made of the photosensitive resist is deposited. On the other hand, when an insulating film, a metal film, Si, or the like is used as a material for the selection mask layer 72, a selection made of an insulating film, a metal film, Si, or the like on the entire surface of the deposition layer 71 by a vacuum deposition method, a plasma CVD method, or the like. A mask layer 72 is deposited.

  Secondly, when the etching method is used, first, a selective mask layer 72 is deposited on the entire surface of the deposition layer 71, and then a photosensitive resist is uniformly applied to the entire surface of the selective mask layer 72. Next, an opening for exposing the selective mask layer 72 is formed by forming a desired pattern on the photosensitive resist applied on the entire surface of the selective mask layer 72. Subsequently, the opening that exposes the selection mask layer 72 is etched to remove the portion of the selection mask layer 72 that exists in the opening, thereby forming the selection mask layer 72 having a desired pattern. The etching method includes a wet etching method, a dry etching method, and the like. When the dry etching method is used, the selective mask layer 72 is subjected to dry etching to the opening from which the selective mask layer 72 is exposed. It is also possible to form the modified region 73 by removing excessively dry etching on the portion of the deposited layer 71 that is not protected by the selective mask layer 72 after removing the portion existing in the opening in 72. It is.

  As described above, when the selective mask layer 72 having a desired pattern is formed using an etching method, a method for depositing the selective mask layer 72 is appropriately selected according to the material used for the selective mask layer 72. When a photosensitive resist is used as the material of the selective mask layer 72, the photosensitive resist is uniformly applied to the entire surface of the deposition layer 71 by spin coating, and the selective mask layer 72 made of the photosensitive resist is deposited. On the other hand, when an insulating film, a metal film, Si, or the like is used as a material for the selection mask layer 72, a selection made of an insulating film, a metal film, Si, or the like on the entire surface of the deposition layer 71 by a vacuum deposition method, a plasma CVD method, or the like. A mask layer 72 is deposited.

  Next, as shown in FIG. 7 (c), a portion of the deposited layer 71 that is not protected by the selective mask layer 72 is removed by dry etching while forming a crystal defect by damaging the modified region. 73 is formed. Specific examples of dry etching performed in this step include plasma etching, sputter etching, ion milling, and the like.

  Here, when the modified region 73 is formed by dry etching, conditions for dry etching will be specifically described.

  For example, when the modified region 73 is formed by performing dry etching with a power of 0 W on the deposited layer 71 made of GaN, a specific atmosphere is used in the next step shown in FIG. By performing heat treatment on the modified region 73 under the oxygen atmosphere (1000 ° C.), the oxidized region 74 having a thickness of 100 nm can be formed. Further, when the modified region 73 is formed by changing the power from 0 W to 100 W and performing dry etching on the deposited layer 71 made of GaN, it is in a specific atmosphere (in an oxygen atmosphere, 1000 ° C.). By performing heat treatment on the modified region 73, an oxidized region 74 having a thickness of 105 nm can be formed. Further, when the modified region 73 is formed by changing the power from 100 W to 300 W and performing dry etching on the deposited layer 71 made of GaN, it is under a specific atmosphere (in an oxygen atmosphere, 1000 ° C.). By performing heat treatment on the modified region 73, an oxidized region 74 having a thickness of 120 nm can be formed.

  Thus, the modified region 73 is formed while adjusting the degree of modification by adjusting the power in dry etching. As a result, the modified region 73 is formed in a desired range and a desired strength, so that the oxidized region 74 having a desired location and a desired shape can be formed. For example, when a crystal defect is formed as the modified region 73, an oxide region 74 having a desired region and a desired film thickness can be easily formed by adjusting the density at which the crystal defect is formed.

  Next, as shown in FIG. 8 (a), the portion of the deposited layer 71 in the element formation region is protected by the selective mask layer 72, and the modified region 73 is subjected to heat treatment in a specific atmosphere. An oxidized region 74 in which the modified region 73 is oxidized is formed. Here, heat treatment is performed in an oxygen atmosphere at 1000 ° C. Thereby, since only the modified region 73 in the deposited layer 71 can be oxidized, the oxidized region 74 can be easily formed in a portion of the deposited layer 71 other than the element formation region. If the selective mask layer 72 formed in the previous step shown in FIG. 7B is not suitable for the heat treatment performed in this step, the selective mask layer 72 is removed before the heat treatment. A selective mask layer suitable for heat treatment needs to be formed again using the method described above.

  Next, as shown in FIG. 8B, after the selective mask layer 72 is removed, a source electrode 75 and a drain electrode 76 are formed in the element formation region partitioned by the oxidation region 74 in the deposition layer 71, and heat treatment is performed. To obtain ohmic contact.

  Next, as shown in FIG. 8C, a gate electrode 77 is formed in the element formation region partitioned by the oxidation region 74 in the deposition layer 71. In this embodiment, the method of forming the source electrode 75, the drain electrode 76, and the gate electrode 77 is performed in the same manner as a normal method for manufacturing a semiconductor device.

  As described above, according to the manufacturing method of the semiconductor device according to the fourth embodiment of the present invention, the modified region 73 made of the group III nitride semiconductor layer formed in the deposition layer 71 is subjected to the oxidation treatment. Since the oxidation reaction in the modified region 73 of the deposited layer 71 can be promoted, the oxidized region 74 can be easily formed. Thereby, the oxidation region 74 as a high resistance region capable of suppressing the leakage current can be formed. For this reason, a high-resistance region having excellent thermal stability can be formed.

  Further, a modified region 73 having, for example, a crystal defect is formed while removing a portion of the deposited layer 71 in a region other than the element formation region by dry etching in advance. Thereby, since the oxidation reaction with respect to the modified region 73 can be promoted, the oxidized region 74 can be easily formed in the modified region 73 of the deposited layer 71. That is, the formation of the oxidized region 74 starts mainly with crystal defects existing in the modified region 73 of the deposited layer 71, so that the oxidation reaction on the modified region 73 can be promoted.

  Further, as shown in FIG. 7C, a modified region 73 is formed in the portion of the deposited layer 71 in a region other than the element formation region while reducing the thickness of the deposited layer 71 by dry etching. Thereby, after oxidizing the modified region 73, the surface of the region where the modified region 73 is oxidized can be prevented from becoming a convex state as compared with the surface of the region not oxidized. In this way, the difference between the surface height of the portion of the deposited layer 71 existing in the element formation region and the surface height of the oxidized region 74 can be reduced and flattened. For this reason, it becomes possible to increase the resolution in the photolithography process, which is a subsequent process, and to facilitate the multilayer wiring process.

Further, as shown in FIG. 7 (c), by forming a plurality of modified regions 73 in the deposited layer 71, oxidized regions having different film thicknesses in the next step shown in FIG. 8 (a). 74 can be formed in the same process. For this reason, simplification of a process can be achieved. For example, in the case of forming an oxide film made of SiO ₂ , a plurality of steps are required to form oxide films having different thicknesses in a plurality of regions. By oxidizing a plurality of regions having different degrees of modification, oxidized regions 74 having different film thicknesses can be formed in the same process.

  As described above, a semiconductor device having an excellent element isolation structure capable of electrically isolating elements can be manufactured by the oxidized region 74 which is a high resistance region. It is possible to provide a semiconductor device using a group III nitride semiconductor layer that can realize high efficiency, high efficiency, and high integration.

  INDUSTRIAL APPLICABILITY The present invention is useful for a method for manufacturing a semiconductor device including an insulating oxide film that separates element formation regions in a group III nitride semiconductor layer.

(a)-(c) is principal part process sectional drawing which shows the manufacturing process of the semiconductor device which concerns on the 1st Embodiment of this invention. (a)-(c) is principal part process sectional drawing which shows the manufacturing process of the semiconductor device which concerns on the 1st Embodiment of this invention. (a)-(c) is principal part process sectional drawing which shows the manufacturing process of the semiconductor device which concerns on the 2nd Embodiment of this invention. (a)-(c) is principal part process sectional drawing which shows the manufacturing process of the semiconductor device which concerns on the 2nd Embodiment of this invention. (a)-(c) is principal part process sectional drawing which shows the manufacturing process of the semiconductor device which concerns on the 3rd Embodiment of this invention. (a)-(c) is principal part process sectional drawing which shows the manufacturing process of the semiconductor device which concerns on the 3rd Embodiment of this invention. (a)-(c) is principal part process sectional drawing which shows the manufacturing process of the semiconductor device which concerns on the 4th Embodiment of this invention. (a)-(c) is principal part process sectional drawing which shows the manufacturing process of the semiconductor device which concerns on the 4th Embodiment of this invention. It is sectional drawing which shows the structure of the conventional semiconductor device. It is sectional drawing which shows the structure of the conventional semiconductor device. It is sectional drawing which shows the structure of the conventional semiconductor device.

Explanation of symbols

10, 30, 50, 70 Semiconductor substrate 11A, 31A, 51A, 71A First region 11B, 31B, 51B, 71B Second region 11, 31, 51, 71 Deposition layer 12, 32, 52, 72 Select mask layer 13, 33, 53, 73 Modified region 33A Metal oxide film 14, 34, 74 Oxidized region 54A Element isolation oxidized region 54B MOS oxidized region 15, 35, 55, 75 Source electrode 16, 36, 56, 76 Drain electrode 17, 37, 57, 77 Gate electrodes 100, 200, 300 Semiconductor substrates 101A, 201A, 301A First region (gallium nitride compound semiconductor layer)
101B, 201B, 301B Second region (gallium nitride compound semiconductor layer)
102 Ion implantation region 202 Etching region 302 Oxidation region 103, 203, 303 Source electrode 104, 204, 304 Drain electrode 105, 205, 305 Gate electrode

Claims (8)

A method of manufacturing a semiconductor device for forming an insulating oxide film for separating an element formation region in a group III nitride semiconductor layer,
Forming a modified region of the group III nitride semiconductor layer in the group III nitride semiconductor layer so as to partition the element formation region in the group III nitride semiconductor layer;
Forming the insulating oxide film by oxidizing the modified region ,
The step of forming the modified region includes a step of forming the modified region by excessively dry-etching the group III nitride semiconductor layer .   The step of forming the modified region includes a step of forming the modified region by damaging the group III nitride semiconductor layer to form crystal defects. The manufacturing method of the semiconductor device of description. A method of manufacturing a semiconductor device for forming an insulating oxide film for separating an element formation region in a group III nitride semiconductor layer,
Forming a modified region of the group III nitride semiconductor layer in the group III nitride semiconductor layer so as to partition the element formation region in the group III nitride semiconductor layer;
Forming the insulating oxide film by oxidizing the modified region,
Wherein the step of forming the modified region, seen including a step of forming the modified region by ion implantation to said group III nitride semiconductor layer,
The ion implantation method of manufacturing a semi-conductor device characterized in that is carried out using aluminum, an ion composed of gallium or titanium. A method of manufacturing a semiconductor device for forming an insulating oxide film for separating an element formation region in a group III nitride semiconductor layer,
Forming a modified region of the group III nitride semiconductor layer in the group III nitride semiconductor layer so as to partition the element formation region in the group III nitride semiconductor layer;
Forming the insulating oxide film by oxidizing the modified region,
The step of forming the modified region, after forming a metal oxide film on the surface of the group III nitride semiconductor layer, viewed including the step of forming the modified region by performing heat treatment in a nitrogen atmosphere,
Method of manufacturing a semi-conductor device you wherein the metal oxide film is an oxide film of Ti, Ta or Mo. The step of forming the modified region, the semiconductor device according to any one of claims 1-4, characterized in that it comprises a step of forming the modified region while adjusting the degree of modification Production method. The step of forming the modified region includes a step of forming a plurality of the modified regions in the group III nitride semiconductor layer,
The step of forming the insulating oxide film by oxidizing said plurality of said modified regions, any one of the claims 1-5, characterized in that it comprises a step of forming a plurality of said insulating oxide film A method for manufacturing the semiconductor device according to the item. The step of forming the insulating oxide film by oxidizing the modified region while masking the device formation region, one of claims 1-6, characterized in that it comprises a step of forming the insulating oxide film A manufacturing method of a semiconductor device given in any 1 paragraph. Before Symbol dry etching, as the surface height of the surface height of the portion present in the element forming region in the group III nitride semiconductor layer and the insulating oxide film is the same, removal of the group III nitride semiconductor layer The method of manufacturing a semiconductor device according to claim 1, wherein:

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