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JP4744078B2 - Semiconductor wafer - Google Patents

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JP4744078B2
JP4744078B2 JP2003431820A JP2003431820A JP4744078B2 JP 4744078 B2 JP4744078 B2 JP 4744078B2 JP 2003431820 A JP2003431820 A JP 2003431820A JP 2003431820 A JP2003431820 A JP 2003431820A JP 4744078 B2 JP4744078 B2 JP 4744078B2
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semiconductor
inspection
dicing
pad
semiconductor element
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JP2005191334A (en
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勝喜 内海
隆博 隈川
芳宏 松島
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Panasonic Corp
Panasonic Holdings Corp
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Matsushita Electric Industrial Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H01L22/32—Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

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  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Dicing (AREA)

Description

本発明は、半導体素子をダイシングにより分割する半導体ウェーハに関するものである。   The present invention relates to a semiconductor wafer that divides a semiconductor element by dicing.

従来、半導体ウェーハのダイシング方法には、ダイヤモンドやＣＢＮの粒子をボンド材で保持させた環状のダイシングソーを高速回転させて、破砕加工する手法が最も一般的に用いられてきた。ダイシングソーによる加工は、ダイヤモンド粒子の粒径や、密度、ボンド材等のダイシングソー仕様や、回転速度、送り速度、切り込み深さなどの設備条件の改善と最適化により、加工品質の向上に取り組まれてきた。しかし、ダイシングソーによる加工は破砕加工であり、さらにダイシングレーンに配置されたプロセスコントロールモジュール（ＰＣＭ）は一般的にアルミニウム等の延性材料であるため、必ずチッピングやダイシングレーン上に形成された膜剥離、さらにメタルばりが発生するという問題点があった。   Conventionally, as a method for dicing a semiconductor wafer, a method of crushing by rotating an annular dicing saw in which diamond or CBN particles are held by a bonding material at a high speed has been most commonly used. Processing with a dicing saw works to improve processing quality by improving and optimizing the diamond particle size, density, bond material and other dicing saw specifications, and rotational speed, feed speed, and cutting depth. I have been. However, since the processing by the dicing saw is crushing, and the process control module (PCM) placed in the dicing lane is generally a ductile material such as aluminum, chipping and film peeling always formed on the dicing lane Further, there was a problem that metal flash was generated.

一方、半導体素子のさらなる微細化を実現するために露光解像度を向上させる必要があり、露光装置のＮＡ（レンズ開口数）の向上と光源の短波長化が進んでいるが、これは同時に焦点深度の減少をもたらす。つまり、ウェーハ表面に大きな凹凸がある場合は狙った解像度が得られないことになり、ウェーハ表面を平坦化する必要がある。平坦化の方法として、ＳＯＧ（Ｓｐｉｎ ｏｎ Ｇｌａｓｓ）膜の塗布やエッチバック法、ＣＭＰ（化学的機械研磨）などを用い、酸化膜やメタル配線の段差をなくしている。この平坦化は、半導体ウェーハ上の半導体素子部のみならず、ダイシングレーン上も行なわれる。その結果、ＳＯＧや層間絶縁膜などが平坦化後の残膜として形成されている。   On the other hand, in order to realize further miniaturization of semiconductor elements, it is necessary to improve the exposure resolution. The NA (lens numerical aperture) of the exposure apparatus and the wavelength of the light source have been shortened. Resulting in a decrease. In other words, if there are large irregularities on the wafer surface, the targeted resolution cannot be obtained, and it is necessary to flatten the wafer surface. As a planarization method, a step of an SOG (Spin on Glass) film, an etch back method, CMP (Chemical Mechanical Polishing), or the like is used to eliminate a step of an oxide film or a metal wiring. This planarization is performed not only on the semiconductor element portion on the semiconductor wafer but also on the dicing lane. As a result, SOG, an interlayer insulating film, and the like are formed as a remaining film after planarization.

ダイシングは前述のようにダイヤモンドやＣＢＮの粒子による破砕加工であるため、これらの残膜上をダイシングすると膜からメタルばりが発生する場合がある。それは、とくに残膜が脆弱であったり下層との密着力が弱い場合に顕著に発生する。   Since dicing is a crushing process using diamond or CBN particles as described above, a metal flash may be generated from the film when the remaining film is diced. This is particularly noticeable when the remaining film is fragile or the adhesion with the lower layer is weak.

これらのＰＣＭや残膜等の半導体素子検査用パッドや半導体検査用素子から発生するメタルばりは、半導体素子内部へダメージを及ぼす危険性があるだけではなく、剥離したメタルばりのかけらが組立工程などで端子ショートなどの不具合をもたらすという問題点があった。   The metal flash generated from the semiconductor element inspection pads such as PCM and residual film and the semiconductor inspection element not only has a risk of damaging the inside of the semiconductor element, but the peeled pieces of the metal flash may cause an assembly process, etc. However, there was a problem of causing problems such as terminal short circuit.

そのため、ダイシングにおいて従来から様々な対策をしている。
例えば、半導体ウェーハのダイシングレーン内の半導体素子検査用パッドや半導体検査用素子の平面内部のＡｌ膜を十字に除去しダイシングすることで発生するメタルばり量を極力少なくすることを提供している（例えば、特許文献１参照）。 For this reason, various countermeasures have conventionally been taken in dicing.
For example, it is possible to reduce the amount of metal flash generated by dicing by removing the cross-section of the semiconductor element inspection pad in the dicing lane of the semiconductor wafer and the Al film inside the plane of the semiconductor inspection element. For example, see Patent Document 1).

しかしながら、この方法によると、メタルばりはある程度は抑制できるが完全に除去できず剥離したメタルばりのかけらが組立工程などで端子ショートなどの不具合をもたらすという問題点があった。
特開平２−１１８６４１号公報 However, according to this method, metal flash can be suppressed to some extent, but it cannot be completely removed, and there has been a problem that a fragment of peeled metal flash causes a problem such as a short circuit in an assembly process.
JP-A-2-118864

本発明の半導体ウェーハは、上記問題点を解決するために、半導体素子検査用パッドや半導体検査用素子が形成されていても、ダイシングの際に、半導体素子検査用パッドや半導体検査用素子から発生するＰＣＭや残膜等のメタルばりが発生しにくくなり、組立工程等において剥離したメタルばりにより端子ショートなどの不具合を発生させないことを目的とする。   In order to solve the above problems, the semiconductor wafer of the present invention is generated from the semiconductor element inspection pad or the semiconductor inspection element during dicing even if the semiconductor element inspection pad or the semiconductor inspection element is formed. The object is to prevent metal flashes such as PCM and residual film from occurring, and to prevent problems such as terminal short-circuits due to metal flashes that have been peeled off during an assembly process or the like.

また、あらかじめ半導体装置に設置しておく半導体組立用パッドの数量を減少させ、半導体装置の面積を減少させることにより、ウェーハ当りの半導体素子の取り数を向上することを目的とする。   It is another object of the present invention to improve the number of semiconductor elements per wafer by reducing the number of semiconductor assembly pads previously installed in the semiconductor device and reducing the area of the semiconductor device.

上記目的を達成するために、本発明の半導体ウェーハは、複数の半導体素子領域と、前記複数の半導体素子領域各々を囲むように形成されたダイシングレーンと、前記ダイシングレーンに形成された半導体検査用素子と、前記半導体素子領域に形成された半導体検査用パッドと、前記半導体素子領域に形成されたボンディングパッドと、前記半導体検査用素子と前記半導体検査用パッドとをつなぐ配線と、前記半導体素子領域で前記半導体検査用パッドおよび前記ボンディングパッドの各々に接続されるボンディングパッド配線とを備え、前記半導体検査用素子は、前記複数の半導体素子領域を個片に分離する際にダイシングされる領域に形成され、 前記半導体素子検査用パッドは、前記複数の半導体素子領域を個片に分離した後に、前記ボンディングパッドとともに半導体組立用パッドとして利用することを特徴とする。 To achieve the above object, a semiconductor wafer of the present invention includes a plurality of semiconductor element regions, a dicing lane formed so as to surround each of the plurality of semiconductor element regions, and a semiconductor inspection formed in the dicing lane. An element, a semiconductor inspection pad formed in the semiconductor element region, a bonding pad formed in the semiconductor element region, a wiring connecting the semiconductor inspection element and the semiconductor inspection pad, and the semiconductor element region And the semiconductor inspection pad and the bonding pad wiring connected to each of the bonding pads, and the semiconductor inspection element is formed in a region diced when the plurality of semiconductor element regions are separated into individual pieces. And the semiconductor element testing pad separates the plurality of semiconductor element regions into individual pieces and It is used as a semiconductor assembly pad together with a bonding pad .

この半導体ウェーハによれば、半導体素子検査用パッドと、半導体検査用素子と、半導体素子検査用パッドと半導体検査用素子とつなぐ配線とがそれぞれ独立しており、特にウェーハ検査のための半導体素子検査用パッドをダイシングしなくてもよいためメタルばりが発生しにくくなる。   According to this semiconductor wafer, the semiconductor element inspection pad, the semiconductor inspection element, and the wiring connecting the semiconductor element inspection pad and the semiconductor inspection element are independent, and particularly the semiconductor element inspection for wafer inspection. Since metal pads do not have to be diced, metal flash is less likely to occur.

また、本発明の半導体ウェーハは、複数の半導体素子領域と、前記複数の半導体素子領域各々を囲むように形成されたダイシングレーンと、前記ダイシングレーンに形成された半導体検査用素子と、前記ダイシングレーンに形成された前記半導体検査用パッドと、前記半導体検査用素子と前記半導体検査用パッドとをつなぐ配線と、を備え、前記半導体検査用素子は、前記複数の半導体素子領域を個片に分離する際にダイシングされる領域に形成され、前記半導体検査用パッドは、前記複数の半導体素子領域を個片に分離する際にダイシングされない領域に形成されることを特徴とする。 The semiconductor wafer of the present invention includes a plurality of semiconductor element regions, a dicing lane formed so as to surround each of the plurality of semiconductor element regions, a semiconductor inspection element formed in the dicing lane, and the dicing lane. The semiconductor testing pad formed on the wiring, and a wiring connecting the semiconductor testing element and the semiconductor testing pad, wherein the semiconductor testing element separates the plurality of semiconductor element regions into pieces. The semiconductor inspection pad is formed in a region that is not diced when the plurality of semiconductor element regions are separated into individual pieces .

また、前記半導体検査用素子は前記ダイシングレーンの中心部に、前記半導体検査用パッドは前記ダイシングレーンの前記半導体素子領域近傍に形成されても良い。The semiconductor inspection element may be formed in the center of the dicing lane, and the semiconductor inspection pad may be formed in the vicinity of the semiconductor element region of the dicing lane.

また、前記半導体検査用素子と、前記配線とが絶縁膜に覆われていることが好ましい。 The semiconductor testing element and the wiring are preferably covered with an insulating film .

また、前記半導体検査用素子の幅をダイシング切削幅よりも細くし、ダイシングの際に前記半導体検査用素子を取り除くことが好ましい。 Also, the width of the semiconductor inspection device thinner than the dicing width of cut, it is preferable to remove the semiconductor inspection device during dicing.

この半導体ウェーハによれば、完全に半導体検査用素子が取り除くことができメタルばりが発生しない。   According to this semiconductor wafer, the element for semiconductor inspection can be completely removed, and metal flash does not occur.

本発明に係る半導体ウェーハは、半導体素子検査用パッドを半導体素子領域に形成したり、ダイシングレーンのダイシングしない領域に形成することにより、ダイシングに際し、ＰＣＭや残膜等の半導体素子検査用パッドや半導体検査用素子から発生するメタルばりが発生しにくくなり、剥離したメタルばりのかけらが組立工程などで端子ショートなどの不具合を発生させないことができる。   The semiconductor wafer according to the present invention has a semiconductor element inspection pad formed in a semiconductor element region or a non-dicing region of a dicing lane so that a semiconductor element inspection pad such as a PCM or a remaining film or a semiconductor can be used for dicing. The metal flash generated from the inspection element is less likely to occur, and the peeled pieces of the metal flash can prevent the occurrence of problems such as a short circuit in the assembly process.

また、半導体素子検査用パッドを半導体組立用パッドと共有することにより、あらかじめ半導体装置に設置しておく半導体組立用パッドの数量を減少することができ、半導体装置の面積を減少できるので、ウェーハ当りの半導体装置の取り数を向上することができる。   Also, by sharing the semiconductor element testing pads with the semiconductor assembly pads, the number of semiconductor assembly pads that are installed in the semiconductor device in advance can be reduced, and the area of the semiconductor device can be reduced. The number of semiconductor devices obtained can be improved.

本発明の半導体ウェーハの実施の形態について、以下、図面を参照しながら説明する。
（実施の形態１）
図１（ａ）は本発明の実施の形態１における半導体ウェーハのダイシングレーンおよびその周辺を示す平面図、図１（ｂ）は本発明の実施の形態１における半導体ウェーハのダイシング後の平面図を示す。また、図１（ｃ）は図１（ａ）に示すＡ−Ａ断面図であり、図１（ｄ）は図１（ｂ）に示すＣ−Ｃ断面図である。さらに、図１（ｅ）は図１（ａ）に示すＢ部分の拡大図であり、図１（ｆ）は図１（ｂ）に示すＤ部分の拡大図である。 Embodiments of a semiconductor wafer according to the present invention will be described below with reference to the drawings.
(Embodiment 1)
FIG. 1A is a plan view showing a dicing lane and its periphery of a semiconductor wafer in the first embodiment of the present invention, and FIG. 1B is a plan view after dicing of the semiconductor wafer in the first embodiment of the present invention. Show. Moreover, FIG.1 (c) is AA sectional drawing shown to Fig.1 (a), FIG.1 (d) is CC sectional drawing shown in FIG.1 (b). Further, FIG. 1 (e) is an enlarged view of a portion B shown in FIG. 1 (a), and FIG. 1 (f) is an enlarged view of a portion D shown in FIG. 1 (b).

図１において、１は半導体ウェーハ、２はダイシングレーン、２ａはダイシングラインの中心、３は半導体素子領域、４はダイシング切削幅の例、５はボンディングパッド、６は半導体検査用素子、２１は配線、２３は半導体素子検査用パッドを示している。   In FIG. 1, 1 is a semiconductor wafer, 2 is a dicing lane, 2a is the center of a dicing line, 3 is a semiconductor element region, 4 is an example of a dicing cutting width, 5 is a bonding pad, 6 is a semiconductor inspection element, and 21 is a wiring. , 23 indicate semiconductor element inspection pads.

半導体ウェーハ１にはダイシングレーン２がある。ダイシングレーン２は、切断を行う仮想ラインである。半導体ウェーハ１上には、トランジスタなどの能動素子や、抵抗素子などの受動素子、配線や、ボンディングパッド５などが半導体素子形成面に形成されており、ダイシングレーン２上にも、層間絶縁膜や、表面保護膜などが形成される場合がある。   The semiconductor wafer 1 has a dicing lane 2. The dicing lane 2 is a virtual line for cutting. An active element such as a transistor, a passive element such as a resistance element, a wiring, a bonding pad 5 and the like are formed on the semiconductor element forming surface on the semiconductor wafer 1, and an interlayer insulating film or the like is also formed on the dicing lane 2. In some cases, a surface protective film or the like is formed.

本発明の特徴は、半導体素子領域に半導体素子検査用パッド２３を備え、半導体素子検査用パッド２３とダイシングレーンに設けられた半導体検査用素子６とつなぐ配線２１とが形成されており、半導体素子検査用パッド２３をダイシングしなくてもよく、従来、ダイシングレーン上に半導体素子検査用パッド２３が形成されていた為に必然的に半導体素子検査用パッド２３をダイシングしメタルばりを発生させ問題を発生させていたが、上記の如くダイシングレーン上に半導体素子検査用パッド２３がない為にメタルばりを発生しないことを特徴としている。さらに、前記半導体検査用素子６と、半導体素子検査用パッド２３と半導体検査用素子６とつなぐ配線２１とが表面保護膜などの絶縁膜下に覆われ露出していない構造にすることもできる。   A feature of the present invention is that a semiconductor element inspection pad 23 is provided in a semiconductor element region, and a semiconductor element inspection pad 23 and a wiring 21 connected to a semiconductor inspection element 6 provided in a dicing lane are formed. The inspection pad 23 does not have to be diced. Conventionally, since the semiconductor element inspection pad 23 is formed on the dicing lane, the semiconductor element inspection pad 23 is inevitably diced to generate a metal flash. However, since there is no semiconductor element inspection pad 23 on the dicing lane as described above, no metal flash is generated. Furthermore, the semiconductor inspection element 6, the semiconductor element inspection pad 23, and the wiring 21 connecting the semiconductor inspection element 6 may be covered with an insulating film such as a surface protective film and not exposed.

このように半導体素子検査用パッド２３をダイシングする必要がないために、メタルばりの発生が抑制でき、さらに、半導体検査用素子６と配線２１とが表面保護膜などの絶縁膜下に覆われ露出していないことでメタルばりの発生が抑制でき、剥離したメタルばりのかけらが組立工程などで端子ショートなどの不具合を防ぐことができる。   Since it is not necessary to dice the semiconductor element inspection pad 23 in this way, the occurrence of metal flash can be suppressed, and the semiconductor inspection element 6 and the wiring 21 are covered and exposed under an insulating film such as a surface protective film. By not doing so, it is possible to suppress the occurrence of metal flash, and it is possible to prevent defects such as terminal short-circuits in the assembling process or the like due to the peeled pieces of metal flash.

また、以上の説明では、半導体検査用素子をダイシングレーンに設けたが、半導体素子領域に形成しても良い。
（実施の形態２）
図２（ａ）は本発明の実施の形態２における半導体ウェーハのダイシングレーンおよびその周辺を示す平面図、図２（ｂ）は本発明の実施の形態２における半導体ウェーハのダイシング後の平面図を示す。 In the above description, the semiconductor inspection element is provided in the dicing lane, but may be formed in the semiconductor element region.
(Embodiment 2)
FIG. 2A is a plan view showing a dicing lane and its periphery of a semiconductor wafer in the second embodiment of the present invention, and FIG. 2B is a plan view after dicing of the semiconductor wafer in the second embodiment of the present invention. Show.

図２において、２はダイシングレーン、２ａはダイシングラインの中心、３は半導体素子領域、４はダイシング切削幅の例、５はボンディングパッド、６は半導体検査用素子、２１は配線、２２はボンディングパッド配線、２３は半導体素子検査用パッドを示している。   In FIG. 2, 2 is a dicing lane, 2a is the center of a dicing line, 3 is a semiconductor element region, 4 is an example of a dicing cutting width, 5 is a bonding pad, 6 is a semiconductor inspection element, 21 is a wiring, and 22 is a bonding pad. A wiring 23 indicates a semiconductor element inspection pad.

本発明の特徴は半導体素子検査用パッド２３がボンディングパッド配線２２と接続されており、さらに半導体素子検査用パッド２３が半導体ウェーハ１の半導体素子領域３内に配置されており、ダイシング等により半導体ウェーハを個々の半導体チップに分離することで半導体検査用素子６が分離され、半導体素子検査用パッド２３を半導体組立用パッド５に利用することを特徴としている。従来は、半導体装置検査用パッド２３がダイシングレーン上に形成されていた為、ダイシングによって半導体素子検査用パッド２３が破壊されてしまい、半導体組立用パッド５に利用することができず、新たに半導体素子領域３内に半導体組立用パッド５を形成させ、かつダイシングレーン内に半導体素子検査用パッド２３も同時に形成させなければならず、半導体ウェーハ１内の半導体組立用パッド５と半導体素子検査用パッド２３をそれぞれ形成させるため、半導体ウェーハ１内の半導体素子領域３の取り数が減り、半導体ウェーハ１のコストアップにつながっていた。実施の形態２は、実施の形態１の半導体素子検査用パッド２３を半導体組立用パッド５に利用することを特徴させることでコストダウンを図る発展系である。
この半導体ウェーハによれば、メタルばりの発生が抑制できると共に、半導体素子検査用パッドを半導体組立用パッドに利用できるため、あらかじめ半導体装置に設置しておく半導体組立用パッドの数量を減少することができ半導体装置の面積を減少でき、ウェーハ当りの半導体装置の取り数アップが可能で半導体装置のコストダウンが可能となる。 The feature of the present invention is that the semiconductor element inspection pad 23 is connected to the bonding pad wiring 22, and further the semiconductor element inspection pad 23 is disposed in the semiconductor element region 3 of the semiconductor wafer 1, and the semiconductor wafer is subjected to dicing or the like. The semiconductor inspection element 6 is separated by separating the semiconductor chip into individual semiconductor chips, and the semiconductor element inspection pad 23 is used as the semiconductor assembly pad 5. Conventionally, since the semiconductor device inspection pad 23 is formed on the dicing lane, the semiconductor element inspection pad 23 is destroyed by the dicing and cannot be used as the semiconductor assembly pad 5, and a new semiconductor is provided. The semiconductor assembly pad 5 in the element region 3 and the semiconductor element inspection pad 23 in the dicing lane must be formed at the same time, and the semiconductor assembly pad 5 and the semiconductor element inspection pad in the semiconductor wafer 1 are formed. Therefore, the number of semiconductor element regions 3 in the semiconductor wafer 1 is reduced, leading to an increase in the cost of the semiconductor wafer 1. The second embodiment is an advanced system for reducing the cost by using the semiconductor element test pad 23 of the first embodiment as the semiconductor assembly pad 5.
According to this semiconductor wafer, the occurrence of metal flash can be suppressed, and the semiconductor element inspection pad can be used as a semiconductor assembly pad. Therefore, the number of semiconductor assembly pads previously installed in a semiconductor device can be reduced. In addition, the area of the semiconductor device can be reduced, the number of semiconductor devices per wafer can be increased, and the cost of the semiconductor device can be reduced.

また、以上の説明では、半導体検査用素子をダイシングレーンに設けたが、半導体素子領域に形成しても良い。
（実施の形態３）
図３（ａ）は本発明の実施の形態３における半導体ウェーハのダイシングレーンおよびその周辺を示す平面図で、図３（ｂ）は本発明の実施の形態３における半導体ウェーハのダイシング後の平面図を示す。 In the above description, the semiconductor inspection element is provided in the dicing lane, but may be formed in the semiconductor element region.
(Embodiment 3)
FIG. 3A is a plan view showing the dicing lane of the semiconductor wafer and its periphery in the third embodiment of the present invention, and FIG. 3B is a plan view after dicing of the semiconductor wafer in the third embodiment of the present invention. Indicates.

図３において、２はダイシングレーン、２ａはダイシングラインの中心、３は半導体素子領域、４はダイシング切削幅の例、５はボンディングパッド、６は半導体検査用素子、２１は配線、２３は半導体素子検査用パッドを示している。   In FIG. 3, 2 is a dicing lane, 2a is the center of a dicing line, 3 is a semiconductor element region, 4 is an example of a dicing cutting width, 5 is a bonding pad, 6 is a semiconductor inspection element, 21 is a wiring, and 23 is a semiconductor element. A pad for inspection is shown.

本発明の特徴は、半導体素子検査用パッド２３が半導体ウェーハのダイシングレーン内のダイシングされない領域に配置されており、半導体素子検査用パッド２３をダイシングしなくてもよいことである。さらに、図１同様半導体検査用素子６と、半導体素子検査用パッド２３と半導体検査用素子６とつなぐ配線２１とが表面保護膜などの絶縁膜下に覆われ露出していない構造にすることもできる。   The feature of the present invention is that the semiconductor element inspection pad 23 is disposed in a non-diced region in the dicing lane of the semiconductor wafer, and the semiconductor element inspection pad 23 does not have to be diced. Further, as in FIG. 1, the semiconductor inspection element 6, the semiconductor element inspection pad 23, and the wiring 21 connecting the semiconductor inspection element 6 may be covered with an insulating film such as a surface protective film and not exposed. it can.

このように、半導体素子検査用パッド２３をダイシングしなくてもよいことで、メタルばりの発生が抑制でき、さらに、半導体検査用素子６も配線２１とが表面保護膜などの絶縁膜下に覆われ露出していないことでメタルばりの発生が抑制でき、剥離したメタルばりのかけらが組立工程などで端子ショートなどの不具合を防ぐことができる。
（実施の形態４）
図４（ａ）は従来の半導体ウェーハのダイシングレーンおよびその周辺を示す断面図で、図４（ｂ）は従来の半導体ウェーハのダイシング後の断面図を示す。さらに、図４（ｃ）は本発明の実施の形態４における半導体ウェーハのダイシングレーンおよびその周辺を示す断面図で、図４（ｄ）は本発明の実施の形態４における半導体ウェーハのダイシング後の断面図を示す。図中において、４はダイシング切削幅の例、６は半導体検査用素子を示している。 Thus, since it is not necessary to dice the semiconductor element inspection pad 23, the occurrence of metal flash can be suppressed, and the semiconductor inspection element 6 is also covered with the wiring 21 under an insulating film such as a surface protective film. Since it is not exposed, the occurrence of metal flash can be suppressed, and the pieces of peeled metal flash can prevent problems such as terminal short-circuiting during the assembly process.
(Embodiment 4)
4A is a cross-sectional view showing a dicing lane of a conventional semiconductor wafer and its periphery, and FIG. 4B is a cross-sectional view of the conventional semiconductor wafer after dicing. Further, FIG. 4C is a cross-sectional view showing the dicing lane and its periphery of the semiconductor wafer in the fourth embodiment of the present invention, and FIG. 4D is a view after the dicing of the semiconductor wafer in the fourth embodiment of the present invention. A cross-sectional view is shown. In the figure, 4 indicates an example of a dicing cutting width, and 6 indicates a semiconductor inspection element.

本発明の特徴はダイシング切削幅７と半導体検査用素子６の幅を任意に選択し、例えば、図４（ｃ）および図４（ｄ）では、半導体検査用素子６の幅をダイシング切削幅７よりも細くし、ダイシングブレードにて半導体検査用素子６を取り除くことを特徴としている。   A feature of the present invention is that the dicing cutting width 7 and the width of the semiconductor inspection element 6 are arbitrarily selected. For example, in FIGS. 4C and 4D, the width of the semiconductor inspection element 6 is set to the dicing cutting width 7. The semiconductor inspection element 6 is removed with a dicing blade.

このように、半導体検査用素子６の幅をダイシング切削幅７よりも細くすることにより、完全に半導体検査用素子が取り除くことができるため、メタルばりが発生せず、剥離したメタルばりのかけらが組立工程などで端子ショートなどの不具合を防ぐことができる。   Thus, since the semiconductor inspection element can be completely removed by making the width of the semiconductor inspection element 6 smaller than the dicing cutting width 7, metal flash does not occur, and the peeled pieces of metal flash are not generated. It is possible to prevent problems such as a short circuit in the assembly process.

本発明の半導体ウェーハは、ＰＣＭや残膜等の半導体素子検査用パッドや半導体検査用素子から発生するメタルばりが発生しにくく、剥離したメタルばりのかけらが組立工程などで端子ショートなどの不具合の発生を抑制することが可能であり、半導体素子をダイシングにより分割する半導体ウェーハ等に有効である。   The semiconductor wafer of the present invention is less prone to metal flash generated from semiconductor element inspection pads such as PCM and residual film and semiconductor inspection elements. It is possible to suppress the generation, and it is effective for a semiconductor wafer or the like in which a semiconductor element is divided by dicing.

（ａ）本発明の実施の形態１における半導体ウェーハのダイシングレーンおよびその周辺を示す平面図（ｂ）本発明の実施の形態１における半導体ウェーハのダイシング後の平面図（ｃ）図１（ａ）に示すＡ−Ａ断面図（ｄ）図１（ｂ）に示すＣ−Ｃ断面図（ｅ）図１（ｃ）に示すＢ部分の拡大図（ｆ）図１（ｄ）に示すＤ部分の拡大図(A) Plan view showing the dicing lane and its periphery of the semiconductor wafer in the first embodiment of the present invention (b) Plan view after dicing of the semiconductor wafer in the first embodiment of the present invention (c) FIG. A sectional view taken along the line A-A shown in FIG. 1D. A sectional view taken along the line C-C shown in FIG. 1B. FIG. 1C is an enlarged view of the portion B shown in FIG. Enlarged view （ａ）本発明の実施の形態２における半導体ウェーハのダイシングレーンおよびその周辺を示す平面図（ｂ）本発明の実施の形態２における半導体ウェーハのダイシング後の平面図(A) Plan view showing the dicing lane of the semiconductor wafer and its periphery in the second embodiment of the present invention (b) Plan view after dicing of the semiconductor wafer in the second embodiment of the present invention （ａ）本発明の実施の形態３における半導体ウェーハのダイシングレーンおよびその周辺を示す平面図（ｂ）本発明の実施の形態３における半導体ウェーハのダイシング後の平面図(A) Plan view showing the dicing lane of the semiconductor wafer and its periphery in the third embodiment of the present invention (b) Plan view after dicing of the semiconductor wafer in the third embodiment of the present invention （ａ）従来の半導体ウェーハのダイシングレーンおよびその周辺を示す断面図（ｂ）従来の半導体ウェーハのダイシング後の断面図（ｃ）本発明の実施の形態４における半導体ウェーハのダイシングレーンおよびその周辺を示す断面図（ｄ）本発明の実施の形態４における半導体ウェーハのダイシング後の断面図(A) Cross-sectional view showing the dicing lane of the conventional semiconductor wafer and its periphery (b) Cross-sectional view after dicing of the conventional semiconductor wafer (c) The dicing lane of the semiconductor wafer and its periphery in the fourth embodiment of the present invention Sectional view shown (d) Sectional view after dicing of the semiconductor wafer in the fourth embodiment of the present invention

符号の説明Explanation of symbols

１ 半導体ウェーハ
２ ダイシングレーン
２ａ ダイシングラインの中心
３ 半導体素子領域
４ ダイシング切削幅の例
５ ボンディングパッド
６ 半導体検査用素子
７ ダイシング切削幅
２１ 配線
２２ ボンディングパッド配線
２３ 半導体素子検査用パッド DESCRIPTION OF SYMBOLS 1 Semiconductor wafer 2 Dicing lane 2a Center of a dicing line 3 Semiconductor element area | region 4 Example of dicing cutting width 5 Bonding pad 6 Semiconductor inspection element 7 Dicing cutting width 21 Wiring 22 Bonding pad wiring 23 Semiconductor element inspection pad

Claims (5)

複数の半導体素子領域と、
前記複数の半導体素子領域各々を囲むように形成されたダイシングレーンと、
前記ダイシングレーンに形成された半導体検査用素子と、
前記半導体素子領域に形成された半導体検査用パッドと、
前記半導体素子領域に形成されたボンディングパッドと、
前記半導体検査用素子と前記半導体検査用パッドとをつなぐ配線と、
前記半導体素子領域で前記半導体検査用パッドおよび前記ボンディングパッドの各々に接続されるボンディングパッド配線と
を備え、
前記半導体検査用素子は、前記複数の半導体素子領域を個片に分離する際にダイシングされる領域に形成され、
前記半導体素子検査用パッドは、前記複数の半導体素子領域を個片に分離した後に、前記ボンディングパッドとともに半導体組立用パッドとして利用することを特徴とする半導体ウェーハ。 A plurality of semiconductor element regions;
A dicing lane formed to surround each of the plurality of semiconductor element regions;
A semiconductor inspection element formed in the dicing lane;
A semiconductor testing pad formed in the semiconductor element region;
Bonding pads formed in the semiconductor element region;
A wiring connecting the semiconductor testing element and the semiconductor testing pad;
A bonding pad wiring connected to each of the semiconductor inspection pad and the bonding pad in the semiconductor element region ;
The semiconductor inspection element is formed in a region that is diced when the plurality of semiconductor element regions are separated into individual pieces,
The semiconductor element inspection pad is used as a semiconductor assembly pad together with the bonding pad after separating the plurality of semiconductor element regions into individual pieces . 複数の半導体素子領域と、
前記複数の半導体素子領域各々を囲むように形成されたダイシングレーンと、
前記ダイシングレーンに形成された半導体検査用素子と、
前記ダイシングレーンに形成された前記半導体検査用パッドと、
前記半導体検査用素子と前記半導体検査用パッドとをつなぐ配線と、
を備え、
前記半導体検査用素子は、前記複数の半導体素子領域を個片に分離する際にダイシングされる領域に形成され、
前記半導体検査用パッドは、前記複数の半導体素子領域を個片に分離する際にダイシングされない領域に形成されることを特徴とする半導体ウェーハ。 A plurality of semiconductor element regions;
A dicing lane formed to surround each of the plurality of semiconductor element regions;
A semiconductor inspection element formed in the dicing lane;
The semiconductor testing pad formed on the dicing lane;
A wiring connecting the semiconductor testing element and the semiconductor testing pad;
With
The semiconductor inspection element is formed in a region that is diced when the plurality of semiconductor element regions are separated into individual pieces,
The semiconductor inspection pad is formed in a region that is not diced when the plurality of semiconductor element regions are separated into individual pieces . 前記半導体検査用素子は前記ダイシングレーンの中心部に、前記半導体検査用パッドは前記ダイシングレーンの前記半導体素子領域近傍に形成されたことを特徴とする請求項２に記載の半導体ウェーハ。 3. The semiconductor wafer according to claim 2 , wherein the semiconductor inspection element is formed in a central portion of the dicing lane, and the semiconductor inspection pad is formed in the vicinity of the semiconductor element region of the dicing lane . 前記半導体検査用素子と、前記配線とが絶縁膜に覆われていることを特徴とする請求項１乃至３のいずれかに記載の半導体ウェーハ。 4. The semiconductor wafer according to claim 1, wherein the semiconductor inspection element and the wiring are covered with an insulating film . 前記半導体検査用素子の幅をダイシング切削幅よりも細くし、ダイシングの際に前記半導体検査用素子を取り除くことを特徴とする請求項１乃至４のいずれかに記載の半導体ウェーハ。 5. The semiconductor wafer according to claim 1, wherein a width of the semiconductor inspection element is made smaller than a dicing cutting width, and the semiconductor inspection element is removed at the time of dicing .
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