JP4702209B2 - Signal processing apparatus, signal processing method, and program - Google Patents

Description

  The present invention relates to a signal processing device, a signal processing method, and a program for realizing power saving in a startup standby state.

  FIG. 1 shows a configuration example of a transmission system that transmits a digital video signal conforming to a transmission standard such as DVI (Digital Visual Interface) or HDMI (High Definite / On Multimedia Interface) using an electric signal cable.

  The monitor device 11 is a video signal input device that receives and displays a video signal such as a CRT or LCD.

  The source device 12 is a video signal output device that outputs a video signal such as a TV tuner or a hard disk recorder.

  The electrical cable 13 is, for example, a video signal composed of differential electrical signals using two signal lines for one channel called TMDS (Transition Minimized Differential Signaling), and an RGB three-channel RGB signal, It has four signal lines for transmitting a total of four signals with a synchronizing signal for synchronizing RGB signals.

  The monitor device 11 includes a video signal I / F unit 21 and a control signal I / F unit 22, and the source device 12 includes a video signal I / F unit 31 and a control signal I / F unit 32. Configured.

  The video signal I / F unit 21 of the monitor device 11 and the video signal I / F unit 31 of the source device 12 are respectively connected to the electric cable 13, and the monitor device 11 and the source device 12 are connected to the video signal I / F unit. 21 and the video signal I / F unit 31 transmit and receive video signals.

  The control signal I / F unit 22 of the monitor device 11 and the control signal I / F unit 32 of the source device 12 are also connected to the electric cable 13, and the monitor device 11 and the source device 12 are connected to the control signal I / F unit. 22 and the control signal I / F unit 32 are used to transmit and receive control signals for operating instructions of the devices.

  By the way, the video signal and the control signal transmitted / received in this system are electric signals. However, since the electric signal has a large transmission attenuation factor in the high frequency band portion, the electric signal is transmitted through the electric cable 13 in this way. In this case, there is a problem that the transmission distance of the electric signal in the high frequency band is limited to about several meters.

  For example, when transmitting a digital video signal of a standard called Full HD, the pixel rate of the video signal is 148.5 Mbps, and the transmission bandwidth per channel is 1.485 Gbps when transmitted using the TMDS transmission standard. Therefore, it is difficult to transmit this digital video signal over a long distance using the electric cable 13.

  Therefore, a method has been developed in which an optical signal having a transmission attenuation factor of a signal in a high frequency band which is very small compared with an electric signal is transmitted instead of the electric signal.

  FIG. 2 shows a configuration example of an optical transmission system (see Patent Document 1). In this system, an optical signal cable 53 is provided instead of the electric cable 13 of FIG. 1, and a monitor transmission processing unit 51 is provided between the monitor device 11 and the optical signal cable 53. A source transmission processing unit 52 is provided between the devices 12.

  The source transmission processing unit 52 multiplexes the digital video signal output from the source device 12 and a control signal such as DDC defined by DVI or HDMI, and converts the multiplexed signal into an optical signal. The data is transmitted to the monitor transmission processing unit 51 via the optical signal cable 53.

  The monitor transmission processing unit 51 converts the optical signal transmitted via the optical signal cable 53 into an electrical signal, separates it into a digital video signal and a control signal, and supplies them to the monitor device 11.

  The monitor transmission processing unit 51 includes an 0 / E conversion unit 61, an electric signal processing unit 62, and an E / 0 conversion unit 63.

  The 0 / E conversion unit 61 converts an optical signal transmitted from the source transmission processing unit 52 via the optical signal cable 53 into an electrical signal, and outputs the electrical signal to the electrical signal processing unit 62.

  The electric signal processing unit 62 converts the electric signal supplied from the O / E conversion unit 61 into a parallel signal. Here, the optical signal cable 53 is composed of two optical signal lines for transmission and reception, and the transmission format of each optical signal line is a serial transmission format. Since the optical signal transmitted via the serial signal is in the serial signal format, the electrical signal converted by the 0 / E converter 61 is a signal in the serial signal format.

  The electric signal processing unit 62 also separates the multiplexed signal obtained as a result of conversion into the parallel signal format into a video signal and a control signal, and the resulting video signal is based on a predetermined digital video signal transmission standard. The video signal format is converted to the video signal / F unit 21 of the monitor device 11.

  The E / 0 conversion unit 63 converts the electrical signal multiplexed in the electrical signal processing unit 61 into an optical signal and outputs the optical signal to the optical signal cable 53.

  The source transmission processing unit 52 includes an electric signal processing unit 71, an E / 0 conversion unit 72, and a 0 / E conversion unit 73.

  The electric signal processing unit 71 transmits a video signal based on a predetermined digital video signal transmission standard (for example, DVI or HDMI) output from the video signal I / F unit 31 of the source device 12 to the monitor device 11. Necessary data is extracted from the video signal based on the predetermined digital video signal transmission standard.

  The electric signal processing unit 71 time-divides the data extracted from the video signal based on a predetermined digital video signal transmission standard and the control signal output from the control signal I / F unit 32 of the source device 12, respectively. Multiplex in one signal.

  The electric signal processing unit 71 converts the multiplexed signal into a serial signal by performing code conversion suitable for optical transmission.

  The electrical signal processing unit 71 is also an optical signal transmitted from the monitor device 11 via the optical signal cable 53 and is converted into an electrical signal by the 0 / E conversion unit 73. The control signal obtained as a result of the separation is output to the control signal I / F unit 32 of the source device 12.

  The E / 0 conversion unit 72 converts the electrical signal multiplexed and serialized by the electrical signal processing unit 71 into an optical signal and outputs the optical signal to the optical signal cable 53.

  The 0 / E conversion unit 73 detects an optical signal transmitted from the monitor transmission processing unit 51 via the optical signal cable 53, converts the optical signal into an electrical signal, and outputs the electrical signal to the electrical signal processing unit 71.

  Thus, by converting the digital video signal into an optical signal and transmitting it through the optical signal cable 53, the digital video signal can be exchanged between more distant devices.

JP2003273834

  By the way, in the transmission system shown in FIG. 1 and FIG. 2, normally, in order to save power consumption, when the system is not used, it is in a standby state in which a minimum amount of power is supplied and is activated. It operates (activates) in a normal state by a control signal.

  In the electrical signal transmission system shown in FIG. 1, for example, when the monitor device 11 (video signal input device) in a standby state is started by a start command from the source device 12 (video signal output device), the video signal output device A predetermined activation control signal is transmitted to the video signal input device via the electric cable 13 and received.

  In this case, power is always supplied to the control signal I / F unit 32 that performs the transmission process so that the video signal output device can always transmit the activation control signal to the video signal input device.

  Also in the video signal input device, power is always supplied to the control signal I / F unit 22 that performs the reception process so that the activation control signal transmitted from the video signal output device can always be received. Yes.

  In the optical transmission system for transmitting a video signal by the optical signal shown in FIG. 2, the monitor device 11 and the monitor transmission processing unit 51 in the standby state in response to the start commands from the source device 12 and the source transmission processing unit 52 (video signal output device). When starting up (video signal input device), a predetermined start control signal is transmitted from the video signal output device to the video signal input device via the optical signal cable 53 and received.

  In this case, in addition to the control signal I / F unit 32 of the source device 12, the source transmission processing unit 52 (electrical signal is transmitted as an optical signal) so that the video signal output device can always transmit the start control signal to the video signal input device. Electric power is always supplied also to an electrical / optical signal converter for converting the signal into a peripheral circuit.

  Also in the video signal input device, the monitor transmission processing unit 51 (in addition to the control signal I / F unit 22 of the monitor device 11) so that the activation control signal transmitted from the video signal output device can always be received. Electric power is always supplied to an optical / electrical signal conversion unit that converts an optical signal into an electrical signal.

  Therefore, in the transmission system of FIG. 2, since there are many circuits that supply power in the standby state to the transmission system of FIG. 1, standby power consumption is increased.

  Therefore, if a start control signal having a low frequency component is used, power consumption of the monitor transmission processing unit 51 and the source transmission processing unit 52 can be reduced. Therefore, a start control signal having a low frequency component as shown in FIG. The optical transmission system used has been developed.

  In this system, the startup control signal of the SIRCS (Serial Infrared Remote Control System) signal standard with a high frequency band corresponding to the infrared signal output from the infrared remote controller 24 is a UART (Universal Asynchronous Receiver Transmitter) signal with a low frequency band. It is converted into a standard activation control signal and transmitted to the source device 12.

  In this system, a monitor transmission processing unit 81 is provided instead of the monitor transmission processing unit 51 of FIG. 2, and a source transmission processing unit 82 is provided instead of the source transmission processing unit 52.

  The monitor device 11 is provided with a light receiving module 23 that receives the infrared signal output from the infrared remote controller 24, and the source device 12 decodes the activation control signal transmitted via the optical signal cable 53. A SIRCS decoding unit 33 is further provided.

  The monitor transmission processing unit 81 includes a control signal processing unit 64 in addition to the 0 / E conversion unit 61, the electric signal processing unit 62, and the E / 0 conversion unit 63 that constitute the monitor transmission processing unit 51 of FIG. Has been.

  The control signal processing unit 64 is an arithmetic processing unit such as a microprocessor that can operate with low power consumption. By executing a predetermined control program, for example, the source device 12 and the source transmission processing unit 82 are normally operated from a standby state. A transmission process of the activation control signal for shifting to the state is realized.

  The control program executed in the control signal processing unit 64 is functionally configured to include a SIRCS decoding unit 91 and a UART encoding unit 92.

  The SIRCS decoding unit 91 reads control data based on the SIRCS signal standard from the control signal input from the control signal I / F unit 22 of the monitor device 11, and outputs the read control data to the UART encoding unit 92.

  In response to a predetermined operation command, the infrared remote controller 24, as shown in FIG. 4, for example, an SIRCS signal standard electric signal that expresses a signal of 0 and 1 with a difference in pulse time interval of the High signal (details will be described later). 4), the light receiving module 23 receives the light, converts it into an electric signal format, and outputs it to the control signal I / F unit 22. Therefore, the SIRCS decoding unit 91 receives the signal shown in FIG. A control signal as shown in FIG.

  The UART encoding unit 92 generates a UART signal standard activation control signal corresponding to the control data output from the SIRCS decoding unit 91, and transmits it to the E / 0 conversion unit 63.

  The signal of the UART signal standard is a pulse signal at a constant interval, for example, a signal in which a high signal indicates 1 and a low signal indicates 0. Typically, as shown in FIG. Each signal represents 1 or 0 (details will be described later).

  When the activation control data is read in the SIRCS decoding unit 91, the monitor device 11 and the monitor transmission processing unit 81 shift the state from the standby state to the normal operation state.

  The monitor transmission processing unit 82 includes a control signal processing unit 74 in addition to the electric signal processing unit 71, the E / 0 conversion unit 72, and the 0 / E conversion unit 73 that constitute the monitor transmission processing unit 52 of FIG. ing.

  The control signal processing unit 74 is an arithmetic processing device such as a microprocessor that can operate with low power consumption, and realizes reception processing of a control signal transmitted from the monitor device 11 by executing a predetermined control program. .

  The activation control program executed in the control signal processing unit 74 is functionally configured to include a UART decoding unit 93 and a SIRCS encoding unit 94.

  The UART decoding unit 93 reads the control data based on the UART signal standard from the control signal in the serial signal format supplied from the 0 / E conversion unit 73 and outputs the control data to the SIRCS encoding unit 94. To do.

  The SIRCS encoding unit 94 generates a control signal of the SIRCS signal standard corresponding to the control data supplied from the UART decoding unit 93 and supplies the control signal to the SIRCS decoding unit 33 via the control signal I / F unit 32 of the source device 12. To do.

  When the SIRCS decoding unit 33 decodes the control signal supplied from the control signal I / F unit 32 and the control signal is an activation control signal, the monitor device 12 and the monitor transmission device 82 change the state from the standby state to the normal operation. Transition to the state. That is, normal power is supplied to the source device 12 and the source transmission processing unit 82.

  In this way, each device can be shifted from the standby state to the normal operation state using the activation control signal having a low frequency component, and power consumption in the standby state can be saved.

  However, since the function realized by software is realized by the sequence operation of the program, the function as the SIRCS decoding unit 91 in the control signal processing unit 64 of the monitor transmission processing unit 81 and the UART encoding unit 92 described above. The functions are executed one by one in order, and the two functions cannot be executed simultaneously. Similarly, the function as the UART decoding unit 93 and the function as the SIRCS encoding unit 94 in the control signal processing unit 74 of the source transmission processing unit 82 are also executed one by one in order, and the two functions can be executed simultaneously. Can not.

  As a result, as shown in FIG. 6, after the SIRCS signal having a predetermined length is decoded and one control data is obtained (upper part of FIG. 6), the control data is converted into a UART signal (FIG. 6). 6), it takes time for the activation control signal to be transmitted, and as shown in FIG. 7, after the UART signal is decoded and control data is obtained (upper part of FIG. 7), the control data Since it is converted into a SIRCS signal (lower part of FIG. 7), it takes time to recognize the transmitted activation control signal.

  That is, in an optical transmission system that uses optical transmission capable of long-distance transmission and shifts from a standby state to a normal operation state with a start-up control signal having a low frequency band in order to reduce power consumption in the standby state, the standby state is There was a problem that it took time to release, and the device could not be started up quickly. Further, here, the activation control signal has been described as an example. However, since a control signal such as stop or fast forward is also transmitted to the source device 12, a delay occurs as described above even in such a control signal. There was a problem that a delay occurred in obtaining the result, and the device could not be operated properly.

  The present invention has been proposed in view of such a conventional situation, and is an optical transmission system that converts an electrical signal into an optical signal and transmits the optical signal, and includes an arithmetic processing device that executes a single control program. An object of the present invention is to provide a signal processing device, a signal processing method, and a program for performing start-up control for shifting from a standby state to a normal operation state by a start-up control signal transmitted from an infrared remote controller without causing a delay time. To do.

  A signal processing device according to a first aspect of the present invention is a signal processing device that transmits and receives a predetermined transmission signal to and from another signal processing device via an optical transmission cable, wherein the transmission signal in an electric signal format is an optical signal format. Electrical / optical signal converting means for converting to optical signal, and optical / electrical signal converting means for converting the transmission signal in the optical signal format transmitted from another signal transmission apparatus connected via the optical transmission cable into an electrical signal format And control signal processing means for controlling transmission of the control signal of the first signal standard to the other signal processing device, wherein the control signal processing means is controlled from the control signal of the first signal standard. First processing means for reading information; and second processing means for converting the control information read by the first processing means into a control signal of a second signal standard and outputting the control signal. The control signal of the signal standard is Data bit on-time first level signal and data bit on-time second level signal whose length differs according to the bit value, and the control signal of the second signal standard is leveled according to the data represented. Are composed of signals of different data bit time intervals, the first processing means and the second processing means are executed by a program operating in a sequence, and the first processing means is based on the first signal standard. Bit data is extracted from the control signal of the first signal standard based on the data bit off time and the data bit on time of the control signal, and the second processing means responds to the bit data in the order of extraction. A signal having a data bit time of a different level is output as a control signal of the second signal standard.

  The first signal standard may be a SIRCS (Serial Infrared Remote Control System) signal standard, and the second signal standard may be a UART (Universal Asynchronous Receiver Transmitter) signal standard.

  The control signal may be an activation control signal for shifting another signal processing device from a standby state to a normal operation state.

  The apparatus further comprises infrared light receiving means for receiving a transmission signal of an infrared remote controller for transmitting an infrared signal of the first signal standard and converting it into an electric signal format, and the first processing means is converted by the infrared light receiving means. The control information can be read from the control signal of the first signal standard.

  The first processing means also measures the input interrupt interval time of the control signal of the first signal standard as a data bit off time or a data bit on time, and based on the measured time, Bit data is extracted from a control signal of one signal standard, and the second processing means generates a timer interrupt for each data bit on time, and each time a timer interrupt occurs, the second bit of the data bit time is generated. A signal having a level corresponding to the bit extracted by one processing means can be output.

  A signal processing method or program according to a first aspect of the present invention is a signal processing method for a signal processing device that transmits and receives a predetermined transmission signal to and from another signal processing device via an optical transmission cable, and the signal processing method or program A program for causing a computer to execute signal processing for transmitting / receiving a predetermined transmission signal to / from another signal processing device, the electrical / optical signal converting step for converting the transmission signal in an electrical signal format into an optical signal format, and the optical An optical / electrical signal conversion step for converting the transmission signal in an optical signal format transmitted from another signal transmission device connected via a transmission cable into an electrical signal format, and the control signal of the first signal standard, A control signal processing step for controlling transmission to another signal processing device, wherein the control signal processing step reads control information from a control signal of the first signal standard. A first processing step, and a second processing step for converting the control information read in the processing of the first processing step into a control signal of a second signal standard and outputting the control signal. The standard control signal is composed of a first level signal of the data bit off time and a second level signal of the data bit on time having a different length depending on the bit value. The control signal is composed of signals of data bit time intervals whose levels differ depending on the data to be represented, and the first processing step and the second processing step are executed by a program operating in a sequence, and the first processing step includes: The bit data is extracted from the control signal of the first signal standard based on the data bit off time and the data bit on time of the control signal of the first signal standard It said second processing step, the level data bit time of the signal corresponding to the bit data to the extracted order, and outputs as a control signal of the second signal standard.

  In the signal processing device, the signal processing method, and the program according to the first aspect of the present invention, the transmission signal in the electrical signal format is converted into the optical signal format, and the other signal transmission is connected via the optical transmission cable. The transmission signal in the optical signal format transmitted from the device is converted into the electrical signal format, and the transmission of the control signal of the first signal standard to the other signal processing device is controlled. Control information is read from the control signal of the signal standard, and the read control information is converted into a control signal of the second signal standard and output. The control signal of the first signal standard includes a first level signal of a data bit off time and a second level signal of a data bit on time having a different length depending on the bit. The control signal of the signal standard is composed of signals of data bit time intervals having different levels depending on the data to be represented, reading of control information from the control signal of the first signal standard, and second of the read control information. The conversion output to the control signal of the signal standard is executed by a program operating in sequence, and the first signal standard is based on the data bit off time and the data bit on time of the control signal of the first signal standard. Bit data is extracted from the control signal, and a signal having a data bit time of a level corresponding to the bit data in the extracted order is controlled by the second signal standard. It is output as the issue.

  A second signal processing device of the present invention is a signal processing device for transmitting / receiving a predetermined transmission signal to / from another signal processing device via an optical transmission cable, and converts the transmission signal in an electric signal format into an optical signal format. An electrical / optical signal conversion means for converting, and an optical / electrical signal conversion means for converting the transmission signal in an optical signal format transmitted from another signal transmission apparatus connected via the optical transmission cable into an electrical signal format; Control signal processing means for controlling reception of the control signal of the first signal standard converted into the control signal of the second signal standard in the other signal processing device, wherein the control signal processing means is the first signal standard. First processing means for reading control information from a control signal of two signal standards, and second for generating a control signal of the first signal standard corresponding to the control information read by the first processing means Processing means, and The control signal of the first signal standard is composed of a first level signal of the data bit off time and a second level signal of the data bit on time having a different length depending on the bit. The control signal of the signal standard is composed of signals of data bit time intervals having different levels depending on the data to be represented, and the first processing means and the second processing means are executed by a program operating in a sequence, The processing means reads the level of the data bit interval from the control signal of the second signal standard, and outputs bit data corresponding to the read level, and the second processing means outputs the data in the order of output. , A first level signal of the data bit off time and a second level signal of the data bit on time having a length according to the output bit, No. outputs as a control signal standards.

The first processing means generates a timer interrupt for each data bit on time, reads a control signal of the second signal standard and outputs bit data each time a timer interrupt occurs, The processing means 2 alternately generates timer interrupts for the data bit off time and the data bit on time, and each time a timer interrupt occurs, a length corresponding to the first level signal and the output bit The second level signals can be alternately output.

  The signal processing method or program according to the second aspect of the present invention is a signal processing method for transmitting / receiving a predetermined transmission signal to / from another signal processing device via an optical transmission cable, or another method via an optical transmission cable. A program for causing a computer to execute signal processing for transmitting / receiving a predetermined transmission signal to / from a signal processing device, the electrical / optical signal converting step for converting the transmission signal in an electrical signal format into an optical signal format, and the optical transmission cable An optical / electrical signal conversion step for converting the transmission signal in the optical signal format transmitted from another signal transmission device connected via the optical signal format into an electrical signal format; A control signal processing step for controlling reception of the control signal of the first signal standard converted into the control signal, wherein the control signal processing step controls the second signal standard. A first processing step of reading out control information from the signal and a second processing step of generating a control signal of the first signal standard according to the control information read out by the first processing step. The control signal of the first signal standard includes a first level signal of a data bit off time and a second level signal of a data bit on time having a different length depending on the bit. The control signal of the signal standard of 2 is composed of signals of data bit time intervals having different levels depending on the data to be represented, and the first processing step and the second processing step are executed by a program operating in a sequence, In the first processing step, the level of the data bit interval is read from the control signal of the second signal standard, and bit data corresponding to the read level is read. The second processing step outputs a first level signal of the data bit off time and a second bit of the data bit on time having a length corresponding to the output bit in the order of output. Is output as a control signal of the first signal standard.

  In the signal processing device, the signal processing method, or the program according to the second aspect of the present invention, the other signal transmission in which the transmission signal in the electric signal format is converted into the optical signal format and connected via the optical transmission cable. The transmission signal in the optical signal format transmitted from the apparatus is converted into the electrical signal format, and the control signal in the first signal standard converted into the control signal in the second signal standard is received in the other signal processing apparatus. Is controlled, control information is read from the control signal of the second signal standard, a control signal of the first signal standard is generated according to the read control information, and the first signal standard is generated. The control signal of the second signal standard is composed of a first level signal of the data bit off time and a second level signal of the data bit on time having a different length depending on the bit. Represents the data Read out the control information from the control signal of the second signal standard, and the control signal of the first signal standard corresponding to the read control information Is generated by a program operating in a sequence, the level of the data bit interval is read from the control signal of the second signal standard, bit data corresponding to the read level is output, and the output order In addition, a first level signal of the data bit off time and a second level signal of the data bit on time having a length corresponding to the output bit are used as control signals of the first signal standard. Is output.

  According to one aspect of the present invention, for example, even when an arithmetic processing device that executes a single control program is used, the signal standard of the activation control signal is converted without causing a delay time, and the signal processing device is in a standby state. To the normal operating state.

  FIG. 8 shows a configuration example of an optical transmission system to which the present invention is applied. In this transmission system, a digital video signal compliant with a transmission standard such as DVI (Digital Visual Interface) or HDMI (High Definition Multimedia Interface) is transmitted via the optical signal cable 53.

  In this system, a monitor transmission processing unit 101 is provided instead of the monitor transmission processing unit 81 of FIG. 3, and a source transmission processing unit 102 is provided instead of the source transmission processing unit 82. Other parts having the same reference numerals as those in FIG. 3 have the same functions as those in FIG.

  The monitor transmission processing unit 101 is a control signal for an electrical signal (hereinafter referred to as a SIRCS signal) having a high frequency band in accordance with the infrared signal output from the infrared remote controller 24 supplied from the monitor device 11. Is converted into an electrical signal of the UART signal standard having a low frequency band (hereinafter referred to as a UART signal) as will be described later, and the UART signal is converted into an optical signal. The data is output to the transmission processing unit 102.

  The monitor transmission processing unit 101 converts the optical signal transmitted from the source transmission processing unit 102 via the optical signal cable 53 into an electric signal, and separates it into a digital video signal and a control signal, which are supplied to the monitor device 11. To do.

  When the control signal from the infrared remote controller 24 is an activation control signal, the monitor device 11 and the monitor transmission processing unit 101 are in a standby state (for example, an operation of inputting an activation control signal and transmitting it to the source transmission processing unit 102 Power that enables normal operation (for example, receiving a digital video signal and displaying an image corresponding to the signal). The state is shifted to the state of being.

  The source transmission processing unit 102 converts the optical signal (control signal of the UART signal) transmitted from the monitor transmission processing unit 101 via the optical signal cable 53 into an electrical signal, and the UART signal obtained as a result is converted to As described later, it is converted into a SIRCS signal and supplied to the source device 12.

  The SIRCS decoding unit 33 of the source device 12 decodes the control signal of the SIRCS signal supplied from the source transmission processing unit 102. The source device 12 executes a predetermined process according to the decoding result.

  The source transmission processing unit 102 multiplexes the digital video signal output from the source device 12 and a control signal such as DDC defined by DVI or HDMI, and converts the multiplexed signal into an optical signal. Then, the data is transmitted to the monitor transmission processing unit 101 via the optical signal cable 53.

  When the control signal transmitted from the monitor transmission processing unit 101 is an activation control signal, the source device 12 and the source transmission processing unit 102 are supplied with power that enables an operation of receiving the activation control signal (for example, an operation for receiving the activation control signal). In the normal operation state (for example, a state in which electric power enabling transmission of the digital video signal is supplied).

  Next, detailed configurations and operations of the monitor transmission processing unit 101 and the source transmission processing unit 102 will be described.

  First, the monitor transmission processing unit 101 will be described.

  As shown in FIG. 9, the monitor transmission processing unit 101 is provided with a control signal processing unit 111 instead of the control signal processing unit 64 of the monitor transmission processing unit 81 of FIG. Other parts are the same as those of the monitor transmission processing unit 81 of FIG.

  The control signal processing unit 111 is an arithmetic processing unit such as a microprocessor that can operate with low power consumption. By executing a predetermined control program, for example, the source device 12 and the source transmission processing unit 102 are normally operated from a standby state. A control signal such as an activation control signal for shifting to the state is transmitted to the source transmission processing unit 102.

  FIG. 9 shows a functional configuration example when the control program executes the control signal transmission process.

  The CR clock oscillating unit 131 generates a predetermined clock signal by an oscillator composed of a CR oscillating circuit and outputs it to the clock dividing unit 132.

  The clock frequency division unit 132 generates a frequency division clock according to the clock signal oscillated by the CR clock oscillation unit 131 and outputs it to the timer 133 and the timer 134.

  The timer 133 up-counts the clock from the clock division unit 132 and outputs the count result to the SIRCS decoding unit 135.

  The timer 134 counts down the predetermined value that has been set, and outputs an interrupt signal to the UART encoder 137 when the count value reaches zero.

  The SIRCS decoding unit 135 is connected to the microcomputer I / O assigned to the input of the SIRCS signal (control signal) from the control signal I / F unit 22 of the monitor device 11 of the control signal processing unit 111. The SIRCS signal from the control signal I / F unit 22 is decoded.

  As shown in FIG. 4, the SIRCS signal constituting one control data is composed of, for example, 12 pulses of 12 bits following a high signal of a guide pulse time Tg having a predetermined length.

  This pulse includes, for example, a low signal with a data bit off time Toff shorter than the time Tg and a high signal with a data bit on time Ton whose length varies depending on the bit represented by the pulse. The data bit on time Ton for the “1” bit is shorter than the guide pulse time Tg but longer than the data bit off time Toff, and the data bit on time Ton for the “0” bit is the data The time is the same as the bit-off time Toff.

  That is, the SIRCS decoding unit 135 controls the timer 133 when the rising or falling edge of the SIRCS signal is input and an input interrupt is generated, so that the time of the input interrupt occurrence interval is set to the data guide pulse time Tg and the data bit off time Toff. Alternatively, the data bit on time Ton is measured, and bit data is extracted from the SIRCS signal based on the measured time.

  The SIRCS decoding unit 135 outputs the extracted bit data to the FIFO 136.

  The FIFO 136 stores the 1-bit data output from the SIRCS decoding unit 135 and outputs the 1-bit data to the UART encoding unit 137.

  The UART encoding unit 137 converts the control data decoded by the SIRCS decoding unit 135 stored in the FIFO 136 into a UART signal and outputs it to the E / O conversion unit 63.

  As shown in FIG. 5, the UART signal constituting one control data is a predetermined data bit between a high signal of a predetermined time Tes as a start signal and an end signal and between the start signal and the end signal. Twelve bit signals (D1 to D12 in the figure) that are High or Low depending on the bit represented at time Tu (in this example, the same time as time Tes) are arranged.

  In other words, the UART encoding unit 137 sets the time corresponding to the data bit time Tu in the timer 134 to cause the timer 134 to count down, and generates a timer interrupt every data bit time Tu, and the data read from the FIFO 136 every time the timer interrupt occurs. The microcomputer I / O line assigned to the output to the E / O conversion unit 63 of the control signal processing unit 111 is set to High or Low according to the value of the signal, and the UART signal is output to the E / O conversion unit 63 To do.

  Next, the activation control signal transmission process realized by the control signal processing unit 111 executing the control program will be described with reference to the flowchart of FIG.

  In step S1, for example, the monitor device 11 and the monitor transmission processing unit 101 are powered on, and the control signal I / F unit 22 of the monitor device 11 and the E / O conversion unit 63 of the monitor transmission processing unit 101 and the control signal processing are processed. When power in the standby state is supplied to the unit 111, a control program is started in the control signal processing unit 111, and each unit of the control signal processing unit 111 is initialized in step S2.

  Specifically, the timer 133 is initialized to 0 and set to the up counter. As a result, the timer 133 starts counting up from the clock value 0 from the clock dividing unit 132.

  The timer 134 is initialized to 0 and set to a down counter. At this time, the counter 134 is operable, but since the count value is initialized to 0, down-counting has not yet started.

  Further, a variable CS used by the SIRCS decoding unit 135 described later and a variable CU used by the UART encoding unit 137 are each initialized to a value 0.

  In step S3, the microcomputer I / O input pin assigned to the input of the SIRCS signal (control signal) from the control signal I / F unit 22 of the monitor device 11 in the control signal processing unit 111 is set to wait for an interrupt. .

  In step S4, the SIRCS decoding unit 135 and the UART encoding unit 137 operate in parallel to start processing for transmitting the activation control signal to the source transmission processing unit 102. Details of this processing will be described later.

  In step S5, the control signal processing unit 111 determines whether or not transmission of the activation control signal to the source transmission processing unit 102 has been completed. If it is determined that transmission has not yet been completed, the control signal processing unit 111 returns to step S4. That is, the processes in steps S4 and S5 are repeatedly performed until the transmission of the activation control signal to the source transmission processing unit 102 is completed.

  Next, the activation control signal transmission process in step S4 will be described. In this process, the SIRCS decoding process of the SIRCS decoding unit 135 and the UART encoding process of the UART encoding unit 137 are executed in parallel. Separately described.

  Here, the outline of the SIRCS decoding process of the SIRCS decoding unit 135 will be described with reference to the flowchart of FIG. 11, and then a specific example will be described based on FIG.

  In step S11, the SIRCS decoding unit 135 determines whether an input interrupt has occurred due to the input of the SIRCS signal (startup control signal) from the control signal I / F unit 22 of the monitor device 11, and the input interrupt has occurred. If it is determined, the process proceeds to step S12.

  In step S12, the SIRCS decoding unit 135 determines whether or not the variable CS has a value of 0. If it is determined that the variable CS has a value of 0, the process proceeds to step S13.

  In step S13, the SIRCS decoding unit 135 obtains the count value (that is, the measurement time) of the timer 133 when the input interrupt occurs, and determines whether or not it matches the guide pulse time Tg (FIG. 4) of the SIRCS signal. If it is determined that they match, the process proceeds to step S14 and the variable CS is set to a value of 1.

  Next, in step S <b> 15, the SIRCS decoding unit 135 sets a predetermined time in the timer 134. Although details will be described later, the processing of the UART encoding unit 137 is started by the timer interrupt in the timer 134 according to the time set here, so the time set in the timer 134 here is the time of the UART encoding unit 137. This delay time is a delay time until the processing is started. This delay time is enough for the data of the FIFO 136 not to be insufficient even when the processing of the UART encoding unit 137 is started and the data is read from the FIFO 136. This is the time required for accumulation in the FIFO 136 by this SIRCS decoding process.

  When the delay time is set in the timer 134, the timer 134 starts down-counting.

  When it is determined in step S12 that the variable CS is not 0, that is, when the variable CS is set to 1 in the process of step S14, or when the variable CS is incremented by 1 in step S18 described later. In step S16, it is determined whether or not the variable CS is an even value. If it is determined that the variable CS is not an even value, the process proceeds to step S17.

  In step S17, the SIRCS decoding unit 135 determines whether or not the measurement time of the timer 133 when the input interrupt occurs matches the data bit off time Toff (FIG. 4) of the SIRCS signal, and determines that they match. In step S18, the variable CS is incremented by one.

  If it is determined in step S17 that the measurement time of the timer 133 does not coincide with the data bit off time Toff of the SIRCS signal, the process proceeds to step S19, and the SIRCS decoding unit 135 initializes the variable CS to the value 0.

  If it is determined in step S16 that the variable CS is an even value, the process proceeds to step S20, and the SIRCS decoding unit 135 stores the bit of “1” in the SIRCS signal for the measurement time of the timer 133 when the input interrupt occurs. It is determined whether or not the bit on time Ton (FIG. 4) coincides. If it coincides, the process proceeds to step S 21, and the bit “1” is output to the FIFO 136.

  If it is determined in step S20 that the measurement time of the timer 133 does not match the data bit on time Ton of the “1” bit of the SIRCS signal, that is, the data bit on time Ton of the “0” bit matches, In step S 22, the SIRCS decoding unit 135 outputs a “0” bit to the FIFO 136.

  After a predetermined bit is output to the FIFO 136 in step S21 or step S22, in step S23, the SIRCS decoding unit 135 determines whether or not the variable CS is a value 24, and determines that it is not a value 24. In step S18, the variable CS is incremented by one.

  If it is determined in step S23 that the variable CS is the value 24, the process proceeds to step S19, and the variable CS is initialized to the value 0.

  If it is determined in step S13 that the measurement time of the timer 133 does not coincide with the guide pulse time Tg, after the processing in step S15, step S18, or step S19, the process proceeds to step S24, and the SIRCS decoding unit 135 The measurement time of 133 is reset to the value 0.

  If it is determined in step S11 that no input interrupt has occurred, or if the measurement time of the timer 133 is reset to 0 in step S24, the process ends, and the process proceeds to step S5 in FIG. When the determination is made, the process returns to step S11 again, and the subsequent processing is similarly performed.

  Next, the SIRCS decoding process will be described again by taking the case of decoding the SIRCS signal shown in FIG. 12A as an example.

  When the rising edge of the guide pulse of the SIRCS signal shown in FIG. 12A is input to the control signal processing unit 111, an input interrupt is generated as shown in FIG. 12C.

  The rising edge up to the broken line corresponding to “SIRCS Decode” in FIG. 12C indicates the timing of the input interrupt generated in the SIRCS decoding unit 135. The rising edge up to the broken line corresponding to “UART Encode” in FIG. 12C indicates the timing of the input interrupt generated in the UART encoding unit 137.

  When an input interrupt at the rising edge of the guide pulse of the SIRCS signal shown in FIG. 12A occurs as shown in FIG. 12C (step S11), the measurement time of the timer 133 is reset to the value 0 through steps S12 and S13 ( Step S24), measurement of the guide pulse time Tg is started.

  Thereafter, when an input interrupt at the falling edge of the guide pulse shown in FIG. 12A occurs as shown in FIG. 12C (step S11), the variable CS at this time has a value 0 as shown in FIG. 13 (step S12). ), It is determined whether or not the measurement time T0 of the timer 133 shown in FIG. 13 coincides with the guide pulse time Tg (step S13).

  In this case, since the time T0 coincides with the guide pulse time Tg, the variable CS is set to the value 1 (odd value) (step S14), the delay time is set in the timer 134 (step S15), and the measurement of the timer 133 is performed. The time is reset to the value 0 (step S24), and the measurement of the data bit off time Toff is started this time.

  Thereafter, when the first rising input interrupt after the guide pulse shown in FIG. 12A occurs as shown in FIG. 12C (step S11), the variable CS at this time has a value 1 (odd number) as shown in FIG. Value (step S12, step S16), it is determined whether or not the measurement time T1 of the timer 133 matches the data bit off time Toff (step S17).

  In this case, since the time T1 coincides with the data bit off time Toff, the variable CS is set to the value 2 (step S18), and the measurement time of the timer 133 is reset to the value 0 (step S24). Measurement of time Ton is started.

  According to the SIRCS signal standard, as shown in FIG. 4, since a low signal of the data bit off time Toff exists immediately after the guide pulse, the data after the guide pulse time Tg is measured by the timer 133 It is confirmed whether or not the bit-off time Toff has been measured. If it can be confirmed that the bit-off time Toff has been measured, the signal from which the guide pulse time Tg2 has been measured can be used as the guide pulse.

  That is, when it is determined here that the measurement time of the timer 133 does not coincide with the data bit off time Toff (step S17), the signal for which the guide pulse time Tg has been measured first is not a guide pulse, so the variable CS has the value 0. (Step S19), the measurement time of the timer 133 is reset to 0 (step S24), that is, the process returns to the initial state, and the processing from step S11 is performed again.

  Returning to FIG. 12, when the falling input interrupt shown in FIG. 12A occurs as shown in FIG. 12C (step S11), the variable CS at this time has a value 2 (even value) as shown in FIG. (Step S12, Step S16), the measurement time T2 of the timer 133 is assumed to be the data bit on time Ton, and the data bit on time on of the bit whose time T2 is “1” or “0” is either It is determined whether they match. In this case, since the time T2 coincides with the data bit on time on of the “0” bit (step S20), the “0” bit is output (step S21).

  When the bit data is output in this way, since the variable CS is 2 and not 24 (step S23), the variable CS is incremented to 3 (odd value) (step S18), and the timer 133 measures. The time is reset to 0 (step S24), and measurement of the data bit off time Toff is started.

  According to the SIRCS signal standard, the data bit off time Toff and the data bit on time Ton exist alternately, and the length and the bit value of the data bit on time Ton correspond to each other. Using the incremented variable CS, it is determined whether the measurement time of the timer 133 is the data bit off time Toff or the data bit on time Ton (step S16, step S17, step S20), and the data bit on time Ton. (When the variable CS is an even number), bits can be extracted according to the length.

  Since the variable CS is incremented by 2 to extract 1-bit data, the variable CS becomes a value 24 when one control data, that is, 12-bit data is extracted. Therefore, when it is determined in step S23 that the variable CS is the value 24, the variable CS is initialized to the value 0 in order to decode the next control data (step S24), and the measurement time of the timer 133 is a value. It is reset to 0 (step S24).

  In this way, bit data is extracted from each pulse based on the guide pulse time Tg, the data bit off time Toff, and the data bit on time Ton.

  Next, the outline of the UART encoding process of the UART encoding unit 137 in the case of executing the control signal transmission process in step S4 will be described with reference to the flowchart of FIG. 14, and then a specific example based on FIG. Will be explained.

  In step S31, the UART encoding unit 137 determines whether or not a timer interrupt has occurred from the timer 134. If it is determined that a timer interrupt has occurred, the UART encoding unit 137 proceeds to step S32 and reads 1-bit data from the FIFO 136. It is determined whether or not the read bit is “1”, or whether or not the variable CU is the value 0 or the value 13, and the read bit is “1” or the variable CU is the value 1 or the value If it is determined that the number is 13, the process proceeds to step S33.

  In step S33, the UART encoding unit 137 sets the microcomputer I / O line, which is the output of the UART signal, to High (that is, sets the signal level of the UART signal to High).

  If it is determined in step S32 that one bit read from the FIFO 136 is “0” or the variable CU is neither the value 1 nor the value 13, the UART encoding unit 137 proceeds to step S34 to output the UART signal. The microcomputer I / O line is set to Low (that is, the signal level of the UART signal is set to Low).

  When the signal level of the UART signal is set to High or Low in Step S33 or Step S34, the UART encoding unit 137 sets the data bit time Tu (FIG. 5) of the UART signal to the timer 134 in Step S35. Thereby, the timer 134 starts down-counting from the set data bit time Tu.

  After that, in step S36, the UART encoding unit 137 increments the variable CU by 1. In step S37, it is determined whether or not the variable CU is the value 14, and if it is determined that the variable CU is the value 14, In S38, the variable UC is initialized to 0.

  When it is determined at step S31 that no input interrupt has occurred, when it is determined at step S37 that the variable CU is not the value 14, or when the variable CU is initialized to the value 0 at step S38, The process is terminated, and the process proceeds to step S5 in FIG. 10. When No is determined there, the process returns to step S31 again, and the subsequent processes are similarly performed.

  Next, the UART encoding process will be described again by taking as an example the case where the bit data extracted from the SIRCS signal in FIG. 12A is UART encoded.

  As shown in FIG. 12C, when the timer 134 generates a timer interrupt due to the delay time set in step S15 of FIG. 11 (step S31), the variable CU has a value 0 as shown in FIG. In step S32), the microcomputer I / O line, which is the output of the UART signal, is set to High (step S33). As a result, as shown in FIG. 12B, output of the start signal is started.

  The signal setting in step S33 or step S34 is performed every time a timer interrupt occurs in the timer 134. Therefore, here, the time until the next signal of the start signal is set is the time Tes of the UART signal (in this case, the data bit time Tu), and the high signal as the start signal is only the data bit time Tu. The data bit time Tu is set in the timer 134 so as to be output (step S35). Then, the variable CU is incremented to a value 1 as shown in FIG. 15 (step S36).

  As shown in FIG. 12B, when the start signal is output with the data bit time Tu and the timer interrupt is generated with the data bit time Tu in the timer 134 as shown in FIG. 12C (step S31), the variable CU has the value 1 Therefore (step S32), this time, the microcomputer I / O line is set to low according to the bit read from the FIFO 136, that is, the "0" bit extracted from the SIRCS signal (step S34). As a result, as shown in FIG. 12B, output of the signal “0” is started.

  The data bit time Tu is set in the timer 134 so that a signal of “0” is output for the data bit time Tu (step S35), and the variable CU is incremented to a value 2 as shown in FIG.

  When the bit data extracted from the SIRCS signal in this way is sequentially encoded and 12 bits are encoded, and the variable CU becomes the value 13 as shown in FIG. 15 (step S32), the UART In order to output the signal end signal, the microcomputer I / O line is set to High (step S33).

  Then, the data bit time Tu is set in the timer 134 so that the high signal as the end signal is output for the data bit time Tu (step S35), and when the variable CU is incremented to the value 14 (step S36), The variable CU is initialized to the value 0 (steps S37 and S38), and the bits for the next control data are UART encoded.

  The SIRCS decoding process and the UART encoding process are performed as described above. After the delay time set in the timer 134 has elapsed as shown in FIG. 12B, the SIRCS decoding process shown in FIG. 12A and the UART encoding shown in FIG. 12B are performed. Since the processes are executed in parallel, the activation control signal can be transmitted more quickly than in the conventional case (FIG. 6).

  Next, the source transmission processing unit 102 (FIG. 8) will be described.

  As shown in FIG. 16, the source transmission processing unit 102 is provided with a control signal processing unit 121 instead of the control signal processing unit 74 of FIG.

  The control signal processing unit 121 is an arithmetic processing unit such as a microprocessor that can operate with low power consumption. The control signal processing unit 121 executes a predetermined control program to receive a control signal transmitted from the monitor transmission processing unit 101. Realize.

  FIG. 16 shows a functional configuration example when the control program executes control signal processing.

  The CR clock oscillating unit 151 generates a predetermined clock signal by an oscillator configured by a CR oscillation circuit, and outputs the generated clock signal to the clock dividing unit 152.

  The clock frequency dividing unit 152 generates a frequency divided clock according to the clock signal oscillated by the CR clock oscillating unit 151, and outputs it to the timer 153 and the timer 154.

  The timer 153 counts down the predetermined value set by the UART decoding unit 155 and outputs an interrupt signal to the UART decoding unit 155 when the count value becomes zero.

  The timer 154 counts down a predetermined value set by the SIRCS encoding unit 157, and outputs an interrupt signal to the SIRCS encoding unit 157 when the count value becomes zero.

  The UART decoding unit 155 decodes the UART signal from the O / E conversion unit 73 input to the microcomputer I / O assigned to the input of the UART signal from the O / E conversion unit 73 of the control signal processing unit 121, The resulting bit is output to the FIFO 156.

  The FIFO 156 stores the 1-bit data output from the UART decoding unit 155 and outputs the 1-bit data to the SIRCS encoding unit 157.

  The SIRCS encoding unit 157 converts the control data decoded by the UART decoding unit 155 stored in the FIFO 156 into a SIRCS signal and outputs the SIRCS signal to the control signal I / F unit 32 of the source device 12.

  Next, an activation control signal reception process realized by the control signal processing unit 121 executing a control program will be described with reference to the flowchart of FIG.

  In step S71, for example, the source device 12 and the source transmission processing unit 102 are powered on, the control signal I / F unit 32 and the SIRCS decoding unit 33 of the source device 12, and the O / E conversion unit of the source transmission processing unit 102 73 and the control signal processing unit 121 are supplied with power in a standby state, the control signal processing unit 121 starts a control program, and each unit of the control signal processing unit 121 is initialized in step S72.

  Specifically, both timer 153 and timer 154 are set in the down counter, and the count value is initialized to 0.

  Further, a variable CU used by a UART decoding unit 155 (to be described later) and a variable CS used by a SIRCS encoding unit 157 are each initialized to a value 0.

  In step S73, the microcomputer I / O input pin assigned to the input of the UART signal (control signal) from the O / E device 73 in the control signal processing unit 121 is set to wait for an interrupt.

  In step S74, the UART decoding unit 155 and the SIRCS encoding unit 157 operate in parallel to execute the activation control signal reception process. Details of this processing will be described later.

  In step S75, the control signal processing unit 121 determines whether or not reception of the activation control signal has been completed. If it is determined that reception has not yet been completed, the control signal processing unit 121 returns to step S74. That is, the process of step S74 is repeated until reception of the activation control signal is completed.

  Next, the details of the activation control signal reception processing in step S74 will be described. This processing is performed in parallel with the UART decoding processing of the UART decoding unit 155 and the SIRCS encoding processing of the SIRCS encoding unit 157. Each will be described separately.

  Here, the outline of the UART decoding processing of the UART decoding unit 155 will be described with reference to the flowchart of FIG. 18, and then a specific example will be described based on FIG.

  In step S81, the UART decoding unit 155 determines whether or not an input interrupt for the UART signal from the O / E conversion unit 73 has occurred. If it is determined that an input interrupt has occurred, the process proceeds to step S82.

  In step S82, the UART decoding unit 155 determines whether or not the variable CU has a value of 0. If the variable CU determines to have a value of 0, in step S83, the timer 153 receives the data bit time Tu (see FIG. Set the time 1.5 times longer than 5).

  In step S84, the UART decoding unit 155 sets a delay time in the timer 154.

  If it is determined in step S81 that an input interrupt has not occurred, the process proceeds to step S85, in which the UART decoding unit 155 determines whether or not a timer interrupt from the timer 153 has occurred, and the timer interrupt has occurred. If it is determined, the process proceeds to step S86, where the UART signal input microcomputer I / O line is checked to determine whether or not the voltage is high. If it is determined that the voltage is high, the process proceeds to step S87 and "1" is set. The bit is output to the FIFO 156.

  If it is determined in step S86 that the UART signal input microcomputer I / O line is not at the high voltage level, that is, if the voltage is at the low level, the process proceeds to step S88, and the UART decoding unit 155 transfers the bit “0” to the FIFO 156. Output.

  When a bit is output to the FIFO 156 in step S87 or step S88, the process proceeds to step S89, and the UART decoding unit 155 sets the data bit time Tu in the timer 153.

  When the delay time is set in the timer 154 in step S84, or when the data bit time Tu is set in the timer 153 in step S89, the UART decoding unit 155 increments the variable CU by 1 in step S90, In step S91, it is determined whether or not the variable UC is 13. If it is determined that the value is 13, the process proceeds to step S92, and the variable UC is initialized to 0.

  When it is determined in step S82 that the variable CU is not 0, when it is determined in step S85 that a timer interrupt has not occurred, in step S91, when it is determined that the variable CU is not 13 or When the variable CU is initialized to the value 0 in step S92, the process ends thereafter, and the process proceeds to step S75 in FIG. 17. When NO is determined there, the process returns to step S81, and the subsequent processes are performed. The same is done.

  Next, the UART decoding process will be described again using the case of decoding the UART signal shown in FIG. 19B as an example.

  When the start signal of the UART signal shown in FIG. 19B is input to the control signal processing unit 121, an input interrupt occurs as shown in FIG. 19C.

  The rising edge up to the broken line corresponding to “UART Decode” in FIG. 19C indicates the timing of the interrupt generated in the UART decoding unit 155. The rising edge up to the broken line corresponding to “SIRCS Encode” in FIG. 19C indicates the timing of the interrupt generated in the SIRCS encoding unit 157.

  When the input interrupt of the start signal of the UART signal shown in FIG. 19B occurs as shown in FIG. 19C (step S81), the variable CU has a value of 0 (step S82), so that the timer 153 has the data bit time Tu. The time 1.5 times is set (step S83), the delay time is set in the timer 154 (step S84), and the variable CU is set to the value 1 as shown in FIG. 20 (step S90).

  Thereafter, after 1.5 times the data bit time Tu has elapsed, when a timer interrupt occurs as shown in FIG. 19C (steps S81 and S85), the UART signal at that time is Low as shown in FIG. 19B. Therefore, a bit of “0” is output to the FIFO 156 (steps S86 and S88), the data bit time Tu is set to the timer 153 (step S89), and the variable CU is set to the value 2 as shown in FIG. (Step S90).

  After that, after the data bit time Tu elapses, when a timer interrupt occurs as shown in FIG. 19C (step S81, step S85), the UART signal at that time is High as shown in FIG. The bit is output to the FIFO 156 (steps S86 and S87), the data bit time Tu is set again in the timer 153 (step S89), and the variable CU is set to the value 3 as shown in FIG. 20 (step S90). .

  At the time of the input interruption by the start signal of the UART signal, the timer 153 is set to 1.5 times the data bit time Tu (step S83), and thereafter, the data bit time Tu (step S89) is set. Therefore, when half of the bit signal of the UART signal is input in terms of time, a timer interrupt is generated in the timer 153, and the level of the bit signal of the UART signal at that time is bit-converted.

  In this way, when 12 consecutive bits are read from the UART signal and the variable CU becomes the value 13 as shown in FIG. 20 (step S90), the variable CU is initialized to the value 0. (Step S91, Step S92), bit extraction from the UART signal corresponding to the next control data is performed.

  Next, the SIRCS encoding process of the SIRCS encoding unit 157 when executing the activation control signal reception process in step S74 will be described. First, the outline will be described with reference to the flowchart of FIG. 21, and then based on FIG. A specific example will be described.

  In step S101, the SIRCS encoding unit 157 determines whether or not a timer interrupt has occurred in the timer 154. If it is determined that a timer interrupt has occurred, the process proceeds to step S102, and whether or not the variable CS is 0. In step S103, the guide pulse time Tg is set in the timer 154, and in step S104, the microcomputer I / O line that is the output of the SIRCS signal is set to high.

  When it is determined in step S102 that the variable CS is not 0, in step S105, the SIRCS encoding unit 157 determines whether or not the variable CS is an even value, and determines that the variable CS is not an even value. In step S106, the data bit off time Toff (FIG. 4) in the SIRCS signal is set in the timer 154, and in step S107, the microcomputer I / O line that is the output of the SIRCS signal is set to low.

  If it is determined in step S105 that the variable CS is an even value, the process proceeds to step S108, where the SIRCS encoding unit 157 reads one bit from the FIFO 156, and in step S109, whether or not the bit is “1”. If it is determined that the bit is “1”, the process proceeds to step S110, and the data bit on time Ton (FIG. 4) of the bit “1” is set in the timer 154.

  If it is determined in step S109 that the bit is not “1”, that is, if the bit is “0”, the process proceeds to step S111, and the SIRCS encoding unit 157 sends the data bit of “0” to the timer 154. Set the on time Ton.

  When the data bit on time Ton is set in the timer 154 in step S110 or step S111, the process proceeds to step S104.

  When the microcomputer I / O line is set to High or Low in step S104 or step S107, the process proceeds to step S112, and the SIRCS encoding unit 157 increments the variable CS by 1. In step S113, the variable CS is set to the value. It is determined whether or not the value is 26. If it is determined that the value is 26, the process proceeds to step S114, and the variable CS is initialized to 0.

  When it is determined in step S101 that no timer interrupt has occurred, when it is determined in step S113 that the variable CS is not 26, or when the variable CS is initialized to 0 in step S114 The process ends, and the process proceeds to step S75 in FIG. 17, and if NO is determined there, the process returns to step S101, and the subsequent processes are similarly performed.

  Next, the SIRCS encoding process will be described again by taking as an example the case where the bit data extracted from the UART signal shown in FIG. 19B is encoded into the SIRCS signal.

  First, since a timer interrupt is generated by the delay time set in the timer 154 (step S84 in FIG. 18), when the timer interrupt is generated as shown in FIG. 19C (step S101), the variable CS is as shown in FIG. Since the value is 0 (step S102), the guide pulse time Tg is set in the timer 154 (step S103), and the microcomputer I / O line is set to High (step S104). As a result, as shown in FIG. 19A, the output of the guide pulse is started.

  The variable CS is set to the value 1 (step S112).

  Thereafter, when a timer interruption by the guide pulse time Tg occurs as shown in FIG. 19C (step S101), the variable CS has a value 1 as shown in FIG. 22 (step S102, step S105), so the timer 154 Is set to the data bit off time Toff (step S106), and the microcomputer I / O line is set to low (step S107). As a result, as shown in FIG. 19A, a low signal of the data bit off time Toff is output.

  The variable CS is set to a value 2 (step S112).

  Thereafter, when a timer interrupt due to the data bit off time Toff occurs as shown in FIG. 19C (step S101), the variable CS has a value of 2 as shown in FIG. 22 (step S102, step S105). 1-bit data is read from (step S108), and since it is “0”, the data bit on time Ton of data “0” is set in the timer 154 (step S109, step S111), and the microcomputer I / O The O line is set to High (step S104). As a result, as shown in FIG. 19A, the output of the high signal of the data bit on time Ton of the bit “0” is started.

  At this time, the variable CS is set to a value 3 (step S12).

  In this way, SIRCS encoding processing is performed.

  As described above, the UART decoding process and the SIRCS encoding process are performed. After the delay time set in the timer 154 has elapsed as shown in FIG. 19A, the UART decoding process shown in FIG. 19B and the SIRCS shown in FIG. 19A are performed. Since the encoding process is executed in parallel, the activation control signal can be received more quickly than in the conventional case (FIG. 7).

  In order to eliminate the delay caused by the collision between the SIRCS decoding process and the UART encoding process or the program interrupt process in the UART decoding process and the SIRCS encoding process in the execution of the control program in the control signal processing unit 111 and the control signal processing unit 121 described above. In the case of a collision, the decoding process can be prioritized. As hardware, a register for storing the timer value at the time of interruption or a register for storing the low or high electric signal of the microcomputer I / O line at the time of interruption as 0 or 1 can be provided.

  In the above description, transmission / reception of an activation control signal has been described as an example. However, the present invention can also be applied to transmission / reception of other control signals (for example, control signals such as stop and fast-forward).

It is the schematic diagram which showed the structure of the conventional transmission system. It is the schematic diagram which showed the structure of the conventional optical transmission system. It is the schematic diagram which showed the other structure of the conventional optical transmission system. It is a waveform diagram showing an example of a signal waveform of the SIRCS signal standard. It is a waveform diagram showing an example of a signal waveform of the UART signal standard. It is a figure explaining the process of the control signal process part 64 of FIG. It is a figure explaining the process of the control signal process part 74 of FIG. It is the schematic diagram which showed the structure of the optical transmission system of this invention. It is a block diagram which shows the structural example of the monitor transmission process part 101 of FIG. It is a flowchart explaining the process of the control signal process part 111 of FIG. 10 is a flowchart for explaining processing of a SIRCS decoding unit 135 in FIG. 9. It is a figure which shows the specific example of a process of the control signal process part 111 of FIG. It is a figure which shows the specific example of a process of the SIRCS decoding part 135 of FIG. It is a flowchart explaining the process of the UART encoding part 137 of FIG. It is a figure which shows the specific example of a process of the UART encoding part 137 of FIG. It is a block diagram which shows the structural example of the source transmission process part 102 of FIG. It is a flowchart explaining the process of the control signal process part 121 of FIG. 17 is a flowchart for describing processing of a UART decoding unit 155 in FIG. 16. It is a figure which shows the specific example of a process of the control signal process part 121 of FIG. It is a figure which shows the specific example of a process of the UART decoding part 155 of FIG. 17 is a flowchart for describing processing of a SIRCS encoding unit 157 in FIG. 16. It is a figure which shows the specific example of a process of the SIRCS encoding part 157 of FIG.

Explanation of symbols

  101 monitor transmission processing unit, 102 source transmission processing unit, 111 control signal processing unit, 121 control signal processing unit, 131 CR clock transmission unit, 132 clock frequency division unit, 133 timer, 134 timer, 135 SIRCS decoding unit, 136 FIFO, 137 UART encoding unit, 151 CR clock transmission unit, 152 clock division unit, 153 timer, 154 timer, 155 UART decoding unit, 156 FIFO, 137 SIRCS encoding unit

Claims (13)

A signal processing device that transmits and receives a predetermined transmission signal with another signal processing device via an optical transmission cable,
Electrical / optical signal conversion means for converting the transmission signal in electrical signal format into optical signal format;
An optical / electrical signal conversion means for converting the transmission signal in the optical signal format transmitted from another signal transmission device connected via the optical transmission cable into an electrical signal format;
Control signal processing means for controlling transmission of the control signal of the first signal standard to the other signal processing device,
The control signal processing means is
First processing means for reading control information from a control signal of the first signal standard;
Second control means for converting the control information read by the first processing means into a control signal of a second signal standard and outputting the control signal;
The control signal of the first signal standard is composed of a first level signal of a data bit off time and a second level signal of a data bit on time having a different length depending on the bit value,
The control signal of the second signal standard is composed of signals of data bit time intervals having different levels depending on data to be expressed,
The first processing means and the second processing means are executed by a program operating in a sequence,
The first processing means extracts bit data from the control signal of the first signal standard based on the data bit off time and the data bit on time of the control signal of the first signal standard,
The second processing means outputs a signal having a data bit time level corresponding to the bit data in the extracted order as a control signal of the second signal standard. The first signal standard is a SIRCS (Serial Infrared Remote Control System) signal standard,
The signal processing apparatus according to claim 1, wherein the second signal standard is a UART (Universal Asynchronous Receiver Transmitter) signal standard. The signal processing apparatus according to claim 1, wherein the control signal is an activation control signal for shifting the other signal processing apparatus from a standby state to a normal operation state. Infrared light receiving means for receiving a transmission signal of an infrared remote controller for transmitting an infrared signal of the first signal standard and converting it into an electric signal format,
The signal processing apparatus according to claim 1, wherein the first processing unit reads control information from a control signal of the first signal standard converted by the infrared light receiving unit. The first processing means measures an input interrupt interval time of the control signal of the first signal standard as a data bit off time or a data bit on time, and based on the measured time, the first processing unit Bit data is extracted from the control signal of the signal standard of
The second processing means generates a timer interrupt for each data bit on time, and each time a timer interrupt occurs, the second processing means has a level corresponding to the bit extracted by the first processing means for the data bit time. The signal processing device according to claim 1, which outputs a signal. A signal processing method of a signal processing device that transmits and receives a predetermined transmission signal to and from another signal processing device via an optical transmission cable,
An electrical / optical signal conversion step of converting the transmission signal in electrical signal format into optical signal format;
An optical / electrical signal converting step for converting the transmission signal in an optical signal format transmitted from another signal transmission device connected via the optical transmission cable into an electrical signal format;
A control signal processing step for controlling transmission of the control signal of the first signal standard to the other signal processing device,
The control signal processing step includes
A first processing step of reading control information from a control signal of the first signal standard;
A second processing step of converting the control information read in the processing of the first processing step into a control signal of a second signal standard and outputting the control signal;
The control signal of the first signal standard is composed of a first level signal of a data bit off time and a second level signal of a data bit on time having a different length depending on the bit value,
The control signal of the second signal standard is composed of signals of data bit time intervals having different levels depending on data to be expressed,
The first processing step and the second processing step are executed by a program operating in a sequence,
The first processing step extracts bit data from the control signal of the first signal standard based on the data bit off time and the data bit on time of the control signal of the first signal standard,
The second processing step outputs a signal having a data bit time level corresponding to the bit data in the extracted order as a control signal of the second signal standard. A program for causing a computer to execute signal processing for transmitting / receiving a predetermined transmission signal to / from another signal processing device via an optical transmission cable,
An electrical / optical signal conversion step of converting the transmission signal in electrical signal format into optical signal format;
An optical / electrical signal converting step for converting the transmission signal in an optical signal format transmitted from another signal transmission device connected via the optical transmission cable into an electrical signal format;
A control signal processing step for controlling transmission of the control signal of the first signal standard to the other signal processing device,
The control signal processing step includes
A first processing step of reading control information from a control signal of the first signal standard;
A second processing step of converting the control information read in the processing of the first processing step into a control signal of a second signal standard and outputting the control signal;
The control signal of the first signal standard is composed of a first level signal of a data bit off time and a second level signal of a data bit on time having a different length depending on the bit value,
The control signal of the second signal standard is composed of signals of data bit time intervals having different levels depending on data to be expressed,
The first processing step and the second processing step are executed by a program operating in a sequence,
The first processing step extracts bit data from the control signal of the first signal standard based on the data bit off time and the data bit on time of the control signal of the first signal standard,
The second processing step outputs a signal having a data bit time level corresponding to the bit data in the extracted order as a control signal of the second signal standard. A signal processing device that transmits and receives a predetermined transmission signal with another signal processing device via an optical transmission cable,
Electrical / optical signal conversion means for converting the transmission signal in electrical signal format into optical signal format;
An optical / electrical signal conversion means for converting the transmission signal in the optical signal format transmitted from another signal transmission device connected via the optical transmission cable into an electrical signal format;
Control signal processing means for controlling reception of the control signal of the first signal standard converted into the control signal of the second signal standard in the other signal processing device,
The control signal processing means is
First processing means for reading control information from a control signal of the second signal standard;
Second processing means for generating a control signal of the first signal standard according to the control information read by the first processing means,
The control signal of the first signal standard is composed of a first level signal of a data bit off time and a second level signal of a data bit on time having a different length depending on the bit,
The control signal of the second signal standard is composed of signals of data bit time intervals having different levels depending on data to be expressed,
The first processing means and the second processing means are executed by a program operating in a sequence,
The first processing means reads the level of the data bit interval from the control signal of the second signal standard, and outputs bit data corresponding to the read level,
The second processing means outputs, in the order of output, a first level signal of the data bit off time and a second level signal of the data bit on time having a length corresponding to the output bit. As a control signal of the first signal standard. The first signal standard is a SIRCS (Serial Infrared Remote Control System) signal standard,
The signal processing apparatus according to claim 8, wherein the second signal standard is a UART (Universal Asynchronous Receiver Transmitter) signal standard. The signal processing device according to claim 8, wherein the control signal is an activation control signal for shifting the signal processing device from a standby state to a normal operation state. The first processing means generates a timer interrupt for each data bit on time, and reads a control signal of the second signal standard and outputs bit data each time a timer interrupt occurs.
The second processing means alternately generates timer interrupts for the data bit off time and the data bit on time, and each time a timer interrupt is generated, the first level signal and the output bit are used. The signal processing apparatus according to claim 8, wherein the second level signal having a length is alternately output. A signal processing method for transmitting / receiving a predetermined transmission signal to / from another signal processing device via an optical transmission cable,
An electrical / optical signal conversion step of converting the transmission signal in electrical signal format into optical signal format;
An optical / electrical signal converting step for converting the transmission signal in an optical signal format transmitted from another signal transmission device connected via the optical transmission cable into an electrical signal format;
A control signal processing step of controlling reception of the control signal of the first signal standard converted into the control signal of the second signal standard by the other signal processing device,
The control signal processing step includes
A first processing step of reading control information from a control signal of the second signal standard;
A second processing step of generating a control signal of the first signal standard according to the control information read out by the first processing step;
The control signal of the first signal standard is composed of a first level signal of a data bit off time and a second level signal of a data bit on time having a different length depending on the bit,
The control signal of the second signal standard is composed of signals of data bit time intervals having different levels depending on data to be expressed,
The first processing step and the second processing step are executed by a program operating in a sequence,
The first processing step reads the level of the data bit interval from the control signal of the second signal standard, and outputs bit data corresponding to the read level,
The second processing step includes, in the order of output, a first level signal of the data bit off time and a second level signal of the data bit on time having a length corresponding to the output bit. Is output as a control signal of the first signal standard. A program for causing a computer to execute signal processing for transmitting / receiving a predetermined transmission signal to / from another signal processing device via an optical transmission cable,
An electrical / optical signal conversion step of converting the transmission signal in electrical signal format into optical signal format;
An optical / electrical signal converting step for converting the transmission signal in an optical signal format transmitted from another signal transmission device connected via the optical transmission cable into an electrical signal format;
A control signal processing step of controlling reception of the control signal of the first signal standard converted into the control signal of the second signal standard by the other signal processing device,
The control signal processing step includes
A first processing step of reading control information from a control signal of the second signal standard;
A second processing step of generating a control signal of the first signal standard according to the control information read out by the first processing step;
The control signal of the first signal standard is composed of a first level signal of a data bit off time and a second level signal of a data bit on time having a different length depending on the bit,
The control signal of the second signal standard is composed of signals of data bit time intervals having different levels depending on data to be expressed,
The first processing step and the second processing step are executed by a program operating in a sequence,
The first processing step reads the level of the data bit interval from the control signal of the second signal standard, and outputs bit data corresponding to the read level,
The second processing step includes, in the order of output, a first level signal of the data bit off time and a second level signal of the data bit on time having a length corresponding to the output bit. As a control signal of the first signal standard. A program for causing a computer to execute signal processing.

Images