JP4720089B2 - Method for forming wiring of semiconductor device - Google Patents

Description

  The present invention relates to a method for forming a wiring in a semiconductor device, particularly using chemical mechanical polishing (CMP).

  In recent years, with the high integration of semiconductor integrated circuit formation, miniaturization and multilayering are increasingly accelerated. However, when forming a multilayer wiring structure in which miniaturization is realized, even a slight step on the wiring surface cannot be neglected, and various defects are caused by unevenness formed on the wiring surface. For example, a polishing residue and a short circuit between wirings may occur due to unevenness formed on the wiring surface. In addition, if a global step is formed by multi-layered wiring, a lithography process for forming a wiring pattern or a hole pattern causes a pattern abnormality due to misalignment or defocus, and a pattern with a desired size cannot be formed. It may cause poor connection between wiring and lower layer wiring. Therefore, there is a demand for a technique that improves the flatness of the wiring surface by reducing the level difference formed on the wiring surface, and enables further miniaturization and multilayering of the wiring structure.

  A wiring forming method using the damascene method, which is a conventional Cu wiring forming method, will be described below with reference to FIGS.

  First, as shown in FIG. 5A, an insulating film 102 is deposited on the substrate 101.

  Next, as shown in FIG. 5B, a wiring groove 103a for forming wiring and a wiring groove 103b adjacent to the wiring groove 103a are formed on the insulating film 102 by using a photolithography method and a dry etching method. Form.

  Next, as illustrated in FIG. 5C, a barrier metal 104 is deposited on the wiring groove 103 a and the wiring groove 103 b so as to cover the surface of the insulating film 102. Thereafter, a metal film 105 is formed on the barrier metal 104 so as to fill the wiring groove 103a and the wiring groove 103b.

  Next, as shown in FIG. 5D, the metal film 105 protruding from the wiring groove 103a and the wiring groove 103b is removed until the barrier metal 104 is exposed on the surface of the insulating film in which the embedded wiring is formed, and the metal film is removed. 105a is formed. Hereinafter, this process is referred to as first polishing.

  Next, as shown in FIG. 5E, the barrier metal 104 protruding from the wiring groove 103a and the wiring groove 103b is removed to form the barrier metal 104a. Hereinafter, this process is referred to as second polishing. Here, the second polishing is polishing for removing the barrier metal 104 protruding from the wiring groove 103a and the wiring groove 103b until the surface of the insulating film 102 is exposed, and then remaining on the surface of the insulating film where the embedded wiring is formed. This process is divided into polishing for removing the barrier metal 104 and metal scraps protruding from the wiring groove 103a and the wiring groove 103b. Hereinafter, the former process is referred to as barrier metal removal polishing, and the latter process is referred to as over polishing.

  In the above method, in order to remove the metal film 105 and the barrier metal 104, in general, both a chemical mechanism of oxidizing the wiring surface which is a surface to be polished and a mechanical mechanism of mechanically scraping the oxide layer are used. A chemical mechanical polishing method (CMP) that uses and polishes is employed.

For example, Patent Document 1 is known as prior art document information relating to the invention of this application.
JP-A-10-214834

  However, the conventional method has the following problems. Hereinafter, problems in the conventional method will be described with reference to FIGS.

  FIG. 6 shows the polishing amount of the barrier metal 104a, the insulating film 102, and the metal film 105a polished per unit time in the second polishing shown in FIG. Hereinafter, the polishing amount polished per unit time is referred to as a polishing rate. In damascene wiring, the surface area of the embedded wiring is 20 to 30% of the surface area of the entire substrate, and the surface area of the insulating film on which the embedded wiring of the metal film is formed is 70 to 70% of the surface area of the entire substrate. 80%. Therefore, in the conventional method, the polishing rate of the barrier metal formed on the insulating film occupying 70 to 80% of the surface area of the entire substrate is increased in the second polishing. Further, after removing the barrier metal, the insulating film occupying 70 to 80% of the surface area of the entire substrate is exposed, so the polishing rate of this insulating film is increased. Here, the purpose of the second polishing is to remove the barrier metal on the insulating film. Therefore, in the conventional wiring forming method, in the second polishing, a slurry for removing the barrier metal so that the polishing rate of the barrier metal becomes the highest polishing rate in the film to be polished is used. Further, the polishing rate of the insulating film is set to be slightly lower than the polishing rate of the barrier metal, and the polishing rate of the metal film is set to be extremely low compared to the polishing rate of the barrier metal and the polishing rate of the insulating film.

  FIGS. 7A to 7D are diagrams of a semiconductor device for explaining a problem when polishing is performed at the polishing rate shown in FIG. Here, FIG. 7A is a view of a certain wiring layer of the semiconductor device as viewed from above, and FIGS. 7B to 7D illustrate the wiring layers shown in FIG. It is sectional drawing which showed a mode that it cut | disconnected by BB 'and CC'.

  When polishing is performed at the polishing rate shown in FIG. 6, the barrier metal 104 is selectively scraped at the barrier metal removal stage. In the over polishing stage, the insulating film 102 is selectively polished.

  Here, the polishing of the insulating film 102 is to form a hydrated film on the surface of the insulating film 102 and remove it with abrasive grains. For this reason, the second polishing slurry contains a large amount of abrasive grains to increase the polishing rate of the insulating film. At this time, the slurry in which a large amount of abrasive grains are dispersed in an aqueous solution is in an unstable state because of chemical interaction between the abrasive grains, for example, van der Waals force. As described above, when the dispersed slurry is in an unstable state, the slurry aggregates, so that the wiring surface cannot be uniformly polished. Therefore, it is necessary to add a dispersing agent or the like to the slurry to prevent agglomeration of the abrasive grains. However, even if a dispersing agent is used, the abrasive grains exist in secondary particle bodies (several tens of nanometers to hundreds of tens of nanometers), and the abrasive grains agglomerate and grow into large particles unless otherwise treated. And will precipitate.

  When the abrasive grains are aggregated, while the barrier metal 104 and the insulating film 102 are being polished, the metal film 105a that is much softer than the barrier metal 104 and the insulating film 102 is caused by the abrasive grains that have become larger due to the aggregation. It can be polished and damaged. In particular, since a large pressure is applied by the polishing pad in the initial stage of the second polishing, the metal film is easily damaged by the aggregated abrasive grains.

  In this way, the surface to be polished is scraped into agglomerated abrasive grains, whereby a scratch 108 is formed on the metal film 105a, which is a softer film than other exposed films, and when metal scrap is generated, FIG. As shown in b), a bridged structure made of, for example, a granular metal film 105b may be formed to connect the embedded wiring in the wiring groove 103a and the embedded wiring in the wiring groove 103b. If such a bridging structure remains, adjacent wirings that should be insulated are joined, causing a short circuit between the wirings. Further, when scratch 109 is generated in the insulating film by polishing, metal scrap may enter the scratch of the insulating film. When the metal scrap that has entered the scratch 109 of the insulating film connects the metal films in the plurality of adjacent wiring grooves, the adjacent wirings that should be insulated are joined together, thereby causing a short circuit between the wirings. generate.

  In addition, when the malleable metal film 105a is rubbed and extended by being abraded by the agglomerated abrasive grains, as shown in FIG. 7C, the metal film is formed in the wiring groove 103a. In some cases, a bridged structure made of, for example, a band-shaped metal film 105c is formed to connect the embedded wiring and the embedded wiring in the wiring groove 103b. If such a bridging structure remains, adjacent wirings that should be insulated are joined, causing a short circuit between the wirings. Further, the metal film may be deformed plastically due to friction with the abrasive grains on the surface of the metal film after the metal film 105a has been scraped by the abrasive grains, resulting in a convex and concave portion 110. When the abrasive grains come into contact with the convex and concave portions 110, the abrasive grains collide with the convex parts and a strong frictional force acts, so that the metal film is further damaged.

  Further, when the metal film 105a is largely missing due to the abraded film being cut into agglomerated abrasive grains, as shown in FIG. 7D, the insulating film 102 is uneven, for example, a missing metal A film 105d may be generated. When such a deficient metal film 105d is generated, the wiring cross-sectional area is partially reduced, thereby increasing the wiring resistance. Further, when the missing portion is large, the wiring is further disconnected.

  In addition, when the polishing rate of the insulating film is high, the area of the metal film per unit area is large and the area of the insulating film per unit area is small in the wiring dense region where the wiring is dense. For this reason, polishing tends to proceed excessively compared with a region having a wide space between wires such as a wiring isolated region and a low wiring density. As a result, as shown in FIG. 8B, erosion occurs in which the surface of the wiring dense region is recessed from other regions. When such erosion occurs, when a metal film to be a wiring is formed in the insulating film, the insulation property of the insulating film is impaired due to the decrease in the height of the insulating film, or the wiring resistance is decreased due to the decrease in the metal film. Or increase. In addition, after the second polishing is finished, the insulating film is exposed in one region, but the barrier metal still remains in the other region, and the remaining barrier metal connects adjacent metal films to each other between the wirings. May cause a short circuit. Furthermore, if a global step is formed by the unevenness formed on the wiring surface, a pattern of a desired size cannot be formed in the lithography process for forming a wiring pattern or a hole pattern, causing a pattern abnormality due to misalignment or defocusing. Therefore, connection failure between the upper layer wiring and the lower layer wiring may be caused.

  Further, in overpolishing, when a region having a wide wiring width is polished and when the overpolishing time is long, the metal film 105a in the wiring groove 103a and the wiring groove 103b is excessively polished particularly in the wide wiring portion. As a result, as shown in FIG. 8A, dishing occurs in which the metal film 105e has a larger dent at the center than the both ends of the insulating film 102, for example, is dished. When such dishing occurs, the wiring resistance may increase due to a decrease in the volume of the metal film.

  The object of the present invention is to suppress the generation of scratches and suppress the increase in wiring resistance by controlling the polishing rate of the barrier metal, insulating film and metal film so as to match the entire surface to be polished in the second polishing. It is to prevent the short circuit between the wirings and the disconnection of the wirings and improve the flatness of the wiring surface. In addition, erosion and dishing are effectively prevented, and the flatness of the wiring surface is also achieved. As a result, it is possible to solve the problems of product yield and reliability, and to provide a highly reliable wiring formation method by the damascene method.

  In order to solve the above problems, a wiring forming method of the present invention includes a step of depositing an insulating film on a substrate, and forming a first groove and a second groove adjacent to the first groove on the insulating film. Depositing a first metal so as to cover the first groove and the second groove; depositing a second metal so as to embed the first groove and the second groove; A first polishing step for removing the second metal protruding from the first groove and the second groove by a chemical mechanical polishing method; and the second metal polishing rate and the insulating film polishing rate are the first metal A chemical mechanical polishing method is applied to the first metal, the second metal, and the insulating film protruding from the first groove and the second groove so as to be within a range of 1/3 to 1/2 of the polishing rate of And a second polishing step to be removed.

  Thus, in the second polishing, the scratch generated in the second metal is polished by setting the polishing rate of the second metal to 1/3 or more and 1/2 or less of the polishing rate of the first metal. Since it can be removed, the metal film can be prevented from being damaged. Moreover, since etching of the second metal can be suppressed, dishing can be effectively suppressed.

  Furthermore, in the second polishing, by reducing the polishing rate of the insulating film to 1/3 or more and 1/2 or less of the polishing rate of the first metal, the number of abrasive grains for removing the insulating film is reduced, Since aggregation of particles can be suppressed, formation of scratches and the like on the second metal by the aggregated abrasive grains can be suppressed. Moreover, excessive polishing of the second metal generated in a dense region of the wiring can be prevented, and the generation of erosion can be effectively suppressed.

  Further, after the first polishing step, the surface of the second metal formed in the first groove and the second groove is lower than the surface of the first metal. Is.

  Thereby, in the second polishing, the surface of the second metal is not pressed by the polishing pad, so that the second metal is hard to be polished by the abrasive grains, and the occurrence of a crosslinked structure due to a large metal defect and metal elongation can be suppressed. .

  In the first polishing, a slurry in which the polishing rate of the second metal is 10 times or more larger than the polishing rate of the first metal is used.

  Accordingly, in the first polishing, the second metal is selectively and efficiently polished, so that the polishing time can be shortened, productivity can be improved, and generation of particles can be suppressed.

  In addition, the insulating film is a laminated film containing SiO and SiOF.

  As a result, the dielectric constant of the insulating film is reduced and high-speed information processing of the semiconductor device can be achieved, so that the performance can be improved.

  According to the present invention, in the polishing of the barrier metal in the polishing process of the wiring formation, by controlling the polishing rate, it is possible to suppress the generation of scratches in the metal film, suppress the increase in wiring resistance, and disconnect the wiring, and Generation | occurrence | production of the short circuit between wiring by the residual of the bridge | crosslinking structure of a metal film can be prevented. In addition, erosion and dishing can be effectively prevented, and the flatness of the wiring surface can be achieved. As a result, a highly reliable semiconductor device can be obtained.

  Hereinafter, embodiments of the present invention will be described.

  First, points to be noted regarding CMP will be described.

  In CMP, the chemical mechanism refers to the action of generating a surface film such as an oxide film or a hydrated film, and the mechanical mechanism refers to the cutting action of abrasive grains. Further, the chemical mechanism and the mechanical mechanism act in a complex manner, not alone. In other words, CMP has a mechanical mechanism and a chemical mechanism depending on conditions such as polishing pressure, type of polishing pad, surface plate, number of rotations of polishing head, uniformity of wafer surface of polishing amount, composition ratio of compounds contained in slurry, etc. , The rate of influence will change, but will work together. That is, when polishing, in order to control the polishing rate in accordance with the surface to be polished, the mechanical and chemical mechanisms between the surface to be polished, the abrasive grains, and the liquid must be considered.

  Here, the CMP of the barrier metal, the insulating film, and the metal film in the present invention will be described.

  First, components constituting the slurry for polishing the barrier metal will be described. Most of the slurry is pure water, accounting for about 90% of the total. Another main component is abrasive grains, which occupies about 10% of the whole. For the abrasive grains, silica composed of silicon dioxide is generally used. In particular, colloidal silica is often used among silicas in order to suppress the occurrence of scratches on the copper surface. Concentrations of components other than pure water and abrasive grains are all several percent or less. The organic chemical solution has an effect of promoting the dissolution of the tantalum compound, which is a barrier metal material, by a reaction with an oxidizing agent mixed immediately before use of the slurry. The anticorrosive agent is a chemical for preventing the copper surface from corroding during the polishing of the barrier metal, and coordinates to the copper surface to protect the copper surface from corrosion. Benzotriazole is often used. The pH adjuster is added to obtain a liquid quality for the reaction of the barrier metal, the organic chemical solution, and the oxidant to proceed most stably. In general, the pH is adjusted to 2-5. Nitric acid and ammonia are often used as the pH adjuster.

CMP of the barrier metal occurs by forming a thin and soft reaction layer on the surface of the barrier metal and removing the formed reaction layer at a high speed with a small mechanical action, for example, with fine silica abrasive grains. Here, TaN will be described as an example of the barrier metal. The reaction layer of TaN surface after Ta ₂ O ₅ is formed on the Ta surface by an oxidizing agent, TaO made on its surface ^- it is a reaction product of the silanol groups of the silica surface (SiOH). This is a strong chemical action, and the chemical action becomes more active as the number of particles increases and the specific surface area increases. Therefore, the polishing rate of TaN depends on the number of abrasive grains and the specific surface area. .

  Further, in the polishing of TaN, when the pH is 4 or more, both the zeta potential of Si and the zeta potential of Ta become negative, and an electrical repulsive action is generated between particles. This repulsive action suppresses the polishing rate. Therefore, in order not to suppress the polishing rate, it is necessary to adjust the pH to 4 or less with a pH adjuster.

  The CMP of the insulating film is performed by removing the hydrated film with abrasive grains while forming a hydrated film on the surface of the insulating film. Here, since the hydrated film is sequentially formed in the polishing of the insulating film, the hydrated film is removed earlier as the number of abrasive grains increases. Therefore, the polishing rate of the insulating film depends on the number of abrasive grains. In addition, during polishing, the abrasive grains in the slurry have a much larger specific surface area than the oxide film, so that they are effectively cooled by the surrounding moisture. As a result, plastic deformation is promoted by frictional heat, the water-containing surface of the oxide film becomes high temperature, and the hardness of the oxide film tends to decrease and become soft. Such exothermic action facilitates the plastic deformation of the water-containing surface of the oxide film, and also makes the mechanical removal action by the abrasive grains advantageous.

  The CMP of the metal film is polished by removing the oxide film formed on the surface of the metal film with abrasive grains. That is, an oxidation reaction is caused on the surface of the metal film by the oxidizing agent in the slurry, and the formed oxide film is polished by the abrasive grains. Therefore, the polishing of the metal film depends on the amount of the oxidizing agent that adjusts the redox potential during polishing.

  Next, points to be noted for CMP in polishing for removing the barrier metal in the polishing process of wiring formation will be described. The barrier metal polishing in the wiring forming polishing step is continuous. Therefore, barrier metal polishing in the polishing process of wiring formation is performed by CMP conditions such as polishing pressure, type of polishing pad, surface plate, number of rotations of polishing head, wafer surface uniformity of polishing amount, and composition ratio of compounds contained in slurry. Does not change. However, in the polishing for removing the barrier metal in the wiring forming polishing step, the type of film on the surface to be polished changes depending on the progress of polishing. Therefore, in the second polishing, it is necessary to adjust the polishing rate in consideration of the type of film to be polished to achieve flatness within the substrate surface.

  For example, when polishing with a slurry containing a large amount of abrasive grains in order to increase the polishing rate of the insulating film, the abrasive grains tend to aggregate, so that a soft metal film is more abrasive than the barrier metal and the insulating film. Polishing is performed with a second polishing slurry having large grains. As a result, defects and scratches are generated in the metal film, which may cause an increase in wiring resistance and a short circuit between wirings. Therefore, in the second polishing, in addition to the flatness of the wiring surface, a slurry-containing compound that controls the polishing rate of one of the three films of the metal film, the barrier metal, and the insulating film is further included. The effect of corrosion characteristics on other films must be taken into account. In other words, in the second polishing, it is necessary not only to control the polishing rate of each film in order to achieve flatness, but also to set the polishing rate in consideration of the influence of the slurry and pad on other films. It is.

  Furthermore, in particular, over-polishing is the final step in the present invention, and the flatness of the surface to be polished greatly affects the characteristics of the Cu wiring, so the problem of erosion and dishing must also be considered.

  Therefore, in the second polishing, it is necessary to control the polishing rate of each film in a consistent manner, and to prevent erosion and dishing in consideration of metal film defects due to the influence of the corrosion characteristics of the slurry-containing compound.

  Based on the above, a method for forming a wiring of a semiconductor device according to an embodiment of the present invention will be described below with reference to the drawings.

(Embodiment 1)
FIGS. 1A to 1D and FIGS. 2A to 2D are cross-sectional views illustrating manufacturing steps of the semiconductor device according to the first embodiment of the present invention.

  First, as shown in FIG. 1A, an insulating film 2 made of a laminate containing SiO and SiOF, for example, having a thickness of 300 nm to 500 nm is deposited on a substrate 1 by a CVD method.

  Next, as shown in FIG. 1B, a resist pattern is formed using a lithography technique (not shown), and the insulating film 2 is etched using this resist pattern as a mask to form a wiring. A wiring groove 3a (depth 200 nm to 400 nm) which is one groove and a wiring groove 3b (depth 200 nm to 400 nm) which is a second groove adjacent to the wiring groove 3a are formed.

  Next, as shown in FIG. 1C, a barrier metal 4 having a thickness of, for example, 25 nm to 45 nm is deposited on the insulating film 2 so as to cover the surfaces of the wiring grooves 3a and 3b by sputtering. To do. Here, for the barrier metal 4, Ta (tantalum), a Ta-based compound, or a laminated film thereof is used. Ta or a Ta-based compound or a laminated film thereof can not only prevent the metal film 5 from diffusing into the insulating film 2, but also has a small contact potential difference between the laminated film and the metal film 5. It has the property of making it difficult to cause corrosion.

  Next, as shown in FIG. 1D, a seed layer 6 is formed on the barrier metal 4 so as to cover the surfaces of the wiring grooves 3a and the wiring grooves 3b by sputtering. Here, Cu (copper) or Cu alloy is used for the seed layer 6. For example, the Cu alloy includes an alloy made of Cu and Ag (silver), an alloy made of Cu and Al (aluminum), an alloy made of Cu, Al and Si (silicon), and the like.

  Next, as shown in FIG. 2A, a metal film 5 having a thickness of, for example, 550 nm is deposited on the seed layer 6 by electrolytic plating so as to sufficiently fill the wiring grooves 3a and 3b. Here, Cu or Cu alloy is used for the metal film 5. For example, examples of the Cu alloy include an alloy composed of Cu and Ag, an alloy composed of Cu and Al, and an alloy composed of Cu, Al, and Si.

  Next, as shown in FIG. 2B, the excess metal film 5 protruding from the wiring groove 3a and the wiring groove 3b is removed by CMP, and a metal film 5a is formed in the wiring groove 3a and the wiring groove 3b. (First polishing). At this time, since the barrier metal 4 and the metal film 5 have different chemical characteristics, the metal film 5 is relatively uniform with the barrier metal 4 protruding from the wiring groove 3a and the wiring groove 3b as a stopper film at the time of polishing. Then, it is removed with little polishing residue.

  Next, as shown in FIG. 2C, the excess barrier metal 4 protruding from the wiring groove 3a and the wiring groove 3b is removed by CMP, and the wiring groove 3a and the wiring groove 3b are covered with the barrier metal 4a. A wiring structure made of the metal film 5a is formed. Here, before the barrier metal removal polishing, as shown in FIG. 2B, the wiring groove 3a and the metal film 5a in the wiring groove 3b together with the barrier metal 4 are formed on the surface of the insulating film 2 on which the embedded wiring is formed. Exposed. However, normally, after the completion of the first polishing, the metal film 5a in the wiring groove 3a and the wiring groove 3b becomes a recess and is positioned lower than the surface of the barrier metal 4, so that the metal film 5a is removed at the barrier metal removal stage. The surface is not pressed by the polishing pad. Therefore, the mechanical polishing action hardly acts on the metal film 5a, and only the barrier metal 4 is mainly polished at the barrier metal removal stage.

  Next, as shown in FIG. 2D, surplus protruding from the wiring groove 3a and the wiring groove 3b partially remaining on the surface of the insulating film on which the embedded wiring is formed by the first polishing and the barrier metal removal polishing. Barrier metal 4 and metal scraps are removed. This is to polish the entire wiring surface until the barrier metal 4 protruding from the wiring groove 3a and the wiring groove 3b on the insulating film surface is almost completely removed.

  Here, as described above, in the second polishing, the polishing rate of each film is controlled consistently, and metal film defects due to the influence of the corrosion characteristics exerted by the slurry-containing compound are taken into account to prevent dishing and erosion. is required. Therefore, a polishing rate that satisfies these conditions will be examined below.

  In the second polishing in the present invention, first, only the barrier metal is polished in the initial stage of the barrier metal removal stage. Next, the metal film recessed by the recess is polished together with the barrier metal. Thereafter, the metal film and the barrier metal are polished until the insulating film is exposed on the wiring surface. Subsequently, the insulating film exposed by removing the barrier metal in the over-polishing step is polished together with the barrier metal and the metal film. Therefore, as the film to be polished, at the barrier metal removal stage, only the barrier metal is first considered, and after the polishing pad reaches the metal film, the barrier metal and the metal film are considered as the film to be polished. In the over polishing stage, an insulating film, a metal film, and a barrier metal are considered as a film to be polished. Note that since the barrier metal is thinner than the insulating film and the metal film, the removal of the barrier metal is hardly considered in the over-polishing stage.

3 (ai) to (di) show the ratios of the polishing rates of Cu (metal film), TaN (barrier metal), and SiO2 (insulating film) in the _second polishing, and FIG. (Dii) shows a cross-sectional view of the wiring after being polished at the respective polishing rate ratios. The vertical axis represents the polishing rate.

(i) FIG. 3 (ai) and FIG. 3 (aii) first examine the relationship between the polishing rate of the metal film and the polishing rate of the insulating film. Specifically, as shown in FIG. 3 (ai), the polishing rate of TaN, which is a barrier metal, is the highest among the polishing rates of the film to be polished, and the polishing rate of Cu, which is a metal film, is polished with TaN. The polishing rate of SiO ₂ as an insulating film was made very low compared with the polishing rate of Cu. In the following, polishing using the polishing rate shown in FIG.

  In the initial stage of the barrier metal removal stage, the metal film on the wiring portion is recessed and recessed at the end of the first polishing, so that the barrier metal on the wiring surface is selectively polished. As a result, the surface to be polished of the metal film is at a position lower than the surface of the barrier metal, and the metal film is hardly damaged by being hardly subjected to friction by the polishing pad. However, since a slurry containing a large amount of an oxidant is used to increase the polishing rate of the metal film, the metal film is reduced by a chemical etching action.

  Next, after the polishing pad reaches the metal film, the metal film is further reduced because the polishing rate of the metal film is high.

  Next, in the over-polishing stage, the insulating film having a low polishing rate is hardly subjected to chemical action, so that the polishing does not proceed and becomes a stopper film during polishing. Thereby, the polishing of the entire surface of the insulating film on which the embedded wiring is formed is stopped. However, since the metal film still has a high polishing rate, the metal film thickness continues to decrease.

  As a result, the metal film becomes concave with respect to the insulating film, and dishing as shown in FIG. When such dishing occurs, the volume of the metal film in the wiring trench is reduced, and the size of the embedded wiring is reduced. This may cause an increase in resistance of the entire wiring and a partial disconnection of the wiring.

  Therefore, from the results of FIGS. 3 (ai) and 3 (aii), the slurry in the second polishing step, that is, the slurry of the second polishing, is in a case where the difference between the polishing rate of the metal film and the polishing rate of the insulating film is large. In this case, the decrease in the metal film becomes significant, causing the problems of increase in wiring resistance and disconnection of the wiring, so that the polishing rate of the metal film and the polishing rate of the insulating film are the same, that is, the polishing rate has no significant difference. Need to choose.

(Ii) In FIGS. 3 (bi) and 3 (bii), the polishing rate of the metal film and the polishing rate of the insulating film are approximately the same based on the results of FIGS. 3 (ai) and 3 (aii). It was. For example, the case where the polishing rate of the metal film and the polishing rate of the insulating film are made very low compared to the polishing rate of the barrier metal is examined. Specifically, as shown in FIG. 3 (bi), a slurry having the highest TaN polishing rate and a very low Cu polishing rate and SiO ₂ polishing rate compared to the TaN polishing rate was used. . Hereinafter, polishing using the slurry having the polishing rate shown in FIG.

  In the initial stage of the barrier metal removal stage, the metal film on the wiring portion is recessed and recessed at the end of the first polishing, so that the barrier metal on the wiring surface is selectively polished. As a result, the surface to be polished of the metal film is at a position lower than the surface of the barrier metal, and the metal film is hardly damaged by being hardly subjected to friction by the polishing pad.

  Next, after the polishing pad reaches the metal film, the polishing rate of the metal film is very low compared to the polishing rate of the barrier metal, so that the polishing of the metal film is suppressed. However, even when the metal film has a low polishing rate, when the metal film exposed on the surface to be polished comes into contact with the polishing pad, the friction between the inert metal film surface and the abrasive grains when pressure is applied by pressing the polishing pad. And the metal film is mechanically shaved.

  Next, in the over polishing stage, the polishing of the insulating film and the metal film is difficult to proceed. That is, since the slurry is used so that the polishing rate of the insulating film and the metal film is very low compared to the polishing rate of the barrier metal, the insulating film exposed to the surface to be polished is a stopper film at the time of polishing. Thus, the polishing of the entire surface of the insulating film on which the embedded wiring is formed hardly proceeds. However, the metal film is still mechanically scraped by the polishing pad.

  As a result, defects occur in the metal film, and as shown in FIG. 3Bii, the metal film is scraped to generate scratches, or the metal film extends to form a crosslinked structure. If such a bridging structure remains, adjacent wirings that should be insulated are joined together, causing a short circuit between the wirings. In addition, when the metal film is largely lost, the wiring resistance increases and the wiring is disconnected.

  Therefore, from the results shown in FIGS. 3 (bi) and 3 (bii), the second polishing slurry has a metal film polishing rate even when the metal film polishing rate and the insulating film polishing rate are similar. In addition, when the polishing rate of the insulating film is very low compared to the polishing rate of the barrier metal, a large mechanical action is caused by the contact of the polishing pad with the metal film and the insulating film, and the metal film is damaged. There are things to do. In addition, scratches or the like may occur, and a cross-linked structure in which a conductive material is embedded may be generated. Therefore, it is necessary that the polishing rate of the metal film and the polishing rate of the insulating film are not very low compared to the polishing rate of the barrier metal.

(iii) In FIGS. 3 (ci) and 3 (cii), based on the results of FIGS. 3 (bi) and 3 (bii), the polishing rate of the metal film and the polishing rate of the insulating film are similar. The polishing rate of the metal film and the polishing rate of the insulating film were not very low compared to the polishing rate of the barrier metal. For example, the case where the polishing rate of the metal film and the polishing rate of the insulating film are set to the same level as the polishing rate of the barrier metal is examined. Specifically, as shown in FIG. 3 (ci), a slurry in which the Cu polishing rate, the TaN polishing rate, and the SiO ₂ polishing rate were all made substantially equal was used. Hereinafter, polishing using the slurry having the polishing rate shown in FIG.

  In the initial stage of the barrier metal removal stage, the metal film on the wiring portion is recessed and recessed at the end of the first polishing, so that the barrier metal on the wiring surface is selectively polished. As a result, the surface to be polished of the metal film is at a position lower than the surface of the barrier metal, and the metal film is hardly damaged by being hardly subjected to friction by the polishing pad. However, since a slurry containing a large amount of an oxidant is used to increase the polishing rate of the metal film, the metal film is reduced by a chemical etching action.

  Next, after the polishing pad reaches the metal film, the metal film further decreases because polishing proceeds at the same high polishing rate as the barrier metal.

  Next, in the over-polishing stage, since there is no significant difference in the polishing rate among the insulating film, barrier metal, and metal film exposed on the surface, polishing progresses in a relatively uniform state on the surface to be polished. Therefore, metal film defects and cross-linked structures are unlikely to occur. However, the metal film and the insulating film are polished at a high polishing rate equivalent to that of the barrier metal.

  As a result, since there is no film that acts as a stopper film, polishing of the entire film to be polished proceeds, and in particular, in the dense wiring region, erosion due to the reduction of the insulating film as shown in FIG. As a result, the insulating property of the insulating film is impaired or the wiring resistance increases. Furthermore, if a global step is formed by unevenness formed on the wiring surface, a pattern abnormality due to misalignment or defocusing will occur in the lithography process, and a pattern of the desired size cannot be formed. As a result, the wiring resistance increases and the wiring breaks.

  In addition, since there is no film serving as a stopper film in overpolishing, the overpolishing time becomes long. Therefore, the metal film in the wiring trench is excessively polished, and dishing occurs. When such dishing occurs, the wiring resistance increases as the volume of the metal film decreases.

  Therefore, from the results shown in FIGS. 3 (ci) and 3 (cii), the polishing slurry for the second polishing has the same polishing rate for the metal film and the polishing rate for the insulating film, and compared with the polishing rate for the barrier metal. However, if the polishing rate of the metal film and the polishing rate of the insulating film are as high as the polishing rate of the barrier metal, the insulating film is excessively polished. As a result, erosion in which polishing proceeds depending on the density of wiring and dishing due to excessive polishing are generated, and these cause increase in wiring resistance and disconnection of wiring. Therefore, it is necessary that the polishing rate of the metal film and the polishing rate of the insulating film are not as high as the polishing rate of the barrier metal.

(iv) FIG. 3 (di) and FIG. 3 (dii) are based on the results of FIG. 3 (ci) and FIG. 3 (cii), and the polishing rate of the metal film is similar to the polishing rate of the insulating film. The polishing rate of the metal film and the polishing rate of the insulating film were not very low as compared with the polishing rate of the barrier metal, and were not as high as the polishing rate of the barrier metal. For example, the case where the polishing rate of the metal film and the polishing rate of the insulating film are set to 1/3 or more and 1/2 or less of the polishing rate of the barrier metal is examined. Specifically, as shown in FIG. 3 (di), the TaN polishing rate is set to the highest, and the Cu polishing rate and the SiO ₂ polishing rate are set to about 1/3 to 1/2 of the TaN polishing rate. The resulting slurry was used. Hereinafter, polishing using the slurry having the polishing rate shown in FIG.

  In the initial stage of the barrier metal removal stage, the metal film on the wiring portion is recessed and recessed at the end of the first polishing, so that the barrier metal on the wiring surface is selectively polished. As a result, the surface to be polished of the metal film is at a position lower than the surface of the barrier metal, and the metal film is hardly damaged by being hardly subjected to friction by the polishing pad.

  Next, after the polishing pad reaches the metal film, the polishing of the metal film proceeds at a polishing rate of 1/3 to 1/2 of the barrier metal polishing rate. Therefore, when the pressure is applied by pressing the polishing pad, friction between the inert metal film surface and the abrasive grains does not occur. Even when the metal film is scratched when pressed by the polishing pad, polishing is performed while removing the scratch. Furthermore, in this case, polishing of the metal film is suppressed, and the occurrence of dishing is suppressed.

  Next, in the over polishing stage, the polishing rate of the insulating film is agglomerated because abrasive grains having a small amount of particles are used to adjust the polishing rate to 1/3 or more and 1/2 or less of the polishing rate of the barrier metal. The generation of abrasive grains is suppressed and the metal film is prevented from being damaged. Further, since the polishing rate of the insulating film is less than 1/2 of the polishing rate of the barrier metal, it is possible to prevent excessive polishing of the metal film generated in the dense region of the wiring due to the progress of polishing, and erosion Is suppressed. Furthermore, the metal film is polished while still removing scratches and effectively suppressing dishing.

  As a result, as shown in FIG. 3 (dii), the occurrence of a bridging structure and a metal film defect that induces a short circuit between wirings is prevented, and a highly flat wiring surface without dishing or erosion can be obtained.

  Here, the reason why it is desirable that the polishing rate of the metal film and the polishing rate of the insulating film be 1/3 or more of the polishing rate of the barrier metal will be described.

  First, the polishing amount of the metal film from which scratches are removed in the second polishing is defined. FIG. 4 shows the result of measuring the level difference formed on the substrate surface after completion of the second polishing using an atomic force microscope (AFM). In FIG. 4, the vertical axis is the surface step, and the horizontal axis is the scanning distance.

  As shown in FIG. 4, the maximum value of the depth of the scratch generated when the foreign matter contained in the film to be polished is involved in the polishing is about 10 nm at the maximum. For this reason, in order to prevent the occurrence of scratches in the over-polishing stage, considering the appropriate margin, for example, the polishing amount of the metal film and the insulating film is set to 15 nm or more, 1.5 times the maximum predicted value of the scratch. It is desirable to do. Here, for scratches with a depth less than 10 nm, the polishing rate of the metal film that can remove scratches with a depth of 10 nm is used, so scratches that are shallower than that can be removed by polishing. Conceivable.

  Next, the amount of barrier metal polished in the second polishing is defined. In over-polishing, in order to prevent a short circuit between wirings, it is necessary to polish the entire surface of the insulating film on which the embedded wiring is formed until the barrier metal is almost completely removed from the portion other than the wiring trench. For this reason, in overpolishing, it is necessary to polish in consideration of the maximum overall film thickness variation of the barrier metal. Here, the film thickness variation within the substrate surface of the barrier metal film formation is 10% at the maximum, the film thickness variation between the substrates of the barrier metal film formation is a maximum of 10%, the film thickness variation within the substrate surface by the CMP method is a maximum of 20%, and the CMP method. The inter-substrate film thickness variation due to the maximum is 10%, and the entire film thickness variation is expressed by the average of the sum of these squares (variation propagation law).

Σ = √ (σa ² + σb ² + σc ² + σd ² ) (1)
σa: In-substrate film thickness variation in barrier metal film formation σb: In-substrate film thickness variation in barrier metal film formation σc: In-substrate film thickness variation in CMP σd: In-film film thickness variation in CMP equation (1) Thus, in this wiring structure, the maximum overall film thickness variation of the barrier metal is 26%. In consideration of the film thickness variation margin, over-polishing has a film thickness variation of about 30% in addition to the barrier metal removal polishing. Over polishing is required. Therefore, for example, if the deposited film thickness of the barrier metal is 35 nm, the amount of the barrier metal polished in the second polishing is desirably 45.5 nm.

  From the above, when examining the ratio of the polishing rate of the metal film and the polishing rate of the barrier metal so as not to generate scratches in the second polishing, the polishing time is the same for both the metal film and the barrier metal. It turns out that. As described above, the metal film needs a polishing amount of 15 nm or more, and the barrier metal has a polishing amount of 45.5 nm. Here, the ratio between the polishing amount of the metal film of 15 nm and the polishing amount of the barrier metal of 45.5 nm is 1: 3. Therefore, the polishing rate of the metal film is 1/3 of the polishing rate of the barrier metal.

  Thus, the polishing rate of the metal film that does not generate scratches in the second polishing needs to be 1/3 or more of the polishing rate of the barrier metal.

  Here, a case where the deposited film thickness of the barrier metal is larger than 35 nm, that is, a case where the deposited amount of the barrier metal is larger than 35 nm is considered. In this case, since the thickness of the barrier metal is increased, the polishing time becomes longer, and the polishing amount of the metal film is expected to be 15 nm or more. Therefore, 10 nm scratches can be sufficiently removed.

  Next, description will be made on setting the polishing rate of the metal film and the polishing rate of the insulating film to ½ or less of the polishing rate of the barrier metal.

  There are the following two explanations for setting the polishing rate of the metal film and the polishing rate of the insulating film to ½ or less of the polishing rate of the barrier metal.

  First, consider the case where the insulating film is a laminated film. The laminated film is, for example, an SiO film having a thickness of about 20 to 30 nm and an SiOF film having a thickness of about 200 to 400 nm in order from the wiring surface. Here, the reason why the insulating film is a laminated film is to reduce the interlayer capacitance and realize an insulating film having a low relative dielectric constant.

  In this case, if the upper SiO film is completely polished by the second polishing, the lower SiOF film is exposed on the surface. If the underlying SiOF film is exposed on the surface, the dielectric constant of SiOF increases due to moisture absorption. Further, when the moisture-absorbing insulating film remains in the damascene wiring, the embedded metal film is corroded. Therefore, it is necessary to leave the upper SiO film on the lower SiOF film. Therefore, the amount of polishing of the insulating film is about 1 nm to 20 nm in order to leave the upper SiO film of the insulating film stack. Therefore, the polishing amount of the insulating film needs to be 20 nm or less.

  By the way, as described above, when the deposited film thickness of the barrier metal is 35 nm, the polishing amount of the barrier metal in the second polishing is expected to be 45.5 nm in consideration of the in-film variation and the margin. Here, the ratio between the polishing amount of the insulating film of 20 nm and the polishing amount of the barrier metal of 45.5 nm is about 1: 2. Therefore, the polishing rate of the insulating film is ½ of the polishing rate of the barrier metal.

  Next, the second occurs when the polishing rate of the metal film and the insulating film shown in FIGS. 3 (ci) and 3 (cii) is polished with a slurry that is as high as the polishing rate of the barrier metal. Consider erosion that depends on the density of wiring. At this time, the erosion generated in the second polishing is about 30 nm to 50 nm.

  Here, when the decrease in the insulating film is significant, the insulating property of the insulating film is impaired, or the wiring resistance increases due to the decrease in the metal film.

  As described above, in order to prevent the exposure of SiOF, erosion must be suppressed to 20 nm or less so that SiO remains in the second polishing. Here, a good polishing amount 20 nm of the insulating film in the second polishing and 50 nm which is the maximum value of the erosion of the insulating film are in a relationship of about 1: 2. Further, in FIGS. 3Ci and 3Cii, the polishing rate of the insulating film is approximately the same as the polishing rate of the barrier metal. Therefore, the polishing rate of the insulating film is ½ of the polishing rate of the barrier metal.

  From these two things, the polishing rate of the insulating film in the second polishing needs to be 1/2 or less of the polishing rate of the barrier metal.

  Here, the case where the deposited thickness of the barrier metal is smaller than 35 nm, that is, the case where the deposited amount of the barrier metal is smaller than 35 nm is considered. In this case, since the thickness of the barrier metal is reduced, the polishing time is shortened, and the polishing amount of the insulating film can be suppressed to 20 nm or less. Therefore, it is considered that SiO remains, and moisture absorption of SiOF can be prevented.

  In the present invention, the polishing rate of the metal film and the insulating film is approximately the same. The polishing rate of the metal film and the insulating film is independently within the range of 1/2 to 1/3 of the polishing rate of the barrier metal. It means that. Within that range, for example, when the polishing rate of the metal film is 1/2 of the polishing rate of the barrier metal and the polishing rate of the insulating film is 1/3 of the polishing rate of the barrier metal, or the polishing rate of the metal film is It may be a case where the polishing rate of the barrier metal is 1/3 and the polishing rate of the insulating film is 1/2 of the polishing rate of the barrier metal.

  In the present invention, the polishing rate of the metal film and the insulating film is not too low means that the polishing rate of the metal film and the insulating film is 1/3 or more of the polishing rate of the barrier metal.

  In the present invention, the polishing rate of the metal film and the insulating film is not as high as the polishing rate of the barrier metal. The polishing rate of the metal film and the insulating film is ½ or less of the polishing rate of the barrier metal. That means.

  From the above, it is clear that the polishing rate ratio is most suitable for removing the barrier metal as shown in FIG. In the second polishing, the present embodiment provides a wiring forming method in which the polishing rate of the metal film and the polishing rate of the insulating film are set to 1/2 or more and 1/3 or less of the polishing rate of the barrier metal. . In this way, in the second polishing, the scratch generated on the metal film can be polished and removed by setting the polishing rate of the metal film to 1/2 or more and 1/3 or more of the polishing rate of the barrier metal. It can prevent the metal film from being lost. Further, since excessive etching of the metal film can be suppressed, dishing can be effectively suppressed.

  Furthermore, by setting the polishing rate of the insulating film to 1/3 or more and 1/2 or less of the polishing rate of the barrier metal, the number of abrasive grains for removing the insulating film can be reduced and aggregation of the particles can be suppressed. In addition, it is possible to suppress the loss of the metal film due to the aggregated abrasive grains. In addition, it is possible to prevent excessive polishing of the metal film generated in the dense region of the wiring, and to effectively suppress the generation of erosion.

  As a result, the polishing rate of each film in the second polishing can be controlled consistently, the corrosion effect of metal film defects and the like can be suppressed, and erosion and dishing can be prevented, thereby suppressing an increase in wiring resistance of the semiconductor device. It is possible to prevent the occurrence of a short circuit between wires and the disconnection of the wires. According to the present invention, a highly reliable semiconductor device can be obtained.

  As mentioned above, this invention is useful for the formation method of the wiring using a slurry, etc.

Process sectional drawing of the formation method of wiring in a first embodiment of the present invention Process sectional drawing of the formation method of wiring in a first embodiment of the present invention Sectional view of the selection ratio of the slurry and wiring in the first embodiment of the present invention Figure showing scratch steps Cross-sectional process diagram of conventional wiring formation method The figure which shows the selection ratio of the slurry in the formation method of the conventional wiring Cross-sectional view of wiring for explaining problems in conventional wiring forming method Cross-sectional view of wiring for explaining problems in conventional wiring forming method

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Substrate 2 Insulating film 3a Wiring groove 3b Wiring groove 4 Barrier metal 4a Barrier metal 5 Metal film 5a Metal film 7a Metal film 7b Metal film 101 Substrate 102 Insulating film 103a Wiring groove 103b Wiring groove 104 Barrier metal 104a Barrier metal 105 Metal film 105a Metal film 105b Metal film 105c Metal film 105d Metal film 105e Metal film 108 Scratch 109 Scratch 110 Convex and concave portions

Claims (5)

Depositing an insulating film comprising a SiO film with an upper layer of 20 to 30 nm on the substrate and a SiOF film on the lower layer on the substrate;
Forming a first groove and a second groove adjacent to the first groove on the insulating film;
Depositing TaN (tantalum nitride) having a film thickness of 35 nm or more so as to cover the first groove and the second groove;
Depositing a metal to fill the first groove and the second groove;
A first polishing step of removing the metal protruding from the first groove and the second groove by a chemical mechanical polishing method;
As polishing rate of the polishing rate and the SiO film of the metal is in the range of 1/3 1/2 of the polishing rate of TaN (tantalum nitride), before Symbol first groove and said second groove the TaN method of forming a wiring, characterized in that it comprises a second polishing step of removing the (tantalum nitride) and chemical mechanical polishing the metals protruding from. 2. The wiring according to claim 1, wherein after the first polishing step, the metal in the first groove and the second groove is recessed as compared with the TaN (tantalum nitride). Forming method. The wiring formation method according to claim 1, wherein the metal is Cu (copper). 4. The slurry according to claim 1, wherein in the first polishing step, a slurry in which the polishing rate of the metal is 10 times or more larger than the polishing rate of the TaN (tantalum nitride) is used. Wiring formation method. Said first groove and forming method of the wiring in the second groove, the method for forming a wiring according to claims 1 to 1 wherein one of the 4, characterized in that it is carried out using a damascene method.

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