JP4724578B2 - Level shift circuit - Google Patents

Description

  The present invention relates to a level shift circuit that shifts the level (for example, low potential) of an input signal to another level (for example, high potential).

  Conventionally, as a technique related to the level shift circuit, for example, there are those described in the following documents.

Japanese Patent Laid-Open No. 5-284005

  FIG. 15 is a circuit diagram showing an example of a conventional level shift circuit described in Patent Document 1. In FIG.

  This level shift circuit includes a VDD 1 -GND system circuit 1 for inputting an input signal IN that changes between a ground potential GND (0 V) and a power supply potential VDD 1 (eg, 3 V), and the VDD 1 -GND system circuit 1 The circuit is configured by a VDD2-GND system circuit 10 for shifting an applied signal level and outputting an output signal OUT that changes between a ground potential GND and a power supply potential VDD2 (for example, 62V). The VDD1-GND system circuit 1 is composed of an inverter 2 that receives an input signal IN and generates a signal having a reverse phase. The VDD2-GND circuit 10 includes VDD2 P-channel MOS transistors (hereinafter referred to as “PMOS”) 11 and 12, and VDD2 N-channel MOS transistors (hereinafter referred to as “NMOS”) 13 and 14. .

  That is, the input signal IN is input to the gate of the NMOS 13, and a signal having a phase opposite to that of the input signal IN generated by the inverter 2 is input to the gate of the NMOS 14. The sources of the NMOSs 13 and 14 are connected to the ground potential GND, and the drain of the NMOS 13 is connected to the drain of the PMOS 11 and the gate of the PMOS 12 via the first output node N11. The drain of the NMOS 14 is connected to the drain of the PMOS 12 and the gate of the PMOS 11 via the second output node N12 for outputting the output signal OUT. The sources of the PMOSs 11 and 12 are connected to the power supply potential VDD2.

  FIG. 16 is a voltage waveform diagram showing the simulation result of the level shift operation of FIG. 15, where the horizontal axis represents time (Time) and the vertical axis represents potential (Voltages).

  The operation of the level shift circuit of FIG. 15 will be described. When the input signal IN is at a low level (hereinafter referred to as “L level”) of the ground potential GND, the NMOS 13 is turned off and the NMOS 14 is turned on. Since the NMOS 14 is turned on, the gate potential of the PMOS 11 (the potential of the output node N12) is lowered and the PMOS 11 is turned on. Since the PMOS 11 is on and the NMOS 13 is off, the gate potential of the PMOS 12 (potential of the output node N11) rises to the power supply potential VDD2, and the PMOS 12 is turned off. Here, the circuit is stable, and the output signal OUT having the ground potential GND is output from the output node N12.

  When the input signal IN becomes a high level (hereinafter referred to as “H level”) of the power supply potential VDD1, an operation opposite to the above-described operation occurs. That is, since the NMOS 13 is turned on and the NMOS 14 is turned off, the gate potential of the PMOS 12 connected to the drain of the NMOS 13 (the potential of the output node N11) is lowered, and the PMOS 12 is gradually turned on. When the PMOS 12 is turned on and the NMOS 14 is turned off, the gate potential of the PMOS 11 (potential of the output node N12) gradually increases, and eventually the PMOS 11 is turned off. As a result, the gate potential of the PMOS 12 is lowered to the ground potential GND and is completely turned on. Then, the output signal OUT of the power supply potential VDD2 is output from the output node N12.

  However, the conventional level shift circuit of FIG. 15 has the following problems (a) and (b).

  (A) In the level shift circuit of FIG. 15, when performing level conversion from a low potential to a high potential, the gate input potential to the NMOSs 13 and 14 which are high breakdown voltage elements is low. Do not work. This has a problem that the sizes of the NMOSs 13 and 14 paired with the PMOSs 11 and 12 must be increased.

  (B) As shown in FIG. 16, when the power supply potential VDD1 on the low potential side is lowered, the ability of the NMOSs 13 and 14 is reduced, so that it takes time to switch the level shift circuit, so that the PMOS 11 and the NMOS 13 or the PMOS 12 are switched. There is a problem that the intermediate state in which the NMOS 14 and the NMOS 14 are open at the same time is long, and a through current continues to flow from the power supply potential VDD2 to the ground potential GND.

  In order to solve the problems (a) and (b), Patent Document 1 adopts the following means (1) and (2).

  (1) In FIG. 15, the first NMOS for current cutoff is connected in series between the output node N11 and the drain of the NMOS 13, and the current cutoff is connected between the output node N12 and the drain of the NMOS 14. A second NMOS is connected in series. When the PMOS 11 and the NMOS 13 and the PMOS 12 and the NMOS 14 are simultaneously turned on, the first and second NMOSs are turned off for a short period of time to cut off the current path from the power supply potential VDD2 to the ground potential GND. The current is reduced.

  (2) First and second differentiation circuits are connected to the output nodes N11 and N12, respectively, and the rise of the potentials of the output nodes N11 and N12 is accelerated by the first and second differentiation circuits, and the PMOSs 11 and 12 are turned on. The switching time from the state to the off state is shortened. Thereby, the transition time of the H level and the L level of the output signal OUT output from the output node N12 is shortened, and the response speed of the output signal OUT with respect to the input signal IN is increased.

  However, in the case of (1), the first and second NMOSs for current interruption are connected in series between the output nodes N11 and N12 and the NMOSs 13 and 14, respectively. The response speed is slowed down by the time necessary for the NMOS to operate, which limits the speedup. In the case of (2), the first and second differentiating circuits are each composed of, for example, a capacitor, a resistor, and an NMOS. Therefore, manufacturing variations of the capacitor and the resistor, an increase in circuit formation area for forming the capacitor, etc. Therefore, problems remain in terms of reliability and circuit size reduction.

  An object of the present invention is to solve such a conventional problem and to provide a level shift circuit capable of reducing the circuit scale, having high reliability, high response speed, and low through current.

  The level shift circuit according to the first, fourth, sixth, and seventh aspects of the present invention is connected between the first power supply potential and the first output node, and outputs a second output. A first transistor that is turned on by a first potential of the node and turned off by a second potential; and is connected between the first power supply potential and the second node; A second transistor which is turned on by the first potential and turned off by the second potential, and is connected between the first output node and a second power supply potential, and A third transistor that is turned off by a potential of 1 and turned on by the second potential, and is connected between the second output node and the second power supply potential, and It is turned off by the potential of 1, and turned on by the second potential. A fourth transistor is connected between the first output node and the second output node, and is turned off by the first potential of the third signal and turned on by the second potential. A fifth transistor; and a signal generation circuit that generates the first, second, and third signals to be provided to the first, second, and third transistors.

  The signal generation circuit includes: a first input signal that changes to a first logic level and a second logic level; and the first logic level delayed by a predetermined delay time from the change of the first input signal. And a second input signal that changes to the second logic level, the second input signal changes to the second logic level when the second input signal changes to the second logic level, and the first input The first signal that changes to the first logic level when the signal changes to the first logic level, and the first logic level that changes to the second logic level when the first input signal changes to the second logic level. And when the second input signal changes to the first logic level, the second signal changes to the second logic level, and when the second signal changes to the first logic level. During the delay time, the second potential is set. Serial between the delay time the first signal is changed to the first logic level is a circuit for generating said third signal to be the second potential.

  The level shift circuit according to the second, fifth, sixth, and seventh aspects of the invention is connected between the first power supply potential and the first output node, and the first output node of the second output node that outputs an output signal is provided. A first transistor that is turned on by a potential and turned off by a second potential, and is connected between the first power supply potential and the second node, and the first potential of the first node Connected to the second transistor which is turned on by the second potential and turned off by the second potential, and connected between the first output node and the second power supply potential, and is turned off by the first potential of the first signal. A third transistor that is turned on by the second potential, and is connected between the second output node and the second power supply potential, and is turned off by the first potential of the second signal. State, the fourth transistor that is turned on by the second potential. A fifth transistor connected in parallel with the third transistor, and turned off by the first potential of the third signal and turned on by the second potential; and the fourth transistor; A sixth transistor connected in parallel and turned off by the first potential of the fourth signal and turned on by the second potential, and a signal generation circuit.

  The signal generation circuit includes: a first input signal that changes to a first logic level and a second logic level; and the first logic level delayed by a predetermined delay time from the change of the first input signal. And a second input signal that changes to the second logic level, the second input signal changes to the second logic level when the second input signal changes to the second logic level, and the first input The first signal that changes to the first logic level when the signal changes to the first logic level, and the first logic level that changes to the second logic level when the first input signal changes to the second logic level. And when the second input signal changes to the first logic level, the second signal changes to the second logic level, and the first input signal changes to the second logic level. Then, during the delay time, the second potential is not reached. Wherein a third signal, between said first input signal is changed to the first logic level the delay time, a circuit for generating said fourth signal which becomes the second potential.

  The level shift circuit according to the third, fifth, sixth, and seventh aspects of the invention is different from the first, second, third, fourth, fifth, and sixth transistors that are the same as those of the second aspect. And a signal generation circuit.

  The signal generation circuit includes the first signal that is the same as the first input signal that changes between a first logic level and a second logic level, and the second signal that is in reverse phase with respect to the first signal. And a second input signal that changes to the first logic level and the second logic level after being delayed by a predetermined delay time from the change of the first input signal and the first input signal. And when the first input signal changes to the second logic level, the third signal that becomes the second potential during the delay time and the first input signal is the first logic level. When the level changes, the circuit generates the fourth signal that becomes the second potential during the delay time.

  According to the first, fourth, sixth, and seventh aspects of the present invention, the operation can be performed at a faster response speed than the conventional level shift circuit. Furthermore, since the period during which the first and second transistors and the third and fourth transistors are turned on simultaneously is short, the through current can be suppressed. In the signal generation circuit, a through current flows while the third signal is at the second logic level, but the circuit size can be designed small, and only during a short delay time, the entire level shift circuit Does not significantly affect the operation.

  According to the second, fifth, sixth, and seventh aspects of the invention, the potential is directly dropped using the third and fourth transistors, so that a higher speed operation is possible. Furthermore, since the first and second transistors are used only for maintaining the potential after the potential is completely lowered, for example, the size can be reduced as compared with the conventional level shift circuit.

  The level shift circuit of the invention is connected between a first power supply potential (for example, power supply potential VDD2) and a first output node, and outputs a first potential (for example, a second output node that outputs an output signal). A first transistor that is turned on by an L level and turned off by a second potential (eg, H level), and is connected between the first power supply potential and the second node, A second transistor that is turned on by the first potential and turned off by the second potential, and between the first output node and a second power supply potential (eg, ground potential GND). A third transistor connected and turned off by the first potential of the first signal and turned on by the second potential; and between the second output node and the second power supply potential. The first potential of the connected second signal A fourth transistor which is turned off by the second potential, and is connected between the first output node and the second output node, and is connected to the first potential of the third signal. A fifth transistor that is turned off by the second potential, and a signal generation circuit that generates the first, second, and third signals to be applied to the first, second, and third transistors And have.

  The signal generation circuit has a first input signal that changes to a first logic level (for example, L level) and a second logic level (for example, H level), and a predetermined amount based on a change in the first input signal. When the second input signal changes to the second logic level based on the first logic level and the second input signal that changes to the second logic level after a delay time, the second logic level is changed. When the first input signal changes to the first logic level, the first signal changes to the first logic level, and the first input signal changes to the second logic level. The second signal changes to the first logic level when changing to a logic level, and changes to the second logic level when the second input signal changes to the first logic level; Signal changes to the first logic level. The second potential is generated during the delay time, and when the first signal changes to the first logic level, the third signal that is the second potential is generated during the delay time. Circuit.

(Configuration of Example 1)
FIG. 1 is a circuit diagram of a level shift circuit showing a first embodiment of the present invention.

  This level shift circuit receives a first input signal IN that changes between a second power supply potential (for example, ground potential GND (0 V)) and a power supply potential VDD1 (for example, 3 V), and receives the main level shift unit 50. VDD1-GND system circuit 20 which is a signal generation circuit for generating signals for controlling the signals (first and second signals A and B and complementary signals C and CB) and signals C and CB are input. Then, the simplified level shift unit 40 of the VDD2-GND system circuit 30 which is a signal generation circuit for generating the third signal C3 for controlling the main level shift unit 50, and the first, second and third signals A , B, C3, the main level shift of the VDD2-GND system circuit 30 for outputting the output signal OUT that changes between the ground potential GND whose level has been shifted and the first power supply potential VDD2 (for example, 62V). Part 50.

  The VDD1-GND system circuit 20 delays the input signal IN by a predetermined delay time τD and outputs a second input signal IN2, and first and second input signals IN. , IN2 to obtain a logical product of the two-input logical product gate (hereinafter referred to as "AND gate") 22 that outputs the first signal A and the negative logical sum of the first and second input signals IN, IN2. Find the two-input negative OR gate (hereinafter referred to as “NOR gate”) 2 3 that outputs the second signal B and outputs the signal C by calculating the negative OR of the first and second signals A and B. The two-input NOR gate 24 and the inverter 25 that inverts the signal C and outputs the signal CB.

  The simple level shift unit 40 of the VDD2-GND system circuit 30 is connected in series between the high voltage PMOS 41 and the high voltage NMOS 43 connected in series between the power supply potential VDD2 and the ground potential GND, and between the power supply potential VDD2 and the ground potential GND. The high-voltage PMOS 42 and the high-voltage NMOS 44 are connected to each other. The gates of the PMOSs 41 and 42 are connected to the drain of the PMOS 41 and the drain of the NMOS 43, and a signal C is input to the gate of the NMOS 43. The drain of the PMOS 42 is connected to the drain of the NMOS 44 via a node N53 that outputs the third signal C3, and the signal CB is input to the gate of the NMOS 44.

  The simple level shift unit 40 is not used in a normal level shift circuit because it has a drawback that through current continues to flow through the PMOS 41 and the NMOS 43 while the signal C is at the H level although the switching operation is high speed. is there. The third signal C3 output from the node N53 of the simple level shift unit 40 is supplied to the main level shift unit 50 of the VDD2-GND system circuit 30.

  The main level shift unit 50 includes VDD2 system first and second transistors (for example, PMOS) 51 and 52, VDD2 system third and fourth transistors (for example, high voltage NMOS) 53 and 54, and conventional ones. A fifth transistor (for example, a breakdown voltage NMOS) 55 added to the level shift circuit of FIG.

  That is, the first signal A given from the VDD1-GND system circuit 20 is inputted to the gate of the NMOS 53, and the second signal B given from the VDD1-GND system circuit 20 is inputted to the gate of the NMOS 54. The sources of the NMOSs 53 and 54 are connected to the ground potential GND, and the drain of the NMOS 53 is connected to the drain of the PMOS 51 and the gate of the PMOS 52 via the first output node N51. The drain of the NMOS 54 is connected to the drain of the PMOS 52 and the gate of the PMOS 51 via the second output node N52 for outputting the output signal OUT. The sources of the PMOSs 51 and 52 are connected to the power supply potential VDD2. The source / drain of the newly added NMOS 55 is connected between the output nodes 51 and 52, and the gate of the NMOS 55 is connected to the node N53.

(Operation of Example 1)
FIG. 2 is a diagram showing an outline of the time chart of the level shift operation of FIG. 1, where the horizontal axis represents time and the vertical axis represents the logic level (potential). FIG. 3 is a voltage waveform diagram showing an outline of the simulation result of the level shift operation of FIG.

  For example, consider the initial state where the NMOS 53 is off and the NMOS 54 is on. The drain side potential of NMOS 53 (potential of output node N51) is power supply potential VDD2, and the drain side potential of NMOS 54 (potential of output node N52) is OV of ground potential GND.

  When the human power signal IN changes from the first logic level (for example, L level) to the second logic level (for example, H level), the delay element 21 generates the input signal IN2 delayed by the delay time τD. The signals IN and IN2 are supplied to the AND gate 22 and the NOR gate 23 to generate the L level of the signals A and B, and the NMOSs 53 and 54 are simultaneously turned off only during the delay time τD. During this time, the signal C generated by the NOR gate 24 from the signals A and B becomes H level, the signal C3 output from the node N53 of the simple level shift unit 40 changes to H level (VDD2), and the NMOS 55 Turns on.

  As a result, charges move at the output nodes N51 and N52 on both sides of the main level shift unit 50, and the drain side potential of the NMOS 54 (potential of the output node N52) changes from the first potential (for example, L level) to the second level. The potential rises to a potential (for example, H level), and the drain side potential (the potential of the output node N51) of the NMOS 53 falls from the second potential (for example, H level) to the first potential (for example, L level). When the NMOS 53 is turned on after the delay time τD, the drain side potential of the NMOS 54 (the potential of the output node N52), that is, the gate potential of the PMOS 51 has risen to a certain level, so that the capability of the PMOS 51 is reduced. As a result, the drain-side potential of the NMOS 53 (the potential of the output node N51) quickly decreases to OV.

(Effect of Example 1)
According to the level shift circuit of the first embodiment, it is possible to operate at a faster response speed than the conventional level shift circuit of FIG. Furthermore, since the period of the intermediate potential is short, an effect of suppressing the through current can be obtained. The simple level shift unit 40 allows a through current to flow while the signal C is at an H level, but the circuit size can be designed to be small, and only during a short delay time τD. Does not have a big impact.

  FIG. 4 is a current waveform diagram showing an outline of a simulation result obtained by comparing the through current between the conventional level shift circuit of FIG. 15 and the level shift circuit of the first embodiment, where the horizontal axis represents time and the vertical axis. Is currents.

  As is apparent from FIG. 4, the total through current is reduced by shortening the time during which the potential is intermediate. Further, the through current of the simple level shift unit 40 that flows while the signal C is at the H level is also small.

(Configuration of Example 2)
FIG. 5 is a circuit diagram of a level shift circuit showing a second embodiment of the present invention. Elements common to those in FIG. 1 showing the first embodiment are denoted by common reference numerals.

  The level shift circuit according to the second embodiment inputs a first input signal IN that changes between a second power supply potential (for example, ground potential GND (0 V)) and a power supply potential VDD1 (for example, 3 V). This is a signal generation circuit for generating signals (first and second signals A and B, complementary signals C and CB, and complementary signals D and DB) for controlling the level shift unit 50-1. VDD1-GND system circuit 30-1, which is a signal generation circuit for generating the third signal C3 for inputting the signals C, CB and controlling the main level shift unit 50-1 by inputting the VDD1-GND system circuit 20-1. 1 and a VDD2-GND system circuit 30-1, which is a signal generation circuit for generating a fourth signal D4 for controlling the main level shift unit 50-1 by inputting the signals D and DB. The level is shifted based on the simple level shift unit 40-1 and the first, second, third, and fourth signals A, B, C3, and D4. The main level shift unit 50-1 of the VDD2-GND system circuit 30-1 for outputting the output signal OUT that changes between the potential GND and the first power supply potential VDD2 (for example, 62V).

  The VDD1-GND system circuit 20-1 includes a delay means (for example, a delay element) 21 that delays the input signal IN by a predetermined delay time τD and outputs a second input signal IN2, and first and second inputs. A two-input AND gate 22 that obtains a logical product of the signals IN and IN2 and outputs the first signal A, and a negative logical sum of the first and second input signals IN and IN2 to obtain the second signal B A 2-input NOR gate 23 to be output, an inverter 26-1 for inverting the first input signal IN, an inverter 26-2 for inverting the second input signal IN2, an output signal of the inverter 26-1 and the second A two-input NOR gate 24 that obtains a negative OR of the input signal IN2 and outputs a signal C, an inverter 25 that inverts the signal C and outputs a signal CB, a first input signal IN and an inverter 26-2 A two-input NOR gate 27 that obtains a negative logical sum of the output signals and outputs a signal D, and inverts the signal D to generate a signal DB It is composed of an output inverter 26-3.

  The signal C is a signal that becomes H level only during the delay time τD from the rising edge of the input signal IN, and the signal D is a signal that becomes H level only during the delay time τD from the falling edge of the input signal IN.

  The simple level shift unit 40 of the VDD2-GND system circuit 30-1 is the same circuit as the simple level shift unit 40 of the first embodiment. The simple level shift unit 40-1 of the VDD2-GND system circuit 30-1 includes the same PMOS 41-1, 42-1, and NMOS 43-1, 44- as the PMOS 41, 42 and the NMOS 43, 44 constituting the simple level shift unit 40. 1. In the simple level shift unit 40-1, the signal D is input to the gate of the NMOS 43-1, the signal DB is input to the gate of the NMOS 44-1, and a node between the drain of the PMOS 42-1 and the source of the NMOS 44-1. A fourth signal D4 is output from N53-1.

  The main level shift unit 50-1 includes a fifth transistor (for example, NMOS) 55-1 and a sixth transistor (for example, NMOS) 56 instead of the NMOS 55 in the main level shift unit 50 of the first embodiment. The NMOS 55-1 is connected in parallel to the NMOS 53, and the NMOS 56 is connected in parallel to the NMOS 54. A third signal C3 is input to the gate of the NMOS 55-1, and a fourth signal D4 is input to the gate of the NMOS 56-1.

  In the level shift circuit according to the second embodiment, NMOSs 55-1 and 56 are connected in parallel to the NMOSs 53 and 54, which have low capabilities in the main level shift unit 50 according to the first embodiment, and the gates of the NMOSs 55-1 and 56 are connected. The third and fourth signals C3 and D4 generated by the simple level shift units 40 and 40-1 are input, and the NMOS 55-1 and 56 speed up the potential change at the time of switching.

(Operation of Example 2)
FIG. 6 is a diagram showing an outline of the time chart of the level shift operation of FIG. 5, where the horizontal axis is time and the vertical axis is the logic level (potential). FIG. 7 is a voltage waveform diagram showing an outline of the simulation result of the level shift operation of FIG. 5.

  In the level shift circuit of the second embodiment, the NMOS 55-1 is turned on by the third signal C3 before the NMOS 53 is turned on by the first signal A, so that the drain sides of the NMOS 53 and 55-1 are turned on. The potential (the potential of the output node N51) is lowered at high speed to speed up the switch operation. In the reverse change, before the NMOS 54 is turned on by the second signal B, the NMOS 56 is turned on by the fourth signal D4, thereby speeding up the switching operation from the on state to the off state.

(Effect of Example 2)
In the first embodiment, the electric potential at the output nodes N51 and N52 on both sides of the main level shift unit 50 is moved to act as a potential decrease trigger. In addition, NMOS 53 and 54 were used. On the other hand, in the second embodiment, a direct potential drop using the NMOSs 55-1 and 56 is performed, and a higher speed operation is possible.

  Further, since the NMOSs 53 and 54 are used only for maintaining the potential after the potential is completely lowered, the size of the NMOSs 53 and 54 can be reduced as compared with the conventional level shift circuit of FIG. As an example of simulation, in the conventional level shift circuit of FIG. 15, the NMOSs 13 and 14, which required a gate width of 300 μm, are about 10 μm in the NMOSs 53 and 54 of the second embodiment.

  FIG. 8 is a current waveform diagram showing an outline of a simulation result comparing the through current between the level shift circuit of the first embodiment and the level shift circuit of the second embodiment. The horizontal axis represents time and the vertical axis represents time. Currents (Currents).

  As is apparent from FIG. 8, the peak of the through current is increased in the second embodiment, but the switching time becomes very short, and the result of integration is comparable to that of the first embodiment.

(Configuration of Example 3)
FIG. 9 is a circuit diagram of the VDD1-GND circuit in the level shift circuit showing the third embodiment of the present invention. Elements common to those in FIG. 5 showing the second embodiment are denoted by common reference numerals. Yes.

  In the level shift circuit of the third embodiment, a VDD1-GND circuit 20-2 having a different configuration is provided in place of the VDD1-GND circuit 20-1 of the second embodiment. The VDD1-GND circuit 20-2 is a circuit that outputs the input signal IN as it is as the first signal A, and delays the first input signal IN by a predetermined delay time τD to generate the second input signal IN2. Delay means (for example, delay element) 21 for outputting, inverter 26-4 for inverting first input signal IN (first signal A) and outputting second signal B, and first input signal IN , Inverter 26-2 for inverting the second input signal IN2, and output C of the output signal of the inverter 26-1 and the second input signal IN2 is obtained and the signal C is output. A NOR gate 24 having two inputs, an inverter 25 that inverts the signal C and outputs a signal CB, a negative OR of the first input signal IN and the output signal of the inverter 26-2, and outputs a signal D 2 An input NOR gate 27 and an inverter 26-3 for inverting the signal D and outputting the signal DB It is comprised by.

  In the third embodiment, only the timings of the first and second signals A and B are changed, and other configurations are the same as those in the second embodiment.

(Operation of Example 3)
FIG. 10 is a diagram showing an outline of the time chart of the level shift operation of FIG. 9, where the horizontal axis represents time and the vertical axis represents the logic level (potential). FIG. 11 is a voltage waveform diagram schematically showing a simulation result of the level shift operation of FIG. 9, where the horizontal axis represents time (Time) and the vertical axis represents potential (Voltages).

  The overall operation is almost the same as that of the second embodiment, but in the level shift circuit of the second embodiment, the timings at which the NMOSs 53 and 54 are turned on are shifted by the delay time τD by the first and second signals A and B. However, in the level shift circuit of the third embodiment, the third and fourth signals C3 and D4 are changed to be turned on simultaneously with the NMOSs 55-1 and 56.

(Effect of Example 3)
FIG. 12 is a current waveform diagram showing an outline of a simulation result in which the through current is compared between the level shift circuit of the second embodiment and the level shift circuit of the third embodiment. Currents (Currents).

  As is apparent from FIG. 12, in the third embodiment, the NMOS 53 and 54 are turned on simultaneously with the rise and fall of the input signal IN, so that the through current is slightly increased as compared with the second embodiment. In the signal generation circuit of the VDD1-GND system circuit 20-2, the number can be reduced from the AND gate 22 and the NOR gate 23 in FIG. 5 to one inverter 26-4.

  FIG. 13 is a circuit diagram of the VDD1-GND system circuit in the level shift circuit showing the fourth embodiment of the present invention, and common to the elements in FIGS. 5 and 9 showing the second and third embodiments. The code | symbol is attached | subjected.

  The VDD1-GND circuit 20-3 of the fourth embodiment includes a delay means (for example, a delay element) 21 that delays the first input signal IN by a predetermined delay time τD and outputs the second input signal IN2. , A logical AND of the first and second input signals IN and IN2, and a negative input of the two-input AND gate 22 that outputs the first signal A and the first and second input signals IN and IN2. A two-input NOR gate 23 that outputs the second signal B in search, an inverter 26-5 that inverts the second input signal IN1, an inverter 26-6 that inverts the first input signal IN, and a first A 2-input NAND gate 28 for obtaining a negative logical product of the input signal IN and the output signal of the inverter 26-5 and outputting the signal CB, an inverter 26-7 for inverting the signal CB and outputting the signal C, A 2-input NAND gate 2 for obtaining a negative logical product of the output signal of the inverter 26-6 and the second input signal IN1 and outputting the signal DB 9 and an inverter 26-8 that inverts the signal DB and outputs the signal D.

  In the fourth embodiment, the combinational logic of the NOR gates 24 and 27 and the inverters 25 and 26-3 that generate the signals C and D in the second and third embodiments is the same as the NAND gates 28 and 29 and the inverters 26-7 and 26-8. The combinational logic is changed to the above-described combinational logic, so that substantially the same effect as in the second and third embodiments can be obtained.

  FIGS. 14A and 14B are configuration diagrams of delay means in the level shift circuit showing the fifth embodiment of the present invention. FIG. 14A is a circuit diagram of the delay means, and FIG. It is a figure which shows the outline of the time chart of a signal, A horizontal axis is time and a vertical axis | shaft is a logic level (electric potential).

  In the first to fourth embodiments, the delay element 21 is used to form the delay time τD for the first input signal IN. However, in the fifth embodiment, a flip-flop circuit (hereinafter referred to as “FF”) is used as another delay means. .) 21-1 is used. When the input signal IN changes accompanying a certain clock signal CLK, as shown in FIG. 14B, the clock signal CLK is only one clock (or necessary clock) by the FF 21-1. The delay time τD can be formed by shifting.

  The present invention is not limited to the illustrated first to fifth embodiments, and various modifications and usage forms are possible. Examples of such modifications and usage forms include the following (A) and (B).

  (A) In the transistors constituting the level shift circuit, even if the NMOS is changed to PMOS and the PMOS is changed to NMOS, and the polarity of the power supply potential is reversed, the same operation and effect as in the embodiment can be obtained. For example, in the main level shift unit 50 of FIG. 1, the power supply potential VDD2 is replaced with a negative power supply potential, the ground potential GND is replaced with a positive power supply potential, the PMOSs 51 and 52 are replaced with NMOS, and the NMOSs 53 and 54 are replaced with PMOS. Even if the power supply polarity of the VDD1-GND system circuit 20 and the simple level shift unit 40 and the conductivity type of the MOS transistor are changed, the same effect as the circuit of FIG. 1 can be obtained. Similarly, in the main level shift unit 50-1 of FIG. 5, the power supply potential VDD2 is set to the negative power supply potential, the ground potential GND is set to the positive power supply potential, the PMOSs 51 and 52 are set to NMOS, and the NMOSs 53, 54, 55-1, and 56 are set. Even if the power supply polarity of the VDD1-GND system circuit 20-1 and the simple level shift unit 40 and the conductivity type of the MOS transistor are changed correspondingly to the PMOS, the same effect as the circuit of FIG. Is obtained.

  (B) The MOS transistor constituting the level shift circuit may be replaced with another transistor such as a bipolar transistor, or the signal generation circuit may be changed to a circuit configuration other than that illustrated.

1 is a circuit diagram of a level shift circuit showing a first embodiment of the present invention. FIG. It is a figure which shows the outline of the time chart of the level shift operation | movement of FIG. It is a voltage waveform diagram which shows the outline of the simulation result of the level shift operation | movement of FIG. FIG. 16 is a current waveform diagram showing an outline of a simulation result in which through current is compared between the conventional level shift circuit of FIG. 15 and the level shift circuit of the first embodiment. It is a circuit diagram of the level shift circuit which shows Example 2 of this invention. It is a figure which shows the outline of the time chart of the level shift operation | movement of FIG. FIG. 6 is a voltage waveform diagram showing an outline of a simulation result of the level shift operation of FIG. 5. It is a current waveform diagram which shows the outline of the simulation result which compared the through current with the level shift circuit of Example 1 of this invention and the level shift circuit of Example 2. FIG. It is a circuit diagram of the VDD1-GND system circuit in the level shift circuit which shows Example 3 of this invention. It is a figure which shows the outline of the time chart of the level shift operation | movement of FIG. FIG. 10 is a voltage waveform diagram showing an outline of a simulation result of the level shift operation of FIG. 9. It is a current waveform diagram which shows the outline of the simulation result which compared the through current with the level shift circuit of Example 2 of this invention, and the level shift circuit of this Example 3. FIG. It is a circuit diagram of the VDD1-GND system circuit in the level shift circuit which shows Example 4 of this invention. It is a block diagram of the delay means in the level shift circuit which shows Example 5 of this invention. It is a circuit diagram which shows an example of the conventional level shift circuit. FIG. 16 is a voltage waveform diagram showing a simulation result of the level shift operation of FIG. 15.

Explanation of symbols

20, 20-1, 20-2, 20-3 VDD1-GND system circuit 30, 30-1 VDD2-GND system circuit 40, 40-1 Simple level shift unit 50, 50-1 Main level shift unit 51, 52 PMOS
53, 54, 55, 55-1, 56 NMOS

Claims (7)

A first transistor connected between a first power supply potential and a first output node and turned on by a first potential of a second output node that outputs an output signal and turned off by a second potential When,
A second transistor connected between the first power supply potential and the second node, and turned on by the first potential of the first node and turned off by a second potential;
A third transistor connected between the first output node and a second power supply potential, and turned off by the first potential of the first signal and turned on by the second potential;
A fourth transistor connected between the second output node and the second power supply potential, and turned off by the first potential of a second signal and turned on by the second potential;
A fifth transistor connected between the first output node and the second output node and turned off by the first potential of a third signal and turned on by the second potential;
A first input signal that changes to a first logic level and a second logic level, and a delay of a predetermined delay time from the change of the first input signal, the first logic level and the second logic level And when the second input signal changes to the second logic level, the second input signal changes to the second logic level, and the first input signal changes to the first input signal. The first signal that changes to the first logic level when changing to a logic level, and the first signal that changes to the second logic level when the first input signal changes to the second logic level; When the input signal changes to the first logic level, the second signal changes to the second logic level, and when the second signal changes to the first logic level, during the delay time, The second potential, and the first signal is During the delay time changes to a logic level of 1, a signal generating circuit for generating said third signal to be the second potential,
A level shift circuit comprising: A first transistor connected between a first power supply potential and a first output node and turned on by a first potential of a second output node that outputs an output signal and turned off by a second potential When,
A second transistor connected between the first power supply potential and the second node, and turned on by the first potential of the first node and turned off by a second potential;
A third transistor connected between the first output node and a second power supply potential, and turned off by the first potential of the first signal and turned on by the second potential;
A fourth transistor connected between the second output node and the second power supply potential, and turned off by the first potential of a second signal and turned on by the second potential;
A fifth transistor connected in parallel with the third transistor and turned off by the first potential of a third signal, and turned on by the second potential;
A sixth transistor connected in parallel with the fourth transistor and turned off by the first potential of a fourth signal and turned on by the second potential;
A first input signal that changes to a first logic level and a second logic level, and a delay of a predetermined delay time from the change of the first input signal, the first logic level and the second logic level And when the second input signal changes to the second logic level, the second input signal changes to the second logic level, and the first input signal changes to the first input signal. The first signal that changes to the first logic level when changing to a logic level, and the first signal that changes to the second logic level when the first input signal changes to the second logic level; When the first input signal changes to the first logic level, the second signal changes to the second logic level, and when the first input signal changes to the second logic level, during the delay time The third signal at the second potential; Serial between the delay time the first input signal is changed to the first logic level, and a signal generating circuit for generating said fourth signal which becomes the second potential,
A level shift circuit comprising: A first transistor connected between a first power supply potential and a first output node and turned on by a first potential of a second output node that outputs an output signal and turned off by a second potential When,
A second transistor connected between the first power supply potential and the second node, and turned on by the first potential of the first node and turned off by a second potential;
A third transistor connected between the first output node and a second power supply potential, and turned off by the first potential of the first signal and turned on by the second potential;
A fourth transistor connected between the second output node and the second power supply potential, and turned off by the first potential of a second signal and turned on by the second potential;
A fifth transistor connected in parallel with the third transistor and turned off by the first potential of a third signal, and turned on by the second potential;
A sixth transistor connected in parallel with the fourth transistor and turned off by the first potential of a fourth signal and turned on by the second potential;
A first signal similar to a first input signal that changes to a first logic level and a second logic level; the second signal having a phase opposite to the first signal; and the first signal And the second input signal that changes to the first logic level and the second logic level after being delayed by a predetermined delay time from the change of the first input signal. The third signal that becomes the second potential during the delay time when the input signal changes to the second logic level, and the delay when the first input signal changes to the first logic level. A signal generating circuit for generating the fourth signal at the second potential for a time;
A level shift circuit comprising:   The first and second transistors are composed of complementary first conductivity type and second conductivity type MOS transistors of the first conductivity type, and the third, fourth, and fifth transistors are 2. The level shift circuit according to claim 1, wherein the level shift circuit is composed of the second conductivity type MOS transistor.   The first and second transistors are composed of complementary first conductivity type and second conductivity type MOS transistors of the first conductivity type, and the third, fourth, fifth, and sixth transistors. 4. The level shift circuit according to claim 2, wherein the transistor is composed of the second conductivity type MOS transistor.   6. The level shift circuit according to claim 1, wherein the second input signal is generated by a delay element that delays the first input signal by the delay time.   The second input signal is generated by a flip-flop circuit that takes in the first input signal in synchronization with a clock signal and outputs the first input signal after delaying the delay time. Item 6. The level shift circuit according to any one of Items 1 to 5.

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