JP4878050B2 - Computer and control method - Google Patents

Description

The present invention relates to a shared memory multiprocessor computer having a plurality of processors having a cache memory and a control method, and more particularly to a computer and a control for improving the instruction execution efficiency of a spin wait instruction used for synchronous processing and the like. Regarding the method.

  Conventionally, in a shared memory multiprocessor system in which a main memory is shared by a plurality of processors having a cache memory, spin weights are often used for synchronization processing between the processors.

A typical example of using a spin weight for synchronization processing between processors is spin lock. Spin lock command processing is often realized by the procedure of the verification unit 100 and the setting unit 102 as shown in FIG. The verification unit 100 determines whether or not the process or thread that has reached the lock acquisition point loads the variable X in step S1 and the variable X is a value indicating that lock acquisition is possible, for example, X = 0 in step S2. , The spin wait is performed by performing the spin to repeat the processing of steps S1 and S2 until X = 0. The setting unit 102
Using an interlock instruction such as “test_and_set” or “compare_and_jump”, the lock variable value X is set to X = 1 in step S3, and the spin lock process is exited.

  If the setting of the lock variable value X = 1 fails, the process returns to the verification unit 100 and continues the spin wait. As described above, the spin weight is often used in the spin lock verification unit 100 that checks whether the lock can be acquired.

  Other than spin lock, there is barrier synchronization using spin wait for synchronization processing between processors in a shared memory multiprocessor system. Barrier synchronization means that a process or thread to be synchronized waits at a synchronization point. In the case of memory-based barrier synchronization, it is often realized by the procedure of FIG.

  First, in step S1 of the setting unit 104, the lock variable X is X = 0 before the process or thread reaches the synchronization point. When the synchronization point is reached, the process or thread sets the bit of the lock variable X corresponding to the corresponding process or thread to 1 using an interlock instruction such as “test_and_set” or “compare_and_jump”, and proceeds to the verification unit 106.

The verification unit 106 loads the lock variable X in step S2, and spins and waits until all process or thread bits subject to barrier synchronization become 1 in step S3, that is, all X = 1. Do weights. When all processes or all threads reach the synchronization point, all X = 1, and in a synchronized state, the process exits the spin wait state and proceeds to the next processing.

  As described above, even in the barrier synchronization, the spin weight is often used in the verification unit 106 that checks whether all processes or all threads have reached the synchronization point.

  Also, spin waits are used for synchronization with I / O devices (input / output devices). In normal I / O processing, an interrupt is generally used for synchronization between a processor and an I / O device. This is because the I / O device is very slow compared to the processor, and the loss that the processor keeps waiting for a response from the I / O device is large.

However, due to the speeding up of I / O devices, some I / O devices have a problem due to the use of interrupts. In general, since an interrupt has a large overhead (delay), the original speed of the I / O device cannot be utilized. For this reason, some high-speed I / O devices have begun to employ synchronization processing based on spin waits.

Using Spin-Loop on IntelPentium (R) Processor and Intel XenoProcessor Version 2.1 [Online], USA, Intel Corp. , May 2001 pp. 1-11

  However, the execution of spin wait is wasteful. In the spin wait, the execution of the same instruction sequence is repeated until the variable value serving as the wait end condition is changed to a desired value by another agent such as another processor or an I / O device. The number of spins, which is the number of repetitions, is rarely in the range of several hundreds or thousands, and it can be said that the processor is wasted in a sense. From the viewpoint of power consumption, the power is wasted during the spin weight.

Also, SMT (Simultaneous) that allows simultaneous execution of multiple threads
In a multi-threading architecture (processor), a thread that is executing a spin wait may interfere with another execution thread. Generally, in the SMT processor, processor resources are shared among threads. In general, the processor resources are not allocated evenly for each execution thread, but the number and amount of processor resources to be allocated vary according to the state of each thread. Various methods have been proposed as criteria for determining processor resource allocation. For example, there are the following approaches.

(1) Reduce resource allocation to the thread that caused the cache miss;
(2) Reduce resource allocation to threads with a large number of speculatively executing instructions;
(3) Reduce resource allocation to threads with a large number of instructions registered in the reservation station;
These approaches are based on the idea of preferentially allocating processor resources to threads that are likely to execute instructions more smoothly. Here spin weights can execute instructions very smoothly. This is because only the execution of the same instruction sequence is repeated, so that no cache miss occurs and branch prediction is not missed.

  Therefore, in the SMT processor, processor resources are preferentially allocated without regard to the thread that is executing the spin wait. Then, as compared with a thread that is executing a spin wait, the allocation of processor resources to other threads that are considered to execute a highly productive instruction sequence may be reduced, resulting in a decrease in processor performance.

In this way, the spin weight (1) wastes power.
(2) SMT processor performance is likely to be degraded;
There is a problem.

  As a countermeasure against this problem, there is a method of stopping execution of the spin wait when it is detected that the spin wait has started, and notifying by an interrupt when the condition for exiting from the spin wait is satisfied, and restarting the execution. However, if the conditions for exiting the spin wait are in place, there is no origin or child if it is notified by an interrupt. In the first place, spin wait is used to achieve low delay, and using interrupts increases the time cost.

  There is also a method of providing hardware dedicated for synchronization. However, in that case, the hardware cost becomes high. Currently, memory-based synchronization processing is common, and there is a historical background that there is a great merit in cost reduction by performing synchronization processing using a general-purpose device (memory).

It is an object of the present invention to provide a computer and a control method that increase the efficiency of instruction execution by eliminating the waste of power and processor resources caused by the execution of spin waits.

  In the present invention, in a computer having a plurality of processors having a cache memory, when it is detected that a spin wait instruction is being executed by the processor, monitoring of a variable value that is a spin wait termination condition is instructed. The spin weight detection unit that changes the operation state and the variable value instructed by the spin weight detection unit are monitored, and when the change of the variable value is detected, the processor is notified of the value change and the operation state is recovered. And a value change detecting unit for returning to (2).

  As described above, the present invention reduces waste caused during the execution of the spin wait by changing the operating state of the processor when there is no possibility of being able to escape from the spin wait or when the possibility is low. In addition, according to the present invention, there is no possibility that the spin wait is completed or low due to the addition of a small amount of hardware such as providing the processor with a spin weight detection unit and providing a cache memory with a value change detection unit. And improving the instruction execution efficiency of the processor without impairing the feature of low delay of the spin wait.

  When the spin wait detection unit detects that the processor is executing a spin wait instruction, the spin wait detection unit instructs the value change detection unit to monitor the cache block of the cache memory in which the variable value referenced in the execution of the spin wait instruction is stored. To do. The value change detection unit notifies the processor of a value change when it is detected that the state of the cache block has been invalidated by another processor or the input / output unit. The change detection unit also notifies the processor of a value change when it is detected that the cache block has been evicted from the cache memory.

  When the spin wait detection unit detects that the processor is executing the spin wait instruction, the value change detection unit monitors the bus request for the memory address in which the variable value referenced in the execution of the spin wait instruction is stored. Instruct. The value change detection unit monitors the bus request for the memory address in which the variable value instructed from the spin weight detection unit is stored, and when the bus request for the memory address is detected from another processor or input / output unit, Notify the processor of the value change.

  When the processor has at least two operation modes of the normal mode and the low power consumption mode, the spin wait detection unit sets the operation mode of the processor to the low power consumption mode when detecting that the spin wait instruction is being executed. change. Further, the value change detection unit changes the operation mode of the processor to the normal mode when detecting the change of the variable value which is the spin wait termination condition. As a result, the power consumption of the processor can be reduced during the execution of the spin wait.

  When the processor has a function of stopping the program execution, the spin wait detection unit causes the processor to stop executing the program when detecting that the spin wait instruction is being executed. The value change detection unit causes the processor to resume execution of the program when detecting the change of the variable value which is the spin wait termination condition. As a result, the execution of the program is stopped during the spin wait execution, and accordingly, the power consumption of the processor can be reduced.

  When the processor has a structure (SMT processor) capable of executing a plurality of threads at the same time, when the spin weight detection unit detects a thread that is executing a spin wait instruction, the processor decreases the allocation of processor resources to the thread or Stop. Further, the value change detection unit increases or restarts the allocation of the processor resource to the thread when detecting the change of the variable value which is the spin wait termination condition.

  As a result, the execution of other thread programs is stopped during the spin wait execution of the thread in the SMP processor, the adverse effect on the other threads by the spin wait execution thread is avoided, and as a result, the performance of the processor is improved.

  The processor has a spin wait dedicated instruction, and the spin wait detection unit detects that the spin wait is being executed from the execution of the spin wait dedicated instruction by the processor. The spin wait detection unit compares the instruction sequence by comparing the buffer that stores the executed instruction sequence by the processor, the instruction sequence recording unit that records the instruction sequence of the dedicated spin wait instruction, and the buffer and instruction sequence recording unit. And a comparison unit for detecting that the spin wait is being executed.

The present invention provides a method for controlling a computer having a plurality of processors having a cache memory,
When the execution of the spin wait instruction by the processor is detected, change the operating state of the processor after monitoring the variable value that is the end condition of the spin wait,
When it is detected that a variable value has been changed during monitoring, the processor is notified of the value change and the operation state is restored.
The details of this control method are basically the same as in the case of a computer.

  According to the present invention, it is possible to limit useless instruction execution and processor operation generated by spin wait instruction execution without sacrificing the low delay characteristic of spin wait, and as a result, the processor Power consumption can be saved.

Further, in the SMT processor, it is possible to avoid an adverse effect on other threads by the spin wait execution thread, and it is possible to improve the processing capability of the SMT processor.

  FIG. 3 is a block diagram of a shared memory multiprocessor system to which the present invention is applied. In FIG. 3, the multiprocessor system includes, for example, four processors 10-1 to 10-4, and cache memories 12-1 to 12-4 are provided for the processors 10-1 to 10-4. .

  The cache memories 12-1 to 12-4 are connected to the main memory 16 used as a shared memory via the bus 14. An input / output unit 18 is connected to the bus 14. The input / output unit 18 is, for example, an input / output processor that functions as an input / output agent, and includes subsystems such as an external hard disk drive HDD, a network, a keyboard, and a mouse. Input / output devices such as displays are connected.

  FIG. 4 is an embodiment of the processor 10-1 of FIG. The other processors 10-2 to 10-4 are also the same embodiment. In FIG. 4, the processor 10-1 includes a processor core 11 and a cache memory interface 20. The cache memory 12-1 includes a processor interface 24, a cache memory control unit 26, a bus interface 28, and a cache memory array 30.

  The configurations of the processor 10-1 and the cache memory 12-1 are the same as those of the conventional processor. However, in the present invention, a spin weight detection unit 22 is newly provided on the processor 10-1 side, and at the same time, the cache memory A value change detection unit 32 is provided on the 12-1 side. When the spin wait detection unit 22 provided in the processor 10-1 detects that the processor core 11 is executing the spin wait instruction, the spin wait detection unit 22 monitors the variable value that is the spin wait termination condition. After instructing the value change detector 32 provided on the side, the operating state of the processor 10-1 is changed.

  The change of the operation state of the processor 10-1 by the spin wait detection unit 22 is a change to an operation state that reduces waste generated during execution of the spin wait instruction, and is specifically as follows.

  For example, when the processor 10-1 has at least two operation modes of a normal mode and a low power consumption mode, when the spin wait detection unit 22 detects that the spin wait instruction is being executed, the processor operation mode is changed. Change to low power consumption mode.

  Further, when the processor has a function of stopping the program execution, when the spin wait detection unit 22 detects that the spin wait instruction is being executed, the processor stops the execution of the program. Either the change to the low power consumption mode or the stop of the program execution when the execution of the spin wait instruction is detected, the execution of the spin wait instruction sequence is continued until the end condition of the spin wait is changed to a predetermined value. The spin which repeats is used to prevent wasteful operation of the processor and wasteful power consumption. Of course, it can be said that the execution stop of the program by the processor when the spin wait instruction is detected is included in one form of the low power consumption mode.

  The value change detection unit 32 provided on the cache memory 12-1 side monitors a variable value that is a spin weight end condition instructed by the spin weight detection unit 22, and this variable value is the other processor 10-2. 10-4 or when the input / output unit 18 detects that the processor 10-1 has changed, the processor 10-1 is notified of the value change, and the operating state of the processor is restored.

  For example, if the processor is changed to the low power consumption mode upon detection during execution of the spin wait instruction, the normal mode is restored. When the execution of the spin wait instruction is detected and the execution of the program of the processor is stopped, the execution of the program is resumed.

  FIG. 5 is an embodiment of the spin weight detector 22 provided in the processor 10-1 of FIG. The spin wait detection unit 22 includes an executed instruction sequence buffer 34, a spin wait instruction sequence recording unit 36, and a comparison unit 38. In this embodiment, a case where an existing instruction set ISA (Instruction Set Architecture) is used as it is is taken as an example. The spin wait detection unit 22 first records in advance a command sequence indicating a spin wait in the spin wait command sequence recording unit 36.

  There may be a plurality of records of this instruction sequence, and the recorded contents may be predetermined. In the executed instruction sequence buffer 34, an instruction sequence that has been executed by the processor core is recorded. The comparison unit 38 compares the reference instruction sequence recorded in the spinwait instruction sequence recording unit 36 with the instruction sequence recorded in the executed instruction sequence buffer 34, and if the two match, that is, the spinwait instruction sequence is executed. If it is detected, a spin wait instruction string detection signal E1 is output to the cache memory interface 20.

  FIG. 6 shows an embodiment of the value change detection unit 32 provided on the cache memory 12-1 side in FIG. In this embodiment, the value change detection unit 32 includes a monitoring target recording unit 40 and a cache state monitoring unit 42. When the spin wait is started by the execution of the spin wait instruction in the processor, the spin wait instruction sequence detection signal E1 is output from the spin wait detection unit 22 shown in FIG. 5, and the monitoring target provided in the value change detection unit 32 in FIG. A cache block storing a variable value referred to as an end condition of the spin wait in the address recording unit 40, specifically, a cache memory entry is received via the cache memory control unit 26 and recorded.

  The cache state monitoring unit 42 monitors the cache memory entry recorded in the monitoring target address recording unit 40, and when the cache state (cache state) of this entry is updated, the cache state monitoring unit 42 sends it to the processor side via the cache memory control unit 26. A value change detection signal E2 is output.

  In this embodiment, the MESI protocol is taken as an example of the cache protocol. In this case, the cache state monitoring unit 42 outputs the value change detection signal E2 when the cache state of the entry to be monitored is updated to invalid I. The cache state monitoring unit 42 outputs the value change detection signal E2 from the update of the invalid I of the cache state corresponding to the rewriting of the variable value which is the spin wait end condition. However, the cache state monitoring unit 42 uses the LRU algorithm of the cache memory. The value change detection signal E2 is also output when the cache memory entry to be monitored is evicted.

  FIG. 7 is a time chart of the processing procedure of the present invention for detecting a value change by monitoring a cache memory entry (cache block) that stores a variable value that is a spin wait termination condition when detecting a spin wait. First, the spin wait detection unit 22 checks in step S1 whether or not the processor 10-1 is executing a spin wait instruction.

  When the processor 10-1 executes the spin wait instruction, the spin wait detection unit 22 as shown in the embodiment of FIG. 5 detects the execution of the spin wait instruction and outputs the spin wait instruction detection signal E1. Accordingly, in step S2, the spin weight detection unit 22 instructs the value change detection unit 32 on the cache memory 12-1 side to monitor the cache block in which the variable value referred to by the spin weight is stored. At the same time, the spin wait detection unit 22 stops the execution of the spin wait instruction by the processor 10-1 in step S3, and enters an operation state of low power consumption.

  The value change detection unit 32 instructed to monitor the cache block from the spin weight detection unit 22 starts monitoring the cache block instructed by the processor in step S101. That is, in step S102, it is detected whether the cache state in the cache block to be monitored, that is, the state change of the cache state, specifically, whether or not invalidation has been performed. If a cache block is updated by any of the other processors 10-1 to 10-4 or the input / output unit 18 in this state, the cache state of the monitored cache block is updated to an invalid state.

  When this is detected in step S102, the process proceeds to step S103, where the state change of the cache block is output as the value change detection signal E2 from the value change detection unit 30 in FIG. 6, and the state change of the cache block, that is, the invalidation is notified to the processor side. To do. Upon receiving this value change detection signal, the spin wait detection unit 22 resumes execution of the spin wait instruction by the processor 10-1 in step S4.

  FIG. 8 is an explanatory diagram showing the processing procedure of the present invention taking barrier synchronization processing in a multiprocessor system as an example. FIG. 8A shows a part of the multiprocessor system that is the target of the barrier synchronization processing, and the barrier synchronization processing of the two processors 10-1 and 10-2 is taken as an example to simplify the description.

  Further, in the cache memories 12-1 and 12-2 provided in the processors 10-1 and 10-2, a 2-bit variable value which is a termination condition of the spin wait referred to in the execution of the spin wait instruction And the cache state in the cache block.

  Since this cache state corresponds to the MESI protocol and the variable value is barrier synchronization of the two processors 10-1 and 10-2, it is 2-bit information corresponding to each and reaches the synchronization point. In the previous state, it is “00”.

  FIGS. 8B to 8G show the transition states of the barrier synchronization processing operation according to the processing procedure of the present invention shown in FIG. FIG. 8B shows a state in which the processor 10-1 reaches the synchronization point and spin-waits out of the two processors 10-1 and 10-2 that are subject to barrier synchronization.

  That is, the processor 10-1 sets its own corresponding bit in the variable value of the target entry of the cache memory 12-1 by the processing of the setting unit 104 shown in FIG. The variable value is “00” to “01”. When updating the variable value of the cache memory 12-1, the cache state is invalidated in the cache memory 12-2 of the processor 10-2 having the same cache block. In the cache memory 12-1, the cache state of the corresponding cache block is updated to the change M.

  When the processor 10-1 enters the spin wait state as shown in FIG. 8B, the spin wait detection unit 22 provided in the processor 10-1 detects that the spin wait instruction is being executed as shown in FIG. The memory 12-1 is instructed to monitor whether or not the cache state of the corresponding cache block becomes invalid I. At the same time, for example, the spin-wait program execution is stopped for the processor 10-1. As a result, as shown in FIG. 8C, the processor 10-1 is stopped from executing the spin-wait program, while the processor 10-2 continues to execute the program in the normal mode.

  FIG. 8D shows processing when the processor 10-2 reaches the synchronization point. When the processor 10-2 reaches the synchronization point, a variable value serving as a spin wait end condition is read from the cache memory 12-2 by executing the spin wait instruction. At this time, since the corresponding cache block of the cache memory 12-2 is in the invalid I state, the processor 10 reads the variable value from the cache memory 12-2 of the processor 10-1 by the cache protocol and sets the cache state to the shared S state. Read with -2.

  Subsequently, as shown in FIG. 8E, the processor 10-2 sets the variable value to “11” by rewriting the bit assigned to itself to 1. By updating the variable value, the variable value is invalidated for the cache memory 12-1 of the processor 10-1 in which the program execution is stopped, and the cache state is updated from the shared S so far to invalid I. When the state change to invalid I in the cache memory 12-1 is detected by the value change detection unit 32 provided on the cache memory 12-1 side in FIG. 4, a value change notification is sent to the processor 10-1, thereby The execution of the program that has been stopped is resumed.

  For this reason, the processor 10-1 that has resumed execution of the program reads the variable value “11” of the corresponding cache block in the cache memory 12-1 by executing the spin wait instruction in FIG. Recognize that the condition is met.

  At this time, even on the processor 12-2 side, the spin wait end condition is determined by recognizing the variable value “11”, whereby the barrier synchronization of the two processors 10-1 and 10-2 is taken. As shown in FIG. 8G, the spin wait is ended and the next program execution process is started.

  FIG. 9 shows another embodiment of the value change detection unit 32 provided on the cache memory 12-1 side of FIG. 4, and in this embodiment, variable values that are conditions for ending spin wait are stored. It is characterized in that a value change is detected by monitoring a bus transaction (bus request) for changing a variable value by another processor or an input / output unit for the cache block being operated.

  The value change detection unit 32 in FIG. 9 is provided with a bus transaction monitoring unit 44 for the same monitoring target address recording unit 40 as in FIG. When execution of the spin wait instruction is started on the processor side, the data address referred to by the spin wait is recorded in the monitoring target address recording unit 40.

  The bus transaction monitoring unit 44 monitors a transaction on the bus 14 from another processor or an input / output unit with respect to the monitoring target address via the bus interface 28. When the monitored bus transaction is detected, a value change detection is performed. The signal E2 is output to the processor side via the cache memory control unit 26. This value change detection by monitoring the bus transaction does not directly detect the change of the variable value that is the end condition of the spin wait, but accurately detects that the variable value may be changed. I can say.

  FIG. 10 is a time chart of the processing procedure of the present invention when a value change is detected by monitoring the bus transaction of FIG. When the spin wait detection unit 22 detects that the processor is executing the spin wait instruction in step S1, the spin wait detection unit 22 monitors the cache block in which the variable value referred to by the spin wait instruction is stored, that is, the data address in step S2. An instruction is given to the value change detection unit 32 on the cache memory side.

  In step S3, the spin wait detection unit 22 outputs execution of spin wait instruction sequence detection to the processor, and stops execution of the spin wait instruction by the processor.

  The value change detection unit 32 on the cache memory side monitors the bus transaction for the data address instructed from the processor side in step S101, and if the bus transaction for the cache block to be monitored is detected in step S102, in step S103. A change in state (possibility) due to a bus transaction is notified to the processor by outputting a value change detection signal. In response to this, the spin wait detection unit 22 resumes execution of the spin wait instruction by the processor in step S4.

  Next, another embodiment of the present invention that reduces the allocation of processor resources to a processor that is executing a spinwait instruction will be described in the case where an SMT processor is used as the processors 10-1 to 10-4 in FIG.

  FIG. 11 is a schematic configuration of an SMT processor to which the present invention is applied. The SMT processor includes instruction pointers 46-1, 46-2, fetch / decode 48-1, 48-2, execution unit 50, retirement unit 52, primary instruction cache unit 54, primary data cache unit 56 and secondary. A cache unit 58 is provided. The SMT processor having such a schematic configuration usually has a plurality of instruction pointers for simultaneously executing a plurality of threads. In this example, the case of having two instruction pointers 46-1 and 46-2 is shown. .

  In the execution of the two threads realized by the instruction pointers 46-1, 46-2 and the fetch / decode 48-1, 48-2, resources such as the execution unit 50 are shared between the threads. The effective utilization rate of resources is increased, and this is the aim of the SMT processor. In this manner, in the SMT processor that shares processor resources among a plurality of threads, various policies for determining which thread's instruction is assigned to the execution unit 50 are proposed.

Therefore, the present invention can be used to determine a policy for determining which thread's instruction a processor resource such as an execution unit is allocated to. Specifically, when a thread that is executing a spinwait instruction is detected, the allocation of processor resources such as execution units to the thread that is executing the spinwait instruction is reduced or stopped.
As a result, an opportunity to assign an instruction of another thread that is executing a more meaningful instruction that is not a spin wait to an execution unit increases, and as a result, an improvement in processing performance of the SMT processor can be expected.

  FIG. 12 is a time chart of the processing procedure of the present invention for detecting processor weights and reducing processor resources for an SMT processor. The spin weight detection unit 22 on the SMT processor side checks whether or not a spin wait is being executed by a thread in a plurality of threads in step S1, and if the execution is detected, the process proceeds to step S2 and is referenced by the spin wait. The cache memory side value change detection unit 32 is instructed to monitor the cache block in which the variable value being stored is stored.

  In step S3, the processor resource to which the instruction of the thread executing the spinwait instruction is allocated is reduced or stopped. Specifically, for example, when the execution of the spin wait is detected in the instruction of the thread executed on the instruction pointer 46-1 and the fetch / decode 48-1 side, the instruction is allocated to the execution unit 50 by this thread. The execution unit 50 is allocated to the instructions of the other thread on the side of the instruction pointer 46-2 and the fetch / decode 48-2 that are executing the instructions other than the spin wait instruction.

  The value change detection unit 32 on the cache memory side monitors the cache state of the cache block instructed from the processor side in step S101, and detects that the cache state, that is, the state is updated to invalid I in step S102. In step S103, the processor side is notified of the cache block state change.

  In response to this, on the spin wait detection unit 22 side, the reduction or stop of the allocation of the processor resources to the thread executing the spin wait instruction is canceled in step S4.

  In the above embodiment, the MESI protocol is taken as an example of the cache protocol, but an appropriate cache protocol may be used as long as the update includes invalid I. In the above embodiment, the cache state of the corresponding cache block is invalidated as the change value for the spin wait end condition, or the variable value that is the cache end condition is directly or directly from the bus transaction for this state. Although the monitoring is performed indirectly, it is a matter of course that other variable values may be directly or indirectly monitored.

  Further, in the above embodiment, as a change in the operation state of the processor when the execution of the spin wait is detected, the change to the low power consumption mode, the stop of the program execution, and the processor resource in the SMT processor However, any other change is possible as long as it is a change in the operating state of the processor that eliminates waste caused by the execution of an appropriate spin wait instruction.

The present invention is not limited to the above-described embodiments, and includes appropriate modifications that do not impair the advantages and objects thereof. Further, the present invention is not limited by the numerical values shown in the above embodiments.

Explanatory drawing of conventional spin lock processing Illustration of conventional barrier synchronization processing Book diagram of shared memory multiprocessor system to which the present invention is applied Block diagram of an embodiment of a processor according to the invention FIG. 4 is a block diagram of an embodiment of the spin weight detection unit in FIG. Block diagram of an embodiment of the value change detector in FIG. 4 that monitors cache blocks Time chart of processing procedure of the present invention for detecting a value change by monitoring a cache block at the time of detecting a spin wait Explanatory drawing of the synchronous processing by this invention 4 is a block diagram of another embodiment of the value change detection unit in FIG. 4 that monitors bus transactions. Time chart of the processing procedure of the present invention for detecting a value change by monitoring a bus transaction when detecting a spin wait according to the present invention 1 is a block diagram of a schematic configuration of an SMT processor to which the present invention is applied. Time chart of processing procedure of the present invention for detecting processor weight and detecting processor weight

Explanation of symbols

10: Cache memory interfaces 10-1 to 10-4: Processor 11: Processor cores 12-1 to 12-4: Cache memory 14: Bus 16: Main memory 18: Input / output unit 22: Spin wait detection unit 24: Processor interface 26: Cache memory control unit 28: Bus interface 30: Cache memory array 32: Value change detection unit 34: Completed instruction sequence buffer 36: Spin wait instruction sequence recording unit 38: Comparison unit 38
40: monitoring target recording unit 42: cache state monitoring unit 42
44: Bus transaction monitoring units 46-1, 46-2: Instruction pointers 48-1, 48-2: Fetch / decode 50: Execution unit 52: Retirement unit 54: Primary instruction cache unit 56: Primary data cache unit 58: Secondary cash unit

Claims (2)

A con pin Yuta having a processor and a cache memory,
The processor includes a spin weight detection unit,
The cache memory includes a value change detection unit,
The spin weight detection unit stores a variable value that is the end condition of the spin weight that is monitored by the spin weight process when it detects that the corresponding processor is executing the spin wait process. After instructing the value change detection unit to monitor the cache block, the spin wait process by the corresponding processor is stopped,
The value change detection unit monitors whether or not the variable value stored in the cache block is changed according to an instruction from the spin weight detection unit, and detects that the variable value is changed. Notifying the processor of the change of the variable value, and restarting the spin wait process by the processor ,
The processor has at least two operation modes of a normal mode and a low power consumption mode, and when the spin wait detection unit detects that a spin wait instruction is being executed, the processor changes the operation mode of the processor to the low power consumption mode. change, when the value change detecting unit which detects a change of the variable value that is the termination condition of spinwait, characterized Rukoto to change the operation mode of the processor in the normal mode, the computer.
In a method of controlling a computer having a processor with a cache memory,
Monitoring the execution of the spin wait by the processor;
When the execution of the spin wait by the processor is detected, monitoring of the variable value that is the end condition of the spin wait is started,
After starting monitoring the variable value, stop the spin wait that the processor is executing,
When it is detected that the variable value has been changed, the processor notifies the processor of the value change and restarts the spin wait process by the processor;
The processor has at least two operation modes of a normal mode and a low power consumption mode, and when the spin wait detection unit detects that a spin wait instruction is being executed, the processor changes the operation mode of the processor to the low power consumption mode. changed, when the value change detecting unit which detects a change of the variable value that is the termination condition of spinwait, control method of a computer, characterized in Rukoto to change the operation mode of the processor to the normal mode.

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