JP4954744B2 - Display device and electronic apparatus including the display device - Google Patents

Description

The present invention relates to a display device. In particular, the present invention relates to a display device including a correction circuit for complementing a phase shift accompanying a delay of a signal input to a wiring. The present invention also relates to an electronic device having the display device in a display portion.

In recent years, a display device in which a semiconductor thin film is formed on an insulator such as a glass substrate, in particular, an active matrix display device using a TFT (Thin Film Transistor) has become widespread. An active matrix display device using TFTs has hundreds of thousands to several millions of TFTs arranged in a matrix, and controls lighting or non-lighting of each pixel to display an image. Is going.

In such a display device, a TFT is arranged for each pixel, and lighting or non-lighting of each pixel is controlled by controlling on and off of those TFTs.

In the above-described display device, examples of driving methods for displaying a multi-tone image include an analog driving method (analog gradation method) and a digital driving method (digital gradation method).

The analog driving method is a method in which gradation is obtained by continuously controlling the magnitude of a current flowing through a light emitting element. The digital driving method is a method of driving only in two states of an ON state (lighted state) and an OFF state (non-lighted state) of the light emitting element.

Since the digital driving method can display only two gradations as it is, a combination with a driving method for displaying multiple gradations such as an area gradation method or a time gradation method has been proposed. The area gradation method is a method in which a sub-pixel is provided in a pixel and gradation display is performed according to the size of the light emission area. In addition, the time gray scale method is a driving method in which the multi-tone display is performed by controlling the length of the light emission period of the pixel and the number of times of light emission. Specifically, it is described in Patent Document 1 and Patent Document 2.
JP 2001-5426 A JP 2001-343933 A

FIG. 22A illustrates an example of an active matrix pixel circuit using a light-emitting element as a pixel. The circuit structure illustrated in FIG. 22A includes a writing transistor 2201 (also referred to as a first transistor), a driving transistor 2202 (also referred to as a second transistor), and a light-emitting element 2203. The gate of the writing transistor 2201 is connected to a gate line (also referred to as a gate signal line or a scanning line) GL, the first terminal is connected to a source line (also referred to as a source signal line or signal line) SL, and the second terminal is connected to It is connected to the gate of the driving transistor 2202. The driving transistor 2202 has a first terminal connected to the power supply line VL and a second terminal connected to the first terminal of the light emitting element 2203. A second terminal of the light emitting element 2203 is connected to the counter electrode.

Note that it is difficult to define a source electrode and a drain electrode because of the structure of a transistor, and thus, one of the source electrode and the drain electrode is referred to as a first terminal and the other of the source electrode and the drain electrode is referred to as a second terminal.

Next, the operation of the circuit in FIG. 22A will be described using the timing charts in FIGS. 22B and 22C. Here, the writing transistor 2201 is described as an N-channel transistor, and the driving transistor 2202 is described as a P-channel transistor. Then, the signal waveform of the potential of the node N _S source line SL, the signal waveforms for the potential of the node N _G of the gate line GL is described.

In FIG. 22 (B), the node _{N S} is a low potential of the signal (also referred to as a Low level) node _{N G} is a high potential of the signal (also referred to as a High level) at which if the node _{N S} potentials the driving transistor when the 2202 When the potential of VL is captured by the pixel, the light emitting element 2203 of the pixel emits light. Further, when the node N _S is the potential of the node N _G High node if a signal having a potential N _S when the high potential of the signal is taken to the gate of the driving transistor 2202, the potential of VL is not supplied to the light emitting element 2203 The light emitting element of the pixel is turned off.

However, the signal supplied to the pixel portion where the pixel of the display device is provided may be out of phase due to rounding or delay of the signal due to the resistance or capacitance component of the wiring to which the signal is supplied. FIG. 22C shows a timing chart when the phase of this signal is shifted.

Also in FIG. 22 (C), the potential of the node _{N G} captures the pixel potential of the node _{N S} when the High level. However, in FIG. 22 (C), when the potential of the node _{N G} is High level, the potential of the node _{N S} will rise falls from High level to Low level, or from the Low level to the High level. For this reason, normal display cannot be obtained in actual display, and there is a problem that a non-display part is displayed or a pixel to be displayed is not displayed.

The present invention detects a shift when the phase of two signals is shifted due to parasitic resistance or parasitic capacitance in a wiring for supplying a signal, and then repairs the shift of the signal phase inside the display device, It is an object to provide a display device capable of obtaining a normal display.

In order to solve the above-described problems, the present invention provides a phase comparison circuit for comparing whether or not two input signals have different phases, and the number of cases where the phase comparison circuit detects that the phase is shifted. And a phase shift that can shift the phase of one of the two signals and output a signal in which the phase deviation is repaired according to the degree of the phase deviation counted in the counter circuit It has a circuit. Hereinafter, a specific configuration of the present invention will be described.

One embodiment of the display device of the present invention includes a gate signal line, a source signal line, a phase comparison circuit that compares a signal output to the gate signal line and a potential of the signal output to the source signal line, and a phase comparison circuit A display comprising: a counter circuit that counts the number of output signals; and a phase shift circuit that shifts the phase of the signal output to the gate signal line based on the signal output from the counter circuit. Device.

Another display device of the present invention includes a gate signal line from which a first signal and a second signal are output, a source signal line from which a video signal is output, a phase of the first signal, and a video signal. And a phase comparison circuit that compares the phase of the second signal and the phase of the video signal, and a signal output from the phase comparison circuit, by comparing the phase of the first signal and the phase of the video signal In the signal output from the first counter circuit that counts the number of output signals and the phase comparison circuit, the signal output by counting the phase of the second signal and the phase of the video signal is counted. Based on the second counter circuit, the first phase shift circuit for shifting the phase of the first signal based on the signal output from the first counter circuit, and the signal output from the second counter circuit. There are a display device, characterized in that it comprises a second phase shift circuit for shifting the phase of the second signal.

The phase comparison circuit of the present invention may have a logic circuit.

Further, the counter circuit of the present invention may have a configuration including a D flip-flop circuit and a plurality of logic circuits that output signals corresponding to signals output from the D flip-flop circuit.

The phase shift circuit of the present invention is provided in each stage of the shift register circuit and the shift register circuit for shifting the phase of the signal output to the gate signal line, and the number of signals counted in the counter circuit is A configuration having an analog switch that is switched on and off in response thereto may be used.

According to the present invention, in the active matrix display device, in particular, when driving by a digital driving method, the phase of the scanning signal that is a signal input to the pixel portion and the video signal is the resistance of the wiring to which the signal is supplied. Even when the signal is shifted due to rounding or delay of the signal due to the capacitance component or the like, it is possible to count and repair the signal phase shift inside the display device and obtain a normal display.

Hereinafter, embodiments and examples of the present invention will be described with reference to the drawings. However, the present invention can be implemented in many different modes, and those skilled in the art can easily understand that the modes and details can be variously changed without departing from the spirit and scope of the present invention. Is done. Therefore, the present invention is not construed as being limited to the description of the embodiments and examples. Note that the same portions or portions having similar functions are denoted by the same reference symbols throughout the drawings for describing the embodiments and examples, and the repetitive description thereof is omitted.
(Embodiment 1)

FIG. 1 shows a block diagram of a display device in this embodiment mode, which will be described in detail below. Note that in the present invention, a display device refers to a device having a display element (such as a liquid crystal element or a light-emitting element). Note that a display panel body in which a plurality of pixels including a display element such as a liquid crystal element or an EL element and a peripheral driver circuit for driving these pixels are formed over a substrate may be used. Further, a printed circuit board having a flexible printed circuit (FPC) or a printed wiring board (PWB) may be included. A light-emitting device refers to a display device including a self-luminous display element such as an EL element or an element used in an FED. A liquid crystal display device refers to a display device having a liquid crystal element.

In the present invention, being connected is synonymous with being electrically connected. Therefore, in the configuration disclosed by the present invention, in addition to a predetermined connection relationship, other elements (for example, a switch, a transistor, a capacitor, an inductor, a resistor, a diode, etc.) that can be electrically connected are arranged. May be.

FIG. 1 shows the basic configuration of the present invention. A display device illustrated in FIG. 1A includes a gate signal line driver circuit 101, a source signal line driver circuit 102, a pixel portion 103, a phase comparison circuit 110 (also referred to as a first circuit), and a counter circuit 111 (second circuit). A phase shift circuit 112 (also referred to as a third circuit). A gate line 107 (also referred to as a first signal) is connected to the gate signal line driver circuit 101, and a source line 108 (also referred to as a second signal) is connected to the source signal line driver circuit 102. A pixel 109 in the pixel portion 103 is connected to a gate line 107 and a source line 108. The pixel 109 is provided with a transistor for writing a signal from the source line 108 to a display medium provided in the pixel by a signal of the gate line 107. In each pixel, each terminal of the transistor is connected to the gate line 107. , Connected to the source line 108.

FIG. 1B is a diagram illustrating signals input to each circuit by simplifying the block diagram illustrated in FIG. In FIG. 1B, the gate signal line driver circuit 101 is controlled by the gate signal write control signal GWE input via the phase shift circuit 112, and the source signal line driver circuit 102 is controlled by the source signal write control signal SWE. The A scanning signal (also referred to as a gate signal) is supplied from the gate signal line driver circuit 101 to the gate line 107, and a video signal (also referred to as a source signal or a video signal) is supplied from the source signal line driver circuit 102 to the source line 108. . In the pixel portion 103, a phase comparison circuit 110 is connected to a pair of the gate line 107 and the source line 108 to compare the phases of signals input to the gate line 107 and the source line 108. Then, the output signal from the phase comparison circuit 110 is input to the input terminal of the counter circuit 111 via the wiring. In addition to the signal from the phase comparison circuit 110, the initial set signal PXS is input to the counter circuit 111. Then, a signal corresponding to the number of signals counted by the counter circuit 111 is input to the input terminal of the phase shift circuit 112 from the output terminal of the counter circuit 111. In the phase shift circuit 112, the phase of the gate signal write control signal GWE is shifted in accordance with the timing signal TP, and output from the output terminal to the gate signal line drive circuit 101, thereby correcting the phase shift between the scanning signal and the video signal. To do.

A specific example of the pixel configuration of the pixel 109 is shown in FIG. In FIG. 2, the pixel 201, the transistor 202, and the display medium 203 are included. In this embodiment, an N-channel transistor is used as the transistor 202 (also referred to as a writing transistor) that writes signals from the source line SL. Therefore, when the gate line GL is at a high level, the transistor 202 is turned on, and the potential of the source line SL is taken into the display medium 203. Further, when the gate line GL is at a low level, the transistor 202 is turned off and is not reflected on the potential display medium 203 of the source line SL.

In addition, as a display medium in the display device of the present invention, a liquid crystal display device, a DMD (Digital Micromirror Device), a PDP (Plasma), as well as a display device including a light emitting element typified by an organic light emitting element and an inorganic light emitting element in each pixel. A display device that performs display by a signal input to a display panel (Display Panel), a FED (Field Emission Display) gate line, and a source line is included in its category.

  Note that as a transistor used in the display device of the present invention, a polycrystalline semiconductor, a microcrystalline semiconductor (including a semi-amorphous semiconductor), or a thin film transistor using an amorphous semiconductor can be used. It is not limited to a thin film transistor. A transistor formed using single crystal silicon or a transistor using SOI may be used. In addition, a transistor using an organic semiconductor, a transistor using carbon nanotubes, or a transistor using zinc oxide may be used. In addition, the transistor provided in the pixel of the light-emitting device of the present invention may have a single gate structure, a double gate structure, or a multi-gate structure having more gates.

Next, the function and configuration of the phase comparison circuit 110 in this embodiment will be described with reference to FIG. In the present embodiment, when inputting a signal for lighting the pixel as described above FIG. 22 (C) to the pixel, the potential of the node N _G at the gate line is at the High level, the node N _S in the source line The potential at the time when the signal falls to the low level is taken into the pixel. In the phase comparator circuit 110 takes the logical product of the signal at node N _G in the signal and gate lines of the node N _S in the source line. Specifically, as shown in FIG. 4A, a NAND operation is performed by a NAND circuit, inverted by an inverter circuit, and output to a node N ₁₁₁ on the counter circuit 111 side.

FIG. 3B illustrates the case where the signals of the source line and the gate line are normal signals in the circuit of FIG. FIG. 3C illustrates the case where the signal in the source line and the gate line is out of phase and is not a normal signal in the circuit in FIG. The output shown in FIG. 3 (B) the counter circuit 111 side of the node _{N 111} whereas a Low level, the node _{N 111} of the counter circuit 111 side due to the displacement shown in FIG. 3 (C) in phase a signal of the High level Output.

Further, the phase comparison circuit 110 is not limited to the configuration shown in FIG. FIG. 4A illustrates another structure of the phase comparison circuit 110. 4A, unlike the structure shown in FIG. 3A, when a signal for lighting a pixel is input to the pixel, the potential of the node _NG on the gate line is at a high level. captures potential when the potential of the node N _S in the source line rises to the High level to the pixel. In the phase comparator circuit 110 takes the logical sum of the inverted signal of the signal of the node N _G in the signal and gate lines of the node N _S in the source line. Specifically, is inverted by the inverter circuit a signal at node N _G at the gate line as shown in FIG. 4 (A), inputs the signal of the node N _S in the source line to the NOR circuit, the nodes of the counter circuit 111 side N ₁₁₁ is output.

FIG. 4B illustrates the case where the source line signal and the gate line signal are normal signals in the circuit in FIG. FIG. 4C shows the case where the phase of the gate line signal is out of phase with the signal of the source line in the circuit of FIG. Figure 4 (B) with respect to the the node _{N 111} of the counter circuit 111 side outputs a Low-level signal, FIG. 4 (C) in the phase node _{N 111} is the High level signal with the deviation of the counter circuit 111 side of the Is output.

Next, the function and configuration of the counter circuit 111 in this embodiment will be described. In this embodiment, the output signal from the phase comparison circuit 110 shown in FIG. 3 is counted by a counter using the D flip-flop circuit shown in FIG. In the D flip-flop circuit in FIG. 5, an initial set signal PXS for making an initial state is input. In addition, the D flip-flop circuit in this embodiment has a two-stage configuration, and output signals are output from the terminal C0, the terminal C1, the terminal C2, and the terminal C3. The signal output from the first-stage D flip-flop circuit is the node N _B1 , and the signal output from the second-stage D flip-flop circuit is via the node N _B2 , via the node N _B1 and the node N _B2 . These signals are counted by a logic circuit and output from terminals C0, C1, C2, and C3.

Note that a logic circuit in this specification refers to a circuit expressed by combining transistors, such as an AND circuit and an OR circuit. In addition, as the transistor in this specification, a compound semiconductor such as a thin film transistor (TFT), a transistor formed using a semiconductor substrate or an SOI substrate, a MOS transistor, a junction transistor, a bipolar transistor, ZnO, or a-InGaZnO is used. A transistor such as a conventional transistor, a transistor using an organic semiconductor, or a carbon nanotube can be used. In addition, various types of substrates on which the transistor is arranged can be used, and the substrate is not limited to a specific type. Therefore, for example, it can be disposed on a single crystal substrate, an SOI substrate, a glass substrate, a plastic substrate, a paper substrate, a cellophane substrate, a stone substrate, or the like. Alternatively, a transistor may be formed using a certain substrate, and then the transistor may be moved to another substrate and placed on another substrate.

An example of a D flip-flop circuit in the counter circuit used in this embodiment is illustrated in FIG. The D flip-flop circuit described in this embodiment is an example of what is configured as a NAND circuit and is used as a counter. However, other circuits may be used as long as they have a counter function. It doesn't matter. In the counter circuit, the number of stages of the D flip-flop circuit and the number of output terminals may be increased. For example, if the D flip-flop circuit is configured in three stages and the number of output terminals is eight, the phase shift of the signal input to the pixel in the phase shift circuit can be accurately corrected.

FIG. 7 shows a timing chart of the counter circuit shown in FIG. First, the initial set signal PXS is input to the counter circuit 111 only once before the operation of the phase comparison circuit 110 is started. When the initial set signal PXS is input, the output signal from the terminal C0 in the counter circuit becomes Low level, and the signals output from the terminals C1, C2, and C3 become High level. When the potential of N ₁₁₁ that is an output signal from the phase comparison circuit 110 is at a high level, the potentials of the nodes N _B1 and N _B2 change. As a result, whenever the phase shift is detected, the low level of the potential at the terminal C0 is shifted at the terminal C1, the terminal C2, and the terminal C3, whereby the above-described phase shift can be counted.

Next, the function and configuration of the phase shift circuit 112 in this embodiment will be described. In the present embodiment, the phase of the gate signal write control signal GWE is shifted in the phase shift circuit 112 in FIG. 8 based on the output signal from the counter circuit 111 shown in FIG. When the gate signal write control signal GWE is not shifted, the wiring to which the gate signal write control signal GWE is input is directly connected to the analog switch, and is output as it is when the analog switch is turned on by a signal from the terminal C0. The phase shift circuit 112 shown in FIG. 8 has a configuration having a number of flip-flop circuits corresponding to the output signal from the counter circuit 111, and each stage of the flip-flop circuit passes through an analog switch provided in each stage. 1 is connected to the gate signal line driving circuit 101 in FIG. Each analog switch is connected to a terminal C1, a terminal C2, and a terminal C3 from which a signal from the counter circuit 111 is output.

FIG. 9 shows a timing chart of the phase shift circuit 112 shown in FIG. The gate signal write control signal GWE input to the phase shift circuit 112 is shifted from the node N _A1 , the node N _A2 , and the node N _A3 by shifting the High level period by the half wavelength of the timing signal TP by the flip-flop circuit. Is done.

By adopting the structure of this embodiment mode, in the active matrix display device, in particular, when driving by a digital driving method, the phase of the scanning signal and the video signal that are input to the pixel portion is Even if the signal is shifted due to rounding or delay of the signal due to the resistance or capacitance component of the supplied wiring, it is possible to count and repair the phase shift of the signal inside the display device and obtain a normal display It becomes.

Note that the configuration of each circuit in this embodiment is merely an example, and is not limited thereto. In other words, the phase comparison circuit may be any circuit that can detect and output a phase shift between signals supplied to two connected wirings. The counter circuit may be any circuit that counts the phase shift detected by the phase comparison circuit and outputs a signal corresponding to the number of counts. The phase shift circuit is a circuit that shifts the phase of one of the phases of the signals supplied to the two connected wirings based on the count number in the counter circuit. That's fine.

Note that this embodiment can be implemented in combination with any of the other embodiments in this specification.
(Embodiment 2)

In this embodiment, a structure different from the structure shown in Embodiment 1 will be described.

First, a method for driving the display device in this embodiment will be described with reference to FIGS.

In the time gray scale method, which is one of the methods for expressing gray scales by the digital gray scale method, the row writing period is divided into two, and the video to the pixels is divided in the first half row writing period (first row writing period). There is a driving method in which a signal is written and a signal for erasing a video signal written in the pixel is written in the pixel in the latter row writing period (second row writing period). A non-display period is provided by writing a signal for erasing the video signal written in the pixel to the pixel, and the length of the subframe period is shorter than the length of the writing period. Such a driving method is shown in FIG.

FIG. 10 will be described. In the address period Ta1, scanning signals are sequentially input to the gate signal lines from the first row, and pixels are selected. When a pixel is selected, a video signal is input from the source signal line to the pixel. When a video signal is written to the pixel, the pixel holds the signal until the signal is input again. Lighting and non-lighting of each pixel in the sustain period Ts1 are controlled by the written video signal. That is, in the row where the video signal writing operation is completed, the pixel is turned on or off in accordance with the video signal immediately written. The same operation is performed up to the last row, and the address period Ta1 ends. Then, the signal writing operation in the next subframe period is started in order from the row where the data holding time has ended. Similarly, video signals are input to the pixels in the address periods Ta2, Ta3, and Ta4, and lighting and non-lighting of each pixel in the sustain periods Ts2, Ts3, and Ts4 are controlled by the video signals. In the sustain period Ts4, the cycle is set by starting the erase operation. This is because if the signal written to the pixel is erased at the erase time Te of each row, the signal is forced regardless of the video signal written to the pixel in the address period until the signal is written to the next pixel. This is because the light is not turned on. That is, the data holding time ends from the pixel in the row where the erasing time Te has started.

Therefore, it is possible to provide a display device in which the data holding period is shorter than the address period and has a high duty ratio (the ratio of the lighting period in one frame period) without separating the address period and the sustain period. In addition, since the instantaneous luminance can be reduced, the reliability of the display element can be improved. As shown in FIG. 10B, by providing a write time for a write operation and an erase time for an erase operation in one horizontal period, the data holding time is shorter than the address period as shown in FIG. Can be expressed.

For example, as shown in FIG. 11, one horizontal period is divided into two. Here, the first half will be described as writing time, and the second half will be described as erasing time. Then, each scanning line is selected within the divided horizontal period, and a corresponding signal is input to the source signal line at that time. For example, in one horizontal period, the i-th row is selected in the first half and the j-th row is selected in the second half. Then, in one horizontal period, it is possible to operate as if two rows were selected at the same time. That is, the video signal is written from the source signal line to the pixel during the writing time Tb1 to Tb4 using the writing time of the first half of each horizontal period. At this time, no pixel is selected in the erasing time in the second half of one horizontal period. In addition, an erase signal is input from the source signal line to the pixel at the erase time Te using the erase time in the latter half of another horizontal period. At this time, no pixel is selected in the writing time in the first half of one horizontal period. Thus, a display device including a pixel with a high aperture ratio can be provided, and the yield can be improved.

An example of a display device that drives as described above is shown in FIG.

The pixel portion 1203 includes the first gate signal line driver circuit 1201A, the second gate signal line driver circuit 1201B, the source signal line driver circuit 1202, and the pixel portion 1203. The pixel portion 1209 includes the gate signal lines G1 to Gm and the source. They are arranged in a matrix corresponding to the signal lines S1 to Sn. The first gate signal line driver circuit 1201A includes a shift register circuit 1204A and a switch 1205A that controls conduction or non-conduction between the shift register circuit 1204A and each of the gate signal lines G1 to Gm. The second gate signal line driver circuit 1201B includes a shift register circuit 1204B and a switch 1205B that controls conduction or non-conduction between the shift register circuit 1204B and each of the gate signal lines G1 to Gm.

Note that the gate signal line Gp (any one of the gate signal lines G1 to Gm) corresponds to the gate line 107 in FIG. 1, and the source signal line Sq (any one of the source signal lines S1 to Sn) is shown in FIG. It corresponds to the source line 108.

Signals such as a clock signal (GCLK), a clock inversion signal (GCLKB), a start pulse signal (GSP), and a first gate signal write control signal (GWE1) are input to the first gate signal line driver circuit 1201A. . Then, in accordance with these signals, a signal for selecting a pixel is output to the first gate signal line Gp (any one of the gate signal lines G1 to Gm) of the selected pixel row. The signal at this time is a pulse output in the first half of one horizontal period as shown in the timing chart of FIG. That is, a signal output from the shift register circuit 1204A is output to the gate signal lines G1 to Gm only when the switch 1205A is on.

Signals such as a clock signal (RCLK), a clock inversion signal (RCLKB), a start pulse signal (RSP), and a second gate signal write control signal (GWE2) are input to the second gate signal line driver circuit 1201B. . Then, in accordance with these signals, a signal is output to the second gate signal line Gq (any one of the gate signal lines G1 to Gm) of the pixel row to be selected. The signal at this time is a pulse output in the second half of one horizontal period as shown in the timing chart of FIG. That is, the signal output from the shift register circuit 1204B is output to the gate signal lines G1 to Gm only when the switch 1205B is on.

The source signal line driver circuit 1202 receives signals such as a clock signal (SCLK), a clock inversion signal (SCLKB), a start pulse signal (SSP), a video signal (Video Data), and a source signal write control signal (SWE). Entered. And according to those signals, the signal according to the pixel of each column is output to each source signal line S1-Sn. A signal output from the source signal line driver circuit 1202 is controlled by the source signal write control signal (SWE). That is, when the source signal write control signal (SWE) is at a low level, a video signal is output, and when it is at a high level, an erase signal is output.

Therefore, the video signal input to the source signal lines S1 to Sn is selected by the signal input to the gate signal line Gi (any one of the gate signal lines G1 to Gm) from the first gate signal line driving circuit 1201A. Is written in the pixel 1209 of each column of the pixel row. Then, each pixel row is selected by each gate signal line G1 to Gm, and a video signal corresponding to each pixel is written to each pixel 1209. Each pixel 1209 holds the data of the written video signal for a certain period. Each pixel 1209 can maintain a lighting or non-lighting state.

In the driving method shown in FIGS. 10 to 12, the gate signal line performs scanning for writing video data and scanning for erasing video data in one horizontal period. As shown in FIG. 13A, the scanning for writing video data and the scanning for erasing video data must have a normal phase relationship with the source signal. However, as shown in FIGS. 13B and 13C, there may be a case where a normal phase relationship and a bad phase relationship are mixed in one horizontal period. Further, as shown in FIG. 13D, there may be a case where both the scanning for writing video data and the scanning for erasing video data are out of phase in one horizontal period.

Therefore, in this embodiment, even when such video signal writing and erasing are performed on the same gate signal line in one horizontal period, a phase shift is detected, the shift is counted, and the phase is calculated. A display device capable of correcting to a normal phase by shifting will be described.

FIG. 14 shows a block diagram of a display device in this embodiment mode, which will be described in detail below. The block diagram shown in FIG. 14 is a simplified illustration of the display device shown in FIG. 12, and the same reference numerals are given to the reference numerals. In addition, about the specific example of each structure in this Embodiment, if it is the structure similar to Embodiment 1, the description in Embodiment 1 will be used for the description.

FIG. 14 shows the basic configuration of this embodiment. A display device illustrated in FIG. 14A includes a first gate signal line driver circuit 1201A, a second gate signal line driver circuit 1201B, a source signal line driver circuit 1202, a pixel portion 1203, and a phase comparison circuit 1210 (first A first counter circuit 1211A (also referred to as a second circuit), a second counter circuit 1211B, a first phase shift circuit 1212A (also referred to as a third circuit), and a second phase shift circuit 1212B. Have A gate line 1207 is connected to the first gate signal line driver circuit 1201A and the second gate signal line driver circuit 1201B, and a source line 1208 is connected to the source signal line driver circuit 1202. A pixel 1209 in the pixel portion 1203 is connected to a gate line 1207 and a source line 1208. The pixel 1209 is provided with a transistor for writing a signal from the source line 1208 to a display medium provided in the pixel by a signal of the gate line 1207, and each terminal of the transistor in each pixel has a gate line 1207. , Connected to the source line 1208.

FIG. 14B is a diagram illustrating signals input to each circuit by simplifying the block diagram illustrated in FIG. In FIG. 14B, the first gate signal line driver circuit 1201A is controlled by the first gate signal write control signal GWE1 input through the first phase shift circuit 1212A, and the second gate signal line driver is driven. The circuit 1201B is controlled by the second gate signal write control signal GWE2 input via the second phase shift circuit 1212B, and the source signal line driver circuit 1202 is controlled by the source signal write control signal SWE. A first scanning signal (also referred to as a writing signal) is transferred from the first gate signal line driver circuit 1201A to the gate line 1207, and a second scanning signal (also referred to as an erasing signal) is transferred from the second gate signal line driver circuit 1201B to the gate line 1207. A video signal (also referred to as a source signal or a video signal) is supplied from the source signal line driver circuit 1202 to the source line 1208. In the pixel portion 1203, a pair of a gate line 1207 and a source line 1208 is connected to a phase comparison circuit 1210 to which a set signal EXS is input every horizontal period, and is input to the gate line 1207 and the source line 1208. Compare the phase of the signal. Then, the output signal from the phase comparison circuit 1210 is input to the input terminals of the first counter circuit 1211A and the second counter circuit 1211B through wiring. In addition to the signal from the phase comparison circuit 1210, the initial set signal PXS is input to the first counter circuit 1211A and the second counter circuit 1211B. Then, signals corresponding to the number of signals counted by the first counter circuit 1211A and the second counter circuit 1211B from the output terminals of the first counter circuit 1211A and the second counter circuit 1211B are the first phase. The signals are input to the input terminals of the shift circuit 1212A and the second phase shift circuit 1212B. In the first phase shift circuit 1212A and the second phase shift circuit 1212B, the phases of the first gate signal write control signal GWE1 and the second gate signal write control signal GWE2 are shifted according to the timing signal TP, By outputting to the first gate signal line driver circuit 1201A and the second gate signal line driver circuit 1201B from the output terminal, the phase shift between the first scanning signal and the second scanning signal and the video signal is corrected.

The pixel configuration of the pixel 1209 is the same as the configuration in FIG. 2 described in Embodiment 1.

Next, the function and configuration of the phase comparison circuit 1210 in this embodiment will be described with reference to FIG. In the present embodiment, in potential High level of the node N _G at the gate lines, the uptake in the pixel as the signal write potential when the signal at node N _S in the source line falls to the Low level, the node at the gate lines potential of N _G is High level, the signal of the node N _S in the source line is assumed to take the pixels as the erase signal potential when the rose to the High level.

In the phase comparator circuit 1210, it provided a logic circuit LOG1 taking the logical product of the signals of the node N _G in the signal and gate lines of the node N _S in the source line. Specifically, the circuit shown in FIG. 3A of Embodiment 1 is provided. Also, provision of the logic circuit LOG2 ORing inverted signal of the signal of the node N _G in the signal and gate lines of the node N _S in the same time the source line. Specifically, the circuit illustrated in FIG. 4A described in Embodiment 1 is provided.

Outputs from the logic circuits LOG1 and LOG2 are input to the counter circuit 1503A and the counter circuit 1503B via the node N _1503A and the node N _1503B . The counter circuit 1503A and the counter circuit 1503B in FIG. 15 are configured by a two-stage D flip-flop circuit. Note that the D flip-flop circuit in the counter circuit 1503A and the counter circuit 1503B includes the circuit of FIG. 6 described in Embodiment 1.

Note that in the counter circuit 1503A and the counter circuit 1503B, the terminal Q in the first-stage D flip-flop circuit is not connected to the terminal CLK in the second-stage D flip-flop circuit, and is a terminal in the first-stage D flip-flop circuit. QB is connected to a terminal CLK in the second-stage D flip-flop circuit. In the counter circuit 1503A and the counter circuit 1503B, the set signal EXS is input to the terminal XS in each stage of the D flip-flop circuit.

A terminal Q in the second stage D flip-flop circuit of the counter circuit 1503A connected to the logic circuit LOG1 through the node N _1503A is connected to an input terminal of an analog switch 1504 (also referred to as an analog switch circuit). The node N _1503B is connected to the control terminal of the analog switch 1504 and the input terminal of the inverter circuit 1505. The output terminal of the inverter circuit 1505 is connected to the inversion control terminal of the analog switch 1504 and the gate of the transistor 1506. Note that in this embodiment, the transistor 1506 is an N-channel transistor. When the potential of the signal from the inverter circuit 1505 is at a low level, the transistor 1506 is turned off and the analog switch 1504 is turned on. The terminal Q in the second stage D flip-flop circuit of the counter circuit 1503A is turned on from the output terminal of the analog switch 1504. _Is output to a node N _1211A between the phase comparison circuit 1210 and the first counter circuit 1211A in FIG. In addition, when the potential of the signal from the inverter circuit 1505 is at a high level, the analog switch 1504 is turned off, the transistor 1506 is turned on, and the GND potential connected to the first terminal of the transistor 1506 is lower than the second terminal of the transistor 1506. 14 is output to the node N _1211A between the phase comparison circuit 1210 and the first counter circuit 1211A.

The output signal from the terminal Q in the second stage D flip-flop circuit of the counter circuit 1503B connected to the logic circuit LOG2 via the node N _1503B is the phase comparison circuit 1210 and the second counter circuit 1211B in FIG. To node N _1211B .

Further, the second counter circuit 1211B in FIG. 14 is the same as the structure in FIG. 5 described in the first embodiment. Further, the D flip-flop circuit in the first counter circuit 1211A and the second counter circuit 1211B has the circuit of FIG. 6 shown in Embodiment Mode 1.

Further, the first phase shift circuit 1212A and the second phase shift circuit 1212B in FIG. 14 are the same as those in FIG. 8 described in the first embodiment. Note that a signal from the first counter circuit 1211A is input to the first phase shift circuit 1212A, and a signal from the second counter circuit 1211B is input to the second phase shift circuit 1212B.

Next, the operation of FIG. 14 in the present embodiment will be described with reference to the timing charts of FIGS. Note that the logic circuit LOG1 and the counter circuit 1503A in FIG. 15 and the first counter circuit 1211A and the first phase shift circuit 1212A in FIG. 14 shift the phase shift between the gate signal line and the source signal line related to the video signal writing operation. It is to correct. Further, the logic circuit LOG2 and the counter circuit 1503B in FIG. 15 and the second counter circuit 1211B and the second phase shift circuit 1212B in FIG. 14 correct the phase shift between the gate signal line and the source signal line related to the video signal erasing operation. To do.

FIG. 16 is a timing chart when the phases of the signals of the source signal line and the gate signal line are not shifted at the time of writing the video signal and writing of the erase signal. In FIG. 16, when the potential of the source signal line is at the low level, the potential of the gate signal line is set to the high level so that the potential of the source signal line is taken into the pixel during the writing period, and the potential of the source signal line is at the high level. At this time, the potential held in the pixel is erased by setting the potential of the gate signal line to the high level. 17 is a timing chart when the phase of the signal of the gate signal line is shifted in the writing period, FIG. 18 is a timing chart when the phase of the signal of the gate signal line is shifted in the erasing period, and FIG. 6 is a timing chart when the phase of a signal of a gate signal line is shifted in an erasing period.

16, the node _{N 1503A} in the phase comparator circuit 1210 of FIG. 14, the potential of the node _{N 1503B} is a logic circuit LOG1, is the potential of the signal output by the logic circuit LOG2. In FIG. 16, when the potential of the gate signal line is at a high level and the potential of the source signal line is at a high level, that is, when an operation of erasing the potential held in the pixel in the erasing period is performed, The potential of N _1503A becomes High level. In FIG. 16, when the potential of the gate signal line is High level and the potential of the source signal line is Low level, that is, when an operation of writing a signal to the pixel in the writing period is performed, the logic circuit LOG2 outputs the output of the node N _1503B . The potential becomes a high level. Therefore, with the writing operation and the erasing operation in one horizontal period, the potentials of the node N _1503A and the node N _1503B once become a high level.

In the writing period, when the potential of the gate signal line is High level and the potential of the source signal line is High level, that is, when the phase of the gate signal line is shifted as shown in FIG. The potential of the node N _{1503A as} an output is set to a high level. In the erasing period, the logic circuit LOG2 outputs an output when the potential of the gate signal line is high level and the potential of the source signal line is low level, that is, when the phase of the gate signal line is shifted as shown in FIG. The potential of a certain node N _1503B is set to a high level. Therefore, in one horizontal period, the potentials of the node N _1503A and the node N _1503B are set to the high level along with the writing operation and the erasing operation, and the potentials of the node N _1503A and the node N _1503B are set to the high level twice. That is, the potential of the node N _1503A or the node N _1503B becomes a high level based on a change in potential due to a normal writing or erasing operation and a change in potential based on a phase shift between the gate signal line and the source signal line. It is based on.

In the case of this embodiment, the potential difference between the gate signal line and the source signal line when writing a video signal is detected in detecting a shift in the phase of the signal in the gate signal line and the phase of the signal in the source signal line. There is a problem that the relationship between the relationship and the potential relationship when the potentials of the gate signal line and the source signal line in the erasing period are the same is the same. For this reason, the counter circuit provided in the phase comparison circuit in this embodiment has a writing period and an erasing period each time a high level is input or a high level is input twice in a certain horizontal period. Every time, by inputting the set signal EXS, whether the potential changes due to normal writing or erasing operation by one High level, the potential based on the phase shift of the gate signal line and the source signal line by two High levels It is determined whether the change.

For example, in the case of FIG. 16 in which there is no phase shift between the signal of the gate signal line and the source signal line in the writing period and the erasing period, the node N _1503A and the node N _{1503B is set to the} High level only once, and the counter circuit 1503A and the counter circuit 1503B do not output a High level signal that is a signal in which a phase shift is detected at the node N _1211A or the node N _1211B .

In the case of FIG. 17 in which the signal phase of the gate signal line and the source signal line is shifted in the writing period, the gate signal line and the source signal line in the erasing period are in the period during which the set signal EXS is at the high level. The node N _1503B for detecting the phase shift of the first node is at a high level only once, and the counter circuit 1503B does not output a signal at the high level that is a signal at which the phase shift is detected at the node N _1211B . On the contrary, the node N _1503A for detecting the phase shift between the gate signal line and the source signal line in the writing period is twice high, and the counter circuit 1503A is a signal in which the phase shift is detected at the node N _1211A. A high level signal is output.

Further, in the case of FIG. 18 where the phase of the signal of the gate signal line and the source signal line is shifted in the erasing period, the gate signal line and the source signal line in the writing period are in the period during which the set signal EXS is at the high level. The node N _1503A for detecting the phase shift of the first node is at a high level only once, and the counter circuit 1503A does not output a signal at the high level that is a signal in which the phase shift is detected at the node N _1211A . On the contrary, the node N _1503B for detecting the phase shift between the gate signal line and the source signal line in the erasing period is twice high, and the counter circuit 1503B is a signal in which the phase shift is detected at the node N _1211B. A high level signal is output.

Further, in the case of FIG. 19 in which the phase of the signal of the gate signal line and the source signal line is shifted in the writing period and the erasing period, the gate signal line in the writing period and the period of the period during which the set signal EXS becomes High level The node N _1503A for detecting the phase shift of the source signal line is at a high level twice, and the counter circuit 1503A outputs a high level signal that is a signal at which the phase shift is detected at the node N _1211A . Further, the node N _1503B for detecting the phase shift between the gate signal line and the source signal line in the erasing period is set to a high level twice, and the counter circuit 1503B is a signal whose phase shift is detected at the node N _1211B. A level signal is output.

In addition, the analog switch 1504 connected to the output terminal of the counter circuit 1503A that counts the phase shift of the signal in the writing period has a correction defect that occurs when the signal of the source signal line is at a high level, that is, the display is black. It is for prevention. As an example, FIG. 20 shows a timing chart when the signal of the source signal line is at a high level, that is, when the display is black. The potential of the source signal line shown in FIG. 20 is constant at a high level. As shown in FIG. 20, in the period during which the set signal EXS is at the high level, the node N _1503A for detecting the phase shift between the gate signal line and the source signal line in the writing period is at the high level twice. The counter circuit 1503A outputs a high level signal that is a signal in which a phase shift is detected at the node N _1211A .

Note that for the node N _1503B for detecting a phase shift between the gate signal line and the source signal line in the erasing period, a high level signal is output when the potential of the gate signal line is high and the potential of the source signal line is low. _Therefore , the node N _1503B is always at the low level. At this time, the potential level of the node N _1503B is input to the gate of the transistor 1506 through the inverter circuit 1505 without turning on the analog switch 1504. That is, when the node N _1503B is at a low level, a high-level signal is input to the gate of the transistor 1506 through the inverter circuit 1505. Since the transistor 1506 is an N-channel transistor, the transistor 1506 is turned on. The GND potential connected to one terminal is output from the second terminal of the transistor 1506 to the node N _1211A between the phase comparison circuit 1210 and the first counter circuit 1211A in FIG. As a result, the phase comparison circuit 1210 can perform phase comparison only when the potential of the source signal line is at the low level, and the output of the counter circuit 1503A is shown in FIG. 20 during the period when the source signal line is at the high level. Thus, even if a signal indicating a phase shift is output even though the phase is not shifted, output from the counter circuit 1503B is prevented by turning on or off the analog switch 1504 and turning on or off the transistor 1506. be able to. Further, the potential of the transistor 1506 and the GND connected to the analog switch 1504 can be set to the GND potential that is at a low level, avoiding that the node N _1211A becomes a floating potential when the analog switch 1504 is turned off.

FIG. 4B illustrates the case where the source line signal and the gate line signal are normal signals in the circuit in FIG. FIG. 4C shows the case where the phase of the gate line signal is out of phase with the signal of the source line in the circuit of FIG. Figure 4 (B) with respect to the the node _{N 111} of the counter circuit 111 side outputs a Low-level signal, FIG. 4 (C) in the phase node _{N 111} is the High level signal with the deviation of the counter circuit 111 side of the Is output.

By adopting the structure of this embodiment mode, in an active matrix display device, in particular, when driving by a digital drive method, and in particular, input / output of a video signal input to a pixel in one horizontal period Even when scanning lines are used, the phase of the scanning signal that is a signal input to the pixel portion and the video signal is shifted due to rounding or delay of the signal due to the resistance or capacitance component of the wiring to which the signal is supplied. Even in this case, it is possible to count and repair the phase shift of the signal in the display device and obtain a normal display.

Note that the configuration of each circuit in this embodiment is merely an example, and is not limited thereto. That is, the phase comparison circuit may be any circuit that can separately detect and output a phase shift between two types of signals supplied to any one of two connected wirings. . Further, the first counter circuit and the second counter circuit may be circuits that separately count phase shifts of two types of signals detected by the phase comparison circuit and output a signal corresponding to the count number. Further, in the first phase shift circuit and the second phase shift circuit, a first counter is used for a phase shift between two types of signals supplied to any one of two connected wirings. Any circuit that shifts the phase of the signal separately based on the count number in the circuit or the second counter circuit may be used.

  Note that this embodiment can be implemented in combination with any of the other embodiments in this specification as appropriate.

As an electronic device using the display device of the present invention, a video camera, a digital camera, a goggle type display (head mounted display), a navigation system, a sound reproduction device (car audio, audio component, etc.), a notebook personal computer, a game device, A portable information terminal (mobile computer, mobile phone, portable game machine, electronic book, etc.), an image playback device (specifically, Digital Versatile Disc (DVD)) provided with a storage medium is played back, and the image is displayed. A device provided with a display capable of displaying). Specific examples of these electronic devices are shown in FIGS.

FIG. 21A illustrates a light-emitting device, which includes a housing 2401, a support base 2402, a display portion 2403, a speaker portion 2404, a video input terminal 2405, and the like. The present invention can be used for a display device included in the display portion 2403. According to the present invention, display defects can be reduced and a clear image can be viewed. The light emitting device includes all display devices for displaying information such as for personal computers, for receiving TV broadcasts, and for displaying advertisements.

FIG. 21B shows a digital still camera, which includes a main body 2406, a display portion 2407, an image receiving portion 2408, operation keys 2409, an external connection port 2410, a shutter 2411, and the like. The present invention can be used for a display device included in the display portion 2407. According to the present invention, display defects can be reduced and a clear image can be seen.

FIG. 21C illustrates a laptop personal computer, which includes a main body 2412, a housing 2413, a display portion 2414, a keyboard 2415, an external connection port 2416, a pointing device 2417, and the like. The present invention can be used for a display device included in the display portion 2414. According to the present invention, display defects are reduced and a clear image can be viewed.

FIG. 21D illustrates a mobile computer, which includes a main body 2418, a display portion 2419, a switch 2420, operation keys 2421, an infrared port 2422, and the like. The present invention can be used for a display device included in the display portion 2419. According to the present invention, display defects are reduced and a clear image can be viewed.

FIG. 21E illustrates a portable image playback device (specifically, a DVD playback device) provided with a storage medium device, which includes a main body 2423, a housing 2424, a display portion A 2425, a display portion B 2426, a storage medium (such as a DVD). ) A reading unit 2427, an operation key 2428, a speaker unit 2429, and the like are included. The display portion A 2425 mainly displays image information, and the display portion B 2426 mainly displays character information. The present invention can be used for a display device that forms the display portion A 2425 and the display portion B 2426. According to the present invention, display defects can be reduced and a clear image can be seen. Note that an image reproducing device provided with a recording medium includes a home game machine and the like.

FIG. 21F illustrates a goggle type display (head mounted display), which includes a main body 2430, a display portion 2431, an arm portion 2432, and the like. The present invention can be used for a display device included in the display portion 2431. According to the present invention, display defects can be reduced and a clear image can be viewed.

FIG. 21G illustrates a video camera, which includes a main body 2433, a display portion 2434, a housing 2435, an external connection port 2436, a remote control reception portion 2437, an image receiving portion 2438, a battery 2439, an audio input portion 2440, operation keys 2441, and the like. . The present invention can be used for a display device included in the display portion 2434. According to the present invention, display defects can be reduced and a clear image can be viewed.

FIG. 21H illustrates a mobile phone, which includes a main body 2442, a housing 2443, a display portion 2444, an audio input portion 2445, an audio output portion 2446, operation keys 2447, an external connection port 2448, an antenna 2449, and the like. The present invention can be used for a display device included in the display portion 2444. Note that the display portion 2444 can suppress current consumption of the mobile phone by displaying white characters on a black background. Further, according to the present invention, display defects are reduced, and a clear image can be viewed.

As described above, the applicable range of the present invention is so wide that the present invention can be used for electronic devices in various fields. In addition, a display device using any of the structures shown in Embodiment Modes 1 and 2 can be applied to the electronic device of this example.

The block diagram for demonstrating the structure of this invention. Explanatory drawing of the pixel in the display apparatus to which this invention is applied. The figure shown about the example of the phase comparison circuit of this invention, and the timing chart figure shown about the example of the phase comparison circuit of this invention. The figure shown about the example of the phase comparison circuit of this invention, and the timing chart figure shown about the example of the phase comparison circuit of this invention. The figure shown about an example of the counter circuit of this invention. The circuit diagram shown about an example of D flip-flop circuit of the present invention. FIG. 5 is a timing chart showing the operation of the counter circuit of the present invention. The figure shown about an example of the phase shift circuit of this invention. FIG. 4 is a timing chart showing the operation of the phase shift circuit of the present invention. The figure explaining Embodiment 2 of this invention. The figure explaining Embodiment 2 of this invention. The figure explaining Embodiment 2 of this invention. The figure explaining Embodiment 2 of this invention. The figure for demonstrating the structure of the phase comparison circuit of Embodiment 2 of this invention. The block diagram for demonstrating the structure of Embodiment 2 of this invention. The timing chart for demonstrating the phase comparison circuit of Embodiment 2 of this invention. The timing chart for demonstrating the phase comparison circuit of Embodiment 2 of this invention. The timing chart for demonstrating the phase comparison circuit of Embodiment 2 of this invention. The timing chart for demonstrating the phase comparison circuit of Embodiment 2 of this invention. The timing chart for demonstrating the phase comparison circuit of Embodiment 2 of this invention. FIG. 11 illustrates an example of an electronic device to which a display device of the present invention is applied. The figure explaining the conventional example.

Explanation of symbols

101 Gate Signal Line Driver Circuit 102 Source Signal Line Driver Circuit 103 Pixel Unit 107 Gate Line 108 Source Line 109 Pixel 110 Phase Comparison Circuit 111 Counter Circuit 112 Phase Shift Circuit 201 Pixel 202 Transistor 203 Display Medium 1202 Source Signal Line Driver Circuit 1203 Pixel Unit 1207 Gate line 1208 Source line 1209 Pixel 1210 Phase comparison circuit 1503A Counter circuit 1503B Counter circuit 1504 Analog switch 1505 Inverter circuit 1506 Transistor 2201 transistor 2202 Driving transistor 2203 Light emitting element 2401 Housing 2402 Support base 2403 Display unit 2404 Speaker unit 2405 Video Input terminal 2406 Main body 2407 Display unit 2408 Image receiving unit 2409 Operation key 2410 Part connection port 2411 shutter 2412 body 2413 housing 2414 display unit 2415 keyboard 2416 an external connection port 2417 a pointing device 2418 body 2419 display unit 2420 switches 2421 operation keys 2422 infrared port 2423 body 2424 housing 2425 display portion A
2426 Display B
2427 Reading unit 2428 Operation key 2429 Speaker unit 2430 Main body 2431 Display unit 2432 Arm unit 2433 Main unit 2434 Display unit 2435 Case 2436 External connection port 2437 Remote control receiving unit 2438 Image receiving unit 2439 Battery 2440 Audio input unit 2441 Operation key 2442 Main unit 2443 Case 2444 Display unit 2445 Audio input unit 2446 Audio output unit 2447 Operation key 2448 External connection port 2449 Antenna 1201A Gate signal line driver circuit 1201B Gate signal line driver circuit 1202 Source signal line driver circuit 1204A Shift register circuit 1204B Shift register circuit 1205A Switch 1205B switch 1211A counter circuit 1211B counter circuit 1212A phase shift circuit 1212B phase shift circuit

Claims (9)

A gate signal line;
A source signal line;
A phase comparison circuit that compares the phase of the signal output to the gate signal line and the signal output to the source signal line;
A counter circuit that counts the number of signals output from the phase comparison circuit;
A display device comprising: a phase shift circuit that shifts a phase of a signal output to the gate signal line based on a signal output from the counter circuit. In claim 1,
The counter circuit is
A D flip-flop circuit;
And a plurality of logic circuits that output signals corresponding to signals output from the D flip-flop circuit . In claim 1 or 2,
The phase comparison circuit includes a logic circuit . In any one of Claims 1 thru | or 3,
The phase shift circuit includes:
A shift register circuit for shifting the phase of the signal output to the gate signal line,
Wherein provided in each stage of the shift register circuit, a display and having a an analog switch switched on and off in response to the number of signals counted in the counter circuit device. A gate signal line from which the first signal and the second signal are output;
A source signal line for outputting a video signal;
A phase comparison circuit that compares the phase of the first signal and the phase of the video signal, and compares the phase of the second signal and the phase of the video signal;
A first counter circuit that counts the number of signals output by comparing the phase of the first signal and the video signal in the signal output from the phase comparison circuit;
A second counter circuit that counts the number of signals output by comparing the phase of the second signal and the video signal in the signal output from the phase comparison circuit;
A first phase shift circuit that shifts a phase of the first signal based on a signal output from the first counter circuit;
A display device, comprising: a second phase shift circuit that shifts a phase of the second signal based on a signal output from the second counter circuit. In claim 5,
The first counter circuit and the second counter circuit are:
A D flip-flop circuit;
And a plurality of logic circuits that output signals corresponding to the signals output from the D flip-flop circuit . In claim 5 or 6,
The phase comparison circuit is
Logic circuit;
And a D flip-flop circuit . In any one of Claims 5 thru | or 7,
The first phase shift circuit includes:
A first shift register circuit for shifting the phase of said first signal output to the gate signal line,
Provided in each stage of the first shift register circuit has an analog switch that is switched ON and OFF in accordance with the number of counted signal in the first counter circuit,
The second phase shift circuit includes:
A second shift register circuit for shifting the phase of the second signal output to the gate signal line,
A display device , comprising: an analog switch provided at each stage of the second shift register circuit, wherein the analog switch is switched on and off in accordance with the number of signals counted in the second counter circuit.   An electronic apparatus comprising the display device according to claim 1 in a display unit.

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