JP4972917B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

The present invention relates to a semiconductor device in which each cell of a MOS (Metal Oxide Semiconductor) transistor having a trench gate is dispersedly arranged in an element region including an SOI (Silicon On Insulator) layer surrounded by an element isolation trench, and It relates to the manufacturing method.

A semiconductor device in which each cell of a MOS transistor is arranged in an element region formed of an SOI layer surrounded by an element isolation trench is disclosed in, for example, Japanese Patent Laid-Open No. 8-213604 (Patent Document 1) and Japanese Patent Laid-Open No. 10-313064. (Patent Document 2). The MOS transistors in the semiconductor devices disclosed in Patent Documents 1 and 2 are both lateral MOS transistors having a planar gate structure (LDMOS, Lateral Diffused Metal Oxide Semiconductor).

On the other hand, it is generally known that crystal defects are likely to occur around the element isolation trench in the element region formed of the SOI layer surrounded by the element isolation trench. When a MOS transistor is formed in a region where crystal defects exist, the characteristics of the semiconductor device deteriorate due to leakage or the like, and the reliability of the semiconductor device decreases.

For this reason, a method for suppressing the occurrence of crystal defects due to the element isolation trench described above is disclosed in, for example, Japanese Patent Application Laid-Open No. 2002-33382 (Patent Document 3). According to the manufacturing method of the disclosed semiconductor device in Patent Document 3, the outside of the device isolation trench surrounding the element region as a non-device forming region, performing high-concentration ion implantation into the non-device forming region. As a result, a large stress is generated by accelerated oxidation at the time of subsequent LOCOS (Local Oxidation of Silicon) oxidation, crystal defects are preferentially generated in the non-device formation region, and the device is surrounded by element isolation trenches. The occurrence of defects in the device region is suppressed.
JP-A-8-213604 Japanese Patent Laid-Open No. 10-313064 JP 2002-33382 A

Although the method for suppressing crystal defects caused by the element isolation trench disclosed in Patent Document 3 can suppress the generation of crystal defects in the element region , the stress accompanying LOCOS oxidation remains in the element region near the element isolation trench. Is inevitable.

As described above, when a large residual stress exists in the element region in the vicinity of the element isolation trench, this residual stress still causes a crystal defect in the manufacturing process after the LOCOS oxidation. In particular, when a MOS transistor having a trench gate structure is formed in the element region , it is considered that the residual stress at the time of LOCOS oxidation correlates with the stress at the time of forming the trench gate, and is likely to cause crystal defects.

Accordingly, the present invention provides a semiconductor device in which each cell of a MOS transistor having a trench gate is dispersedly arranged in an element region formed of an SOI layer surrounded by an element isolation trench, and leaks due to crystal defects, etc. An object of the present invention is to provide a highly reliable semiconductor device and a method for manufacturing the same, in which the characteristic deterioration due to the above is suppressed.

According to the first aspect of the present invention, an element region formed of an SOI layer surrounded by an element isolation trench is divided into an outer shell region adjacent to the element isolation trench and an inner region inside the outer shell region. Each cell of a MOS transistor having a gate is distributed in the inner region, and a dummy gate trench shallower than the element isolation trench is distributed in the outer shell region, the semiconductor device comprising: When the arrangement pitch of the dummy gate trench is in the range of 3.1 μm or more and 5.6 μm or less, and the arrangement pitch of the dummy gate trench is 3.1 μm or more and 4.4 μm or less, the outer shell region And the inner region is at a distance of 30 μm or more from the element isolation trench, and the arrangement pitch of the dummy gate trench is larger than 4.4 μm. When 5.6μm or less, the boundary of the outer shell region and an inner region, is characterized in that from the isolation trenches at a distance of more than 38 [mu] m.

In the semiconductor device, the outer shell region in which the dummy gate trenches are dispersed can be used as a region for actively generating crystal defects. That is, a large amount of crystal defects can be generated in the outer shell region by correlating the residual stress when the element isolation trench is formed with the residual stress when the dummy gate trench is formed. By virtue of the active generation of crystal defects, the semiconductor device can relieve the residual stress in the outer shell region that is generated along with the formation of the element isolation trench. As a result, the occurrence of crystal defects is suppressed under the following conditions in the internal region where the cells of the MOS transistor are distributed and arranged.
When the arrangement pitch of the dummy gate trench and the number of crystal defects generated in the outer shell region where the residual stress accompanying the element isolation trench exists, the arrangement pitch of the dummy gate trench is 3.1 μm or more and 5.6 μm or less. It was found that the generation of crystal defects in the inner region can be suppressed within the range of. When the arrangement pitch of the dummy gate trenches is larger than 5.6 μm, since the effect of mitigating the residual stress accompanying the element isolation trench is small, the number of crystal defects generated is reduced as a whole, but the distance from the element isolation trench is far away. The generation area extends to the inner area. On the other hand, when the arrangement pitch of the dummy gate trenches is smaller than 3.1 μm, crystal defects are generated due to the dummy gate trenches themselves, the crystal defect generation region extends to a distance far from the element isolation trench, and the number of generations is also increased as a whole. Increase.
Based on the above investigation results, in the semiconductor device, when the arrangement pitch of the dummy gate trenches is 3.1 μm or more and 4.4 μm or less, the boundary between the outer shell region and the inner region is 30 μm from the element isolation trench. When the above-mentioned distance is set and the arrangement pitch of the dummy gate trenches is larger than 4.4 μm and smaller than 5.6 μm, the boundary between the outer shell region and the inner region is at a distance of 38 μm or more from the element isolation trench. It is configured. Thereby, generation | occurrence | production of a crystal defect can be suppressed reliably.

  As described above, the semiconductor device is a semiconductor device in which each cell of the MOS transistor having the trench gate is arranged in a distributed manner, and deterioration in characteristics due to leakage at a crystal defect or the like is suppressed, and high reliability is achieved. It can be set as the semiconductor device which has property.

  According to a second aspect of the present invention, in the semiconductor device, the depth of the dummy gate trench is preferably the same depth as the trench gate.

  Thus, as will be described later, the trench gate and the dummy gate trench can be formed simultaneously using the same trench formation step. Accordingly, there is no increase in cost due to the formation of the dummy gate trench, so that an inexpensive semiconductor device can be obtained.

  According to a third aspect of the present invention, the semiconductor device is suitable when a LOCOS is formed on the element isolation trench.

  In the semiconductor device, a large amount of crystal defects can be generated in the outer shell region by correlating the large residual stress at the time of LOCOS oxidation and the residual stress at the time of forming the dummy gate trench. Due to the active generation of the crystal defects, the semiconductor device can sufficiently reduce the large residual stress in the outer shell region generated with the formation of LOCOS.

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According to a fourth aspect of the present invention, for example, the semiconductor device may be configured such that the trench gate has a depth of 5 μm or less.

The invention described in claims 5 and 6 relates to a method of manufacturing the semiconductor device.

According to a fifth aspect of the present invention, an element region composed of an SOI layer surrounded by an element isolation trench is divided into an outer shell region adjacent to the element isolation trench and an inner region inside the outer shell region. Each cell of a MOS transistor having a gate is distributed in the inner region, and a dummy gate trench shallower than the element isolation trench is distributed in the outer shell region, the semiconductor device comprising: When the arrangement pitch of the dummy gate trench is in the range of 3.1 μm or more and 5.6 μm or less, and the arrangement pitch of the dummy gate trench is 3.1 μm or more and 4.4 μm or less, the outer shell region And the inner region is at a distance of 30 μm or more from the element isolation trench, and the arrangement pitch of the dummy gate trench is larger than 4.4 μm. In the case of 5.6 μm or less, in the method of manufacturing a semiconductor device in which the boundary between the outer shell region and the inner region is at a distance of 38 μm or more from the element isolation trench, the trench gate and the dummy gate trench are the same. The trench formation process is used.

  According to this, since a special process for forming the dummy gate trench is not necessary, it is possible to prevent an increase in cost due to the formation of the dummy gate trench.

According to a sixth aspect of the present invention, in the semiconductor device manufacturing method, after the trench formation step, a rapid heating and quenching treatment step by lamp heating is performed under the conditions of a heat treatment temperature of 1150 ° C. or more and a heat treatment time of 10 seconds or more. It is preferable to do.

  By carrying out the rapid heating and quenching treatment process by lamp heating, the amount of crystal defects induced around the dummy gate trench in the outer shell region can be increased, and with this, the residual stress can also be reduced. It can be made more reliable.

  The best mode for carrying out the present invention will be described below with reference to the drawings.

  FIG. 1 is an example of a semiconductor device according to the present invention. FIG. 1A is a schematic top view of the semiconductor device 10, and FIG. 1B is a schematic cross-sectional view of the semiconductor device 10. .

In the semiconductor device 10 shown in FIGS. 1A and 1B, an element region 1 s composed of an SOI (Silicon On Insulator) layer 1 is provided surrounded by an element isolation trench 4 reaching the buried oxide film 2. In the semiconductor device 10, the element region 1s is divided into an outer shell region 1a adjacent to the device isolation trench 2 and an inner region 1b inside the outer shell region 1a, as indicated by a one-dot chain line in the drawing. In the semiconductor device 10, each cell of a MOS (Metal Oxide Semiconductor) transistor having a trench gate 3b is distributed and arranged in the internal region 1b. In addition, dummy gate trenches 3a which are shallower than the depth of the element isolation trench 4 (thickness of the SOI layer 1) d4 and are not connected to the wiring are arranged in a distributed manner in the outer shell region 1a.

  In the semiconductor device 10 of FIG. 1, the outer shell region 1a in which the dummy gate trenches 3a are distributed can be used as a region for actively generating crystal defects. That is, a large amount of crystal defects can be generated in the outer shell region 1a by correlating the residual stress when the element isolation trench 4 is formed with the residual stress when the dummy gate trench 3a is formed. By virtue of the active generation of crystal defects, the semiconductor device 10 can relieve the residual stress in the outer shell region 1a that is generated along with the formation of the element isolation trench 4. As a result, the occurrence of crystal defects is suppressed in the internal region 1b where the cells of the MOS transistor are dispersedly arranged.

  In particular, when a LOCOS (Local Oxidation of Silicon) 5 is formed on the element isolation trench 4 as in the semiconductor device 10 of FIG. 1, a large residual stress is generated around the element isolation trench 4 during LOCOS oxidation. appear. Also in this case, in the semiconductor device 10 of FIG. 1, a large amount of crystal defects can be generated in the outer shell region 1a by correlating the large residual stress at the time of LOCOS oxidation and the residual stress at the time of forming the dummy gate trench 3a. . Due to the active generation of the crystal defects, the semiconductor device 10 can sufficiently reduce the large residual stress in the outer shell region 1a generated with the formation of the LOCOS 5.

  As described above, the semiconductor device 10 shown in FIG. 1 is a semiconductor device in which the cells of the MOS transistor having the trench gate 3b are dispersedly arranged, and the characteristic deterioration due to leakage due to crystal defects or the like is caused. A semiconductor device which is suppressed and has high reliability can be obtained.

  In the semiconductor device 10 of FIG. 1, the depth d3a of the dummy gate trench 3a shown in FIG. 1B is preferably the same as the depth d3b of the trench gate 3b. As a result, as will be described later, the trench gate 3b and the dummy gate trench 3a can be formed simultaneously using the same trench formation step. Accordingly, there is no increase in cost due to the formation of the dummy gate trench 3a, so that an inexpensive semiconductor device can be obtained.

  For example, in the semiconductor device 10, the depth of the trench gate 3b and the dummy gate trench 3a can be 5 μm or less.

  2 to 4 are examples of evaluation results related to the semiconductor device 10 of FIG. 1, and the depth of the dummy gate trench 3a is the same as the depth of the trench gate 3b that is generally used, and is shown in FIG. This is a result of investigating the relationship between the distance from the element isolation trench 4 and the number of crystal defects generated by changing the arrangement pitch P of the dummy gate trenches 3a. FIG. 2A shows a case where the dummy gate trench 3a is not formed, and FIG. 2B shows a case where the arrangement pitch P of the dummy gate trench 3a is 5.6 μm. FIG. 3A shows a case where the arrangement pitch P of the dummy gate trenches 3a is 4.4 μm, and FIG. 3B shows a case where the arrangement pitch P of the dummy gate trenches 3a is 3.1 μm. FIG. 4 shows a case where the arrangement pitch P of the dummy gate trenches 3a is 1.8 μm.

  In the evaluation test, as shown in FIGS. 2B, 3A, and 3B, the arrangement pitch P of the dummy gate trenches 3a is 3.1 μm or more and 5.6 μm or less. In this range, it has been found that the occurrence of crystal defects in the internal region 1b can be reliably suppressed. When the arrangement pitch of the dummy gate trenches 3a is larger than 5.6 μm and when the dummy gate trenches 3a are not formed, since the effect of mitigating the residual stress associated with the element isolation trench is small, as shown in FIG. Although the number of generated crystal defects is reduced as a whole, the generation region extends to a distance far from the element isolation trench 4 and reaches the internal region 1b. On the other hand, when the arrangement pitch of the dummy gate trenches 3a is smaller than 3.1 μm, crystal defects are generated by the dummy gate trenches themselves, and as shown in FIG. As it extends, the total number of occurrences also increases. From the above results, in the semiconductor device, the arrangement pitch P of the dummy gate trenches 3a is preferably 3.1 μm or more and 5.6 μm or less.

  In particular, in the samples of FIGS. 3A and 3B, a large amount of crystal defects are generated in a region where the distance from the element isolation trench 4 is smaller than 30 μm, whereas the element isolation trench 4 has a thickness of 30 μm. In the region apart from the above, almost no crystal defects are generated.

Accordingly, in the semiconductor device 10 of FIG.
It is preferable that the distance La from the element isolation trench 4 at the boundary between the outer shell region 1a and the inner region 1b indicated by a one-dot chain line is 30 μm or more. As a result, the occurrence of crystal defects in the internal region 1a where the cells of the MOS transistor are dispersedly arranged can be reliably suppressed.

  Next, a method for manufacturing the semiconductor device 10 shown in FIGS. 1A and 1B will be described.

  FIGS. 5A to 5E and FIGS. 6A to 6D are cross-sectional views for each process showing the method for manufacturing the semiconductor device 10.

  First, as shown in FIG. 5A, an SOI substrate having a buried oxide film 2 is prepared, and the surface of the SOI layer 1 is covered with a thermal oxide film 2 of about 500 mm.

  Next, as shown in FIG. 5B, a photoresist film mask M1 is formed on the thermal oxide film 2s, and boron (B) is selectively ion-implanted at an energy of 40 keV, for example, at about 1 × 10 13 cm −2. Thus, the boron implantation region ip is formed. Next, after removing the photoresist film mask M1, in the same way, phosphorus (P) is selectively ion-implanted at an energy of 100 keV, for example, at about 5 × 10 13 cm −2 to separate a phosphorus implantation region (not shown). Form in position.

  Next, as shown in FIG. 5C, after removing the photoresist film mask, heat treatment is performed in a nitrogen (N 2) atmosphere at, for example, 1150 ° C. for 300 minutes to form a P conductivity type well 1p made of a boron diffusion layer. An N conductivity type well (not shown) made of a phosphorus diffusion layer is formed.

  Next, as shown in FIG. 5D, a silicon nitride (Si3N4) film N1 having a thickness of 150 to 200 nm is formed on the thermal oxide film 2s by LP-CVD (Low Pressure-Chemical Vapor Deposition). To deposit. Subsequently, a photoresist film mask M2 is formed on the silicon nitride film N1. Next, the silicon nitride film N1 and the thermal oxide film 2s are selectively dry-etched using the photoresist film mask M2, and the SOI layer 1 is exposed at a predetermined position.

  Next, as shown in FIG. 5E, after removing the photoresist film mask M2, the SOI layer 1 is dry-etched using the silicon nitride film N1 as a mask to form a trench groove reaching the buried oxide film 2. Subsequently, the damage layer formed by etching formed on the surface of the trench groove is removed by 150 nm using chemical dry etching. Next, a BPSG film 4s having a thickness of 500 nm is formed on the sidewall of the trench groove by, for example, LP-CVD. Thereafter, polysilicon (4p) doped with phosphorus (P) is deposited by LP-CVD to fill the trench groove back. Thereby, the element isolation trench 4 is completed.

  Next, as shown in FIG. 6A, a photoresist film mask M3 is formed on the silicon nitride film N1. Next, the silicon nitride film N1 is selectively dry etched using the photoresist film mask M3 to expose the thermal oxide film 2s at a predetermined position.

  Next, as shown in FIG. 6B, after removing the photoresist film mask M3, thermal oxidation is performed at 1000 ° C. for 400 to 500 minutes, for example, using the silicon nitride film N1 as a mask. As a result, a thick LOCOS 5 is formed.

  Note that a large residual stress is generated in the vicinity of the element isolation trench 4 during the LOCOS oxidation.

  Next, as shown in FIG. 6C, a silicon nitride film N2 is deposited to a thickness of 150 to 200 nm by the LP-CVD method. Subsequently, a photoresist film mask M4 is formed on the silicon nitride film N2. Next, using the photoresist film mask M4, the silicon nitride film N2 and the thermal oxide film 2s are selectively dry etched to expose the SOI layer 1 at a predetermined position.

  Next, as shown in FIG. 6D, after removing the photoresist film mask M4, the SOI layer 1 is dry-etched using the silicon nitride film N2 as a mask to form trench grooves of the trench gate 3b and the dummy gate trench 3a. Form. Subsequently, the damage layer formed by etching formed on the surface of the trench groove is removed by 150 nm using chemical dry etching. Next, the silicon nitride film N2 is etched away with phosphoric acid, and the thermal oxide film 2s is further removed with dilute hydrofluoric acid (HF). Thereafter, thermal oxidation is performed at 1100 ° C., for example, to form a sacrificial oxide film having a thickness of 100 nm, and then the sacrificial oxide film is removed by dilute HF.

  Next, thermal oxidation is performed in an oxygen atmosphere at 1000 ° C., for example, to form a gate oxide film 2t having a predetermined thickness.

  During the gate oxidation, the residual stress at the time of forming the element isolation trench 4 and the residual stress at the time of forming the dummy gate trench 3a are correlated, and a large number of crystal defects are generated in the outer shell region 1a by this stress.

  Thereafter, polysilicon doped with phosphorus (P) is deposited by the LP-CVD method to fill the trench groove. Next, a photoresist film mask is formed on the deposited polysilicon, and the polysilicon deposited on the flat portion is dry-etched to form a gate electrode having a predetermined pattern. Thereby, the trench gate 3b and the dummy gate trench 3a are completed.

  Thereafter, the source and drain (not shown) of the MOS transistor, the interlayer insulating film 6, the wiring 7, and the passivation film 8 are formed through a general process that is usually used.

  Thus, the semiconductor device 10 shown in FIGS. 1A and 1B is completed.

  In the method of manufacturing the semiconductor device 10 shown in FIGS. 5 and 6, the trench gate 3b and the dummy gate trench 3a are formed by using the same trench formation process. According to this, since a special process for forming the dummy gate trench 3a is not necessary, it is possible to prevent an increase in cost due to the formation of the dummy gate trench 3a.

  Further, in the semiconductor device manufacturing method, after the trench formation step shown in FIG. 6D, a rapid heating and quenching treatment step by lamp heating is performed under conditions of a heat treatment temperature of 1150 ° C. or more and a heat treatment time of 10 seconds or more. It is preferable to do. By carrying out this rapid heating and quenching treatment process by lamp heating, the amount of crystal defects induced around the dummy gate trench 3a in the outer shell region 1a can be increased. The reduction effect of can also be made more reliable.

As described above, in the semiconductor device and the manufacturing method thereof according to the present invention, each cell of the MOS transistor having the trench gate 3b is dispersed in the element region 1s including the SOI layer 1 surrounded by the element isolation trench 4. Thus, the semiconductor device 10 is arranged, and the deterioration of characteristics due to leakage due to crystal defects or the like is suppressed, and the semiconductor device 10 has a high reliability and the manufacturing method thereof.

In the example of the semiconductor device of the present invention, (a) is a schematic top view of the semiconductor device 10, and (b) is a schematic cross-sectional view of the semiconductor device 10. FIGS. 1A and 1B show examples of evaluation results regarding the semiconductor device 10 in FIG. 1. FIG. 1A shows a case where the dummy gate trench 3a is not formed, and FIG. 1B shows a case where the arrangement pitch P of the dummy gate trench 3a is 5.6 μm. is there. 1A is an example of an evaluation result regarding the semiconductor device 10 in FIG. 1. FIG. 1A shows the case where the arrangement pitch P of the dummy gate trenches 3a is 4.4 μm, and FIG. 1B shows the arrangement pitch P of the dummy gate trenches 3a. This is the case of 3.1 μm. 1 is an example of the evaluation result regarding the semiconductor device 10 of FIG. 1, in which the arrangement pitch P of the dummy gate trenches 3a is 1.8 μm. (A)-(e) is sectional drawing according to process which shows the manufacturing method of the semiconductor device 10 of FIG. (A)-(d) is sectional drawing according to process which shows the manufacturing method of the semiconductor device 10 of FIG.

DESCRIPTION OF SYMBOLS 10 Semiconductor device 1 SOI layer 1s element area | region 1a Outer shell area | region 1b Inner area | region 2 Embedded oxide film 3a Dummy gate trench 3b Trench gate 4 Element isolation trench 5 LOCOS
La Distance from the element isolation trench at the boundary between the outer shell region and the inner region

Claims (6)

An element region composed of an SOI layer surrounded by the element isolation trench is divided into an outer shell region adjacent to the element isolation trench and an inner region inside the outer shell region,
Each cell of the MOS transistor having a trench gate is distributed and arranged in the internal region,
A semiconductor device in which dummy gate trenches shallower than the element isolation trenches are distributed and arranged in the outer shell region,
An arrangement pitch of the dummy gate trenches is in a range of 3.1 μm or more and 5.6 μm or less,
When the arrangement pitch of the dummy gate trenches is 3.1 μm or more and 4.4 μm or less, the boundary between the outer shell region and the inner region is at a distance of 30 μm or more from the element isolation trench,
When the arrangement pitch of the dummy gate trenches is larger than 4.4 μm and smaller than 5.6 μm, the boundary between the outer shell region and the inner region is at a distance of 38 μm or more from the element isolation trench. A semiconductor device.   The semiconductor device according to claim 1, wherein a depth of the dummy gate trench is the same as that of the trench gate.   The semiconductor device according to claim 1, wherein a LOCOS is formed on the element isolation trench.   The depth of the said trench gate is 5 micrometers or less, The semiconductor device as described in any one of Claim 1 thru | or 3 characterized by the above-mentioned. An element region composed of an SOI layer surrounded by the element isolation trench is divided into an outer shell region adjacent to the element isolation trench and an inner region inside the outer shell region,
Each cell of the MOS transistor having a trench gate is distributed and arranged in the internal region,
A semiconductor device in which dummy gate trenches shallower than the element isolation trenches are distributed and arranged in the outer shell region,
An arrangement pitch of the dummy gate trenches is in a range of 3.1 μm or more and 5.6 μm or less,
When the arrangement pitch of the dummy gate trenches is 3.1 μm or more and 4.4 μm or less, the boundary between the outer shell region and the inner region is at a distance of 30 μm or more from the element isolation trench,
When the arrangement pitch of the dummy gate trench is larger than 4.4 μm and smaller than 5.6 μm, the boundary between the outer shell region and the inner region is a distance of 38 μm or more from the element isolation trench. In the manufacturing method,
The method of manufacturing a semiconductor device, wherein the trench gate and the dummy gate trench are formed using the same trench formation step.   6. The method of manufacturing a semiconductor device according to claim 5, wherein after the trench formation step, a rapid heating and quenching treatment step by lamp heating is performed under a heat treatment temperature of 1150 ° C. or more and a heat treatment time of 10 seconds or more.

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