JP4980616B2 - 半導体チップを製作するための方法 - Google Patents
半導体チップを製作するための方法 Download PDFInfo
- Publication number
- JP4980616B2 JP4980616B2 JP2005367794A JP2005367794A JP4980616B2 JP 4980616 B2 JP4980616 B2 JP 4980616B2 JP 2005367794 A JP2005367794 A JP 2005367794A JP 2005367794 A JP2005367794 A JP 2005367794A JP 4980616 B2 JP4980616 B2 JP 4980616B2
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- layer sequence
- semiconductor layer
- growth substrate
- growth
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
- H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
- H10H20/01—Manufacture or treatment
- H10H20/011—Manufacture or treatment of bodies, e.g. forming semiconductor layers
- H10H20/013—Manufacture or treatment of bodies, e.g. forming semiconductor layers having light-emitting regions comprising only Group III-V materials
- H10H20/0137—Manufacture or treatment of bodies, e.g. forming semiconductor layers having light-emitting regions comprising only Group III-V materials the light-emitting regions comprising nitride materials
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
- H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
- H10H20/01—Manufacture or treatment
- H10H20/011—Manufacture or treatment of bodies, e.g. forming semiconductor layers
- H10H20/018—Bonding of wafers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
- H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
- H10H20/80—Constructional details
- H10H20/81—Bodies
- H10H20/822—Materials of the light-emitting regions
- H10H20/824—Materials of the light-emitting regions comprising only Group III-V materials, e.g. GaP
- H10H20/825—Materials of the light-emitting regions comprising only Group III-V materials, e.g. GaP containing nitrogen, e.g. GaN
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
- H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
- H10H20/80—Constructional details
- H10H20/83—Electrodes
- H10H20/832—Electrodes characterised by their material
- H10H20/835—Reflective materials
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Led Devices (AREA)
- Recrystallisation Techniques (AREA)
- Semiconductor Lasers (AREA)
Description
Claims (15)
- エピタキシャル成長により製作された機能的な半導体層列(2)を有する半導体チップを製作するための方法において、当該方法が、以下の方法ステップ:すなわち、
−成長基板(1)を準備し、
−機能的な半導体層列(2)を成長基板(1)にエピタキシャル成長させ、
−該成長基板(1)の主面(8)に対して平行に位置する分離領域(4)を成長基板(1)にイオン注入によって形成し、この場合、成長基板(1)へのイオン注入をエピタキシャル成長に後続させ、機能的な半導体層列(2)を貫いて行い、
−支持基板(6)を機能的な半導体層列(2)に被着し、
−成長基板(1)の、分離領域(4)から見て支持基板(6)と反対の側の部分を分離領域(4)に沿って分離する
を有していることを特徴とする、半導体チップを製作するための方法。 - 成長基板(1)と機能的な半導体層列(2)とが、主として、同じ格子係数を有している、請求項1記載の方法。
- 成長基板(1)と機能的な半導体層列(2)とが、同じ半導体材料をベースとしている、請求項1または2記載の方法。
- 成長基板(1)と機能的な半導体層列(2)とが、それぞれ窒化物化合物半導体材料から形成されている、請求項3記載の方法。
- 機能的な半導体層列(2)が、放射線放出する活性層(3)を有しており、該活性層(3)が、0≦x≦1、0≦y≦1およびx+y≦1を備えたInxAlyGa1−x−yNを有している、請求項1から4までのいずれか1項記載の方法。
- 成長基板(1)が、GaN基板またはAlN基板である、請求項1から5までのいずれか1項記載の方法。
- 分離領域(4)に沿った成長基板(1)の、分離領域(4)から見て支持基板(6)と反対の側の部分の分離を熱的な剥離によって行う、請求項1から6までのいずれか1項記載の方法。
- 成長基板(1)が、導電性の基板である、請求項1から7までのいずれか1項記載の方法。
- 前記導電性の成長基板(1)が、n型伝導性の基板である、請求項8記載の方法。
- 支持基板(6)が、導電性の基板である、請求項1から9までのいずれか1項記載の方法。
- 前記導電性の支持基板(6)が、p型伝導性の基板である、請求項10記載の方法。
- イオン注入時に水素イオンを注入する、請求項1から11までのいずれか1項記載の方法。
- イオン注入後、機能的な半導体層列(2)の熱処理を行う、請求項1から12までのいずれか1項記載の方法。
- 機能的な半導体層列(2)に、支持基板(6)の被着前に電気的なコンタクト層またはコンタクト層列(5)を設ける、請求項1から13までのいずれか1項記載の方法。
- 機能的な半導体層列(2)が、放射線放出する活性層(3)を有しており、電気的なコンタクト層(5)が、放出された放射線に対するリフレクタとして働く、請求項14記載の方法。
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE102004062290A DE102004062290A1 (de) | 2004-12-23 | 2004-12-23 | Verfahren zur Herstellung eines Halbleiterchips |
| DE102004062290.6 | 2004-12-23 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2006179922A JP2006179922A (ja) | 2006-07-06 |
| JP4980616B2 true JP4980616B2 (ja) | 2012-07-18 |
Family
ID=35840707
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2005367794A Expired - Fee Related JP4980616B2 (ja) | 2004-12-23 | 2005-12-21 | 半導体チップを製作するための方法 |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US7524737B2 (ja) |
| EP (1) | EP1675189A3 (ja) |
| JP (1) | JP4980616B2 (ja) |
| DE (1) | DE102004062290A1 (ja) |
Families Citing this family (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE102005052357A1 (de) | 2005-09-01 | 2007-03-15 | Osram Opto Semiconductors Gmbh | Verfahren zum lateralen Zertrennen eines Halbleiterwafers und optoelektronisches Bauelement |
| DE102005052358A1 (de) * | 2005-09-01 | 2007-03-15 | Osram Opto Semiconductors Gmbh | Verfahren zum lateralen Zertrennen eines Halbleiterwafers und optoelektronisches Bauelement |
| DE102006061167A1 (de) | 2006-04-25 | 2007-12-20 | Osram Opto Semiconductors Gmbh | Optoelektronisches Halbleiterbauelement |
| KR100863805B1 (ko) * | 2007-04-24 | 2008-10-16 | 고려대학교 산학협력단 | 질화물 발광소자 및 그 제조 방법 |
| US7791063B2 (en) * | 2007-08-30 | 2010-09-07 | Intel Corporation | High hole mobility p-channel Ge transistor structure on Si substrate |
| DE102008019268A1 (de) * | 2008-02-29 | 2009-09-03 | Osram Opto Semiconductors Gmbh | Optoelektronisches Bauelement und Verfahren zur Herstellung eines optoelektronischen Bauelements |
| KR101111748B1 (ko) | 2008-11-28 | 2012-03-09 | 삼성엘이디 주식회사 | 수직구조 질화갈륨계 반도체 발광소자의 제조방법 |
| JP2012230969A (ja) * | 2011-04-25 | 2012-11-22 | Sumitomo Electric Ind Ltd | GaN系半導体デバイスの製造方法 |
| DE102011113775B9 (de) | 2011-09-19 | 2021-10-21 | OSRAM Opto Semiconductors Gesellschaft mit beschränkter Haftung | Verfahren zur Herstellung eines optoelektronischen Bauelements |
| FR3109469B1 (fr) * | 2020-04-15 | 2022-04-29 | Centre Nat Rech Scient | Procédé de fabrication d’un dispositif émetteur de rayonnement |
Family Cites Families (24)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2681472B1 (fr) | 1991-09-18 | 1993-10-29 | Commissariat Energie Atomique | Procede de fabrication de films minces de materiau semiconducteur. |
| US5376580A (en) * | 1993-03-19 | 1994-12-27 | Hewlett-Packard Company | Wafer bonding of light emitting diode layers |
| FR2747506B1 (fr) * | 1996-04-11 | 1998-05-15 | Commissariat Energie Atomique | Procede d'obtention d'un film mince de materiau semiconducteur comprenant notamment des composants electroniques |
| DE19640594B4 (de) | 1996-10-01 | 2016-08-04 | Osram Gmbh | Bauelement |
| US6251754B1 (en) * | 1997-05-09 | 2001-06-26 | Denso Corporation | Semiconductor substrate manufacturing method |
| US5882987A (en) * | 1997-08-26 | 1999-03-16 | International Business Machines Corporation | Smart-cut process for the production of thin semiconductor material films |
| FR2775121B1 (fr) * | 1998-02-13 | 2000-05-05 | Picogiga Sa | Procede de fabrication de substrats en film mince de materiau semiconducteur, structures epitaxiales de materiau semiconducteur formees sur de tels substrats, et composants obtenus a partir de ces structures |
| US6346459B1 (en) * | 1999-02-05 | 2002-02-12 | Silicon Wafer Technologies, Inc. | Process for lift off and transfer of semiconductor devices onto an alien substrate |
| DE19959182A1 (de) * | 1999-12-08 | 2001-06-28 | Max Planck Gesellschaft | Verfahren zum Herstellen eines optoelektronischen Bauelements |
| DE10051465A1 (de) * | 2000-10-17 | 2002-05-02 | Osram Opto Semiconductors Gmbh | Verfahren zur Herstellung eines Halbleiterbauelements auf GaN-Basis |
| FR2817394B1 (fr) * | 2000-11-27 | 2003-10-31 | Soitec Silicon On Insulator | Procede de fabrication d'un substrat notamment pour l'optique, l'electronique ou l'optoelectronique et substrat obtenu par ce procede |
| FR2840731B3 (fr) * | 2002-06-11 | 2004-07-30 | Soitec Silicon On Insulator | Procede de fabrication d'un substrat comportant une couche utile en materiau semi-conducteur monocristallin de proprietes ameliorees |
| JP3729065B2 (ja) * | 2000-12-05 | 2005-12-21 | 日立電線株式会社 | 窒化物半導体エピタキシャルウェハの製造方法及び窒化物半導体エピタキシャルウェハ |
| US20030064535A1 (en) * | 2001-09-28 | 2003-04-03 | Kub Francis J. | Method of manufacturing a semiconductor device having a thin GaN material directly bonded to an optimized substrate |
| US6995430B2 (en) * | 2002-06-07 | 2006-02-07 | Amberwave Systems Corporation | Strained-semiconductor-on-insulator device structures |
| US6953736B2 (en) * | 2002-07-09 | 2005-10-11 | S.O.I.Tec Silicon On Insulator Technologies S.A. | Process for transferring a layer of strained semiconductor material |
| JP3997523B2 (ja) * | 2002-11-28 | 2007-10-24 | 信越半導体株式会社 | 発光素子 |
| JP5047609B2 (ja) * | 2003-01-07 | 2012-10-10 | ソワテク | 除去構造を含んでなるウェハーの、その薄層を除去した後の、機械的手段による循環使用 |
| DE10350707B4 (de) * | 2003-02-26 | 2014-02-13 | Osram Opto Semiconductors Gmbh | Elektrischer Kontakt für optoelektronischen Halbleiterchip und Verfahren zu dessen Herstellung |
| TWI243488B (en) | 2003-02-26 | 2005-11-11 | Osram Opto Semiconductors Gmbh | Electrical contact-area for optoelectronic semiconductor-chip and its production method |
| US7348260B2 (en) * | 2003-02-28 | 2008-03-25 | S.O.I.Tec Silicon On Insulator Technologies | Method for forming a relaxed or pseudo-relaxed useful layer on a substrate |
| TWI240434B (en) | 2003-06-24 | 2005-09-21 | Osram Opto Semiconductors Gmbh | Method to produce semiconductor-chips |
| DE102004030063A1 (de) | 2004-06-23 | 2006-03-16 | Heinz Leiber | Permanentmagneterregte Drehfeldmaschine |
| US6893936B1 (en) * | 2004-06-29 | 2005-05-17 | International Business Machines Corporation | Method of Forming strained SI/SIGE on insulator with silicon germanium buffer |
-
2004
- 2004-12-23 DE DE102004062290A patent/DE102004062290A1/de not_active Withdrawn
-
2005
- 2005-12-05 EP EP05026485A patent/EP1675189A3/de not_active Withdrawn
- 2005-12-20 US US11/314,447 patent/US7524737B2/en not_active Expired - Fee Related
- 2005-12-21 JP JP2005367794A patent/JP4980616B2/ja not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JP2006179922A (ja) | 2006-07-06 |
| US7524737B2 (en) | 2009-04-28 |
| EP1675189A2 (de) | 2006-06-28 |
| US20060172506A1 (en) | 2006-08-03 |
| DE102004062290A1 (de) | 2006-07-06 |
| EP1675189A3 (de) | 2007-11-07 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP5021302B2 (ja) | 半導体チップの製造方法 | |
| JP4458116B2 (ja) | エピタキシャル層成長用iii族窒化物半導体層貼り合わせ基板および半導体デバイス | |
| US8541290B2 (en) | Optoelectronic substrate and methods of making same | |
| JP4177097B2 (ja) | Iii−v窒化物半導体ベースの放射線を発する半導体チップを製造する方法および放射線を発する半導体チップ | |
| JP5003033B2 (ja) | GaN薄膜貼り合わせ基板およびその製造方法、ならびにGaN系半導体デバイスおよびその製造方法 | |
| JP2004512688A (ja) | GaNベースの半導体デバイスを製造する方法 | |
| TWI532209B (zh) | 一種用於形成一埋入式金屬層結構的方法 | |
| JP2007067418A (ja) | 二重ヘテロ構造の発光領域を有するiii族窒化物発光デバイス | |
| JP6148756B2 (ja) | オプトエレクトロニクス半導体チップ | |
| KR20150003359A (ko) | GaN계 반도체 디바이스의 제조방법 | |
| JP2014060294A (ja) | Led素子及びその製造方法 | |
| JP2014528178A (ja) | オプトエレクトロニクス半導体チップの製造方法および対応するオプトエレクトロニクス半導体チップ | |
| JP4980616B2 (ja) | 半導体チップを製作するための方法 | |
| KR20090105462A (ko) | 수직구조 그룹 3족 질화물계 반도체 발광다이오드 소자 및이의 제조 방법 | |
| JP2010226023A (ja) | 窒化物系化合物半導体層を支持基板上に有する基板生産物を製造する方法、及び半導体デバイスの製造方法 | |
| KR20090106294A (ko) | 수직구조 그룹 3족 질화물계 반도체 발광다이오드 소자 및이의 제조 방법 | |
| JP2009260391A (ja) | Iii族窒化物半導体層貼り合わせ基板および半導体デバイスの製造方法 | |
| JP4508021B2 (ja) | 半導体発光素子の製造方法 | |
| KR100945984B1 (ko) | 반도체 발광 다이오드 제조 방법 | |
| JP2014175335A (ja) | 複合積層基板およびiii族窒化物半導体デバイスの製造方法 | |
| HK1125229A (en) | Iii-v nitride semiconductor layer-bonded substrate and semiconductor device | |
| HK1117270B (en) | Substrate and method of fabricating the same, and semiconductor device and method of fabricating the same |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20081218 |
|
| RD04 | Notification of resignation of power of attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7424 Effective date: 20101228 |
|
| A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20110824 |
|
| A601 | Written request for extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A601 Effective date: 20111114 |
|
| A602 | Written permission of extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A602 Effective date: 20111117 |
|
| A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20120224 |
|
| TRDD | Decision of grant or rejection written | ||
| A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20120328 |
|
| A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 |
|
| A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20120419 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20150427 Year of fee payment: 3 |
|
| R150 | Certificate of patent or registration of utility model |
Ref document number: 4980616 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| LAPS | Cancellation because of no payment of annual fees |