JP4915127B2 - Solid-state imaging device - Google Patents

Description

  The present invention relates to a solid-state imaging device, and more particularly to a solid-state imaging device including a conversion unit that converts a charge generated by a photoelectric conversion element into a pixel signal in a pixel, such as a CMOS image sensor. Here, the CMOS image sensor is an image sensor manufactured by applying or partially using a CMOS process.

  The CMOS image sensor is a solid-state imaging device in which a plurality of pixels each including a photoelectric conversion element and a plurality of MOS transistors are arranged in a two-dimensional array, and charges generated by the photoelectric conversion element are converted into pixel signals and read. In recent years, this CMOS image sensor has attracted attention as an imaging device such as a camera for a mobile phone, a digital still camera, or a digital video camera.

  FIG. 8 shows an example of a general CMOS image sensor. The CMOS image sensor 1 includes, for example, an imaging region 4 in which a plurality of pixels (unit cells) 3 each including a photoelectric conversion element 2 including a photodiode and a plurality of MOS transistors are arranged in a two-dimensional array, and a peripheral area. Circuit.

  The photoelectric conversion element 2 accumulates signal charges generated by photoelectric conversion upon receiving light. In this example, the plurality of MOS transistors are composed of four transistors: a transfer transistor 6, a reset transistor 7, an amplification transistor 8, and a selection transistor 9. The transfer transistor 6 is a transistor for transferring the signal charge accumulated in the photoelectric conversion element 2 to the floating diffusion (FD), and thus to the gate of the amplifying transistor 8. The resetting transistor 7 is a transistor for resetting the gate potential of the amplifying transistor 8. The amplifying transistor 8 is a transistor for amplifying the signal charge. The selection transistor 9 is a transistor for selecting an output pixel.

  In the pixel 3, the source of the transfer transistor 6 is connected to the photoelectric conversion element 2, and the drain thereof is connected to the source of the reset transistor 7. A transfer signal line 11 for controlling the gate potential is connected to the gate of the transfer transistor 6. The reset transistor 7 has a drain connected to the power supply potential supply line 10 and a gate connected to a reset signal line 12 for controlling the gate potential. The amplifying transistor 8 has its drain connected to the power supply potential supply line 10, its source connected to the drain of the selection transistor 9, and its gate connected to the floating diffusion (transfer transistor 6 and resetting transistor 7). FD). The selection transistor 9 has a source connected to the pixel output line 14 and a gate connected to a selection signal line 13 for controlling the gate potential.

  A transistor 16 for supplying a constant current is connected to the pixel output line 14, a constant current is supplied to the selected amplifying transistor 8, the amplifying transistor 8 is operated as a source follower, and the gate of the amplifying transistor 8 is A potential and a potential having a certain voltage difference appear on the pixel output line 14. A constant potential supply line 17 for supplying a constant potential is connected to the gate of the transistor 16 so as to perform a saturation region operation so that the transistor 16 supplies a certain current.

  On the other hand, a vertical selection unit 21, a column selection unit 22, and a CDS (correlated double sampling) circuit 23 are arranged as peripheral circuits. Further, for each row of the pixels 3, the row selection AND element 25 whose output end is connected to the transfer signal line 11, the row selection AND element 26 whose output end is connected to the reset signal line 12, and the output end are selected. Row selection AND elements 27 connected to the signal lines 13 are respectively arranged.

  A pulse terminal 28 for supplying a transfer pulse to the transfer signal wiring 11 is connected to one of the row selection AND elements 25 of each row, and an output from the vertical selection means 21 is connected to the other input end. Connected. A pulse terminal 29 for supplying a reset pulse to the reset signal wiring 12 is connected to one input end of the row selection AND element of each row, and an output from the vertical selection means 21 is connected to the other input end. The A pulse terminal 30 for supplying a selection pulse to the selection signal line 13 is connected to one input terminal of the row selection AND element 27 of each row, and an output from the vertical selection means 21 is connected to the other input terminal. Connected.

  With such a configuration, each control pulse is supplied only to each signal wiring in the row selected by the vertical selection means 21. The readout operation from each pixel 3 is performed as follows by adding the drive signal shown in FIG.

  The transfer signal (pulse) S1 in FIG. 9 is supplied to the transfer signal wiring 11, the reset signal (pulse) S2 is supplied to the reset signal wiring 12, and the selection signal (pulse) S3 is supplied to the selection signal wiring 13.

  First, the selection pulse S3 and the reset pulse S2 are supplied to make the selection transistor 9 and the reset transistor 7 in the row to be read out conductive, and the gate of the amplification transistor 8 (so-called floating diffusion FD). Reset the potential. After the reset transistor 7 is turned off, a voltage corresponding to the reset level of each pixel 3 is read out to the CDS circuit 23 in the subsequent stage. Next, the transfer pulse S3 is supplied to make the transfer transistor 6 conductive, and the charge accumulated in the photoelectric conversion element 2 is transferred to the floating diffusion (FD), and hence to the gate of the amplification transistor 8. After the transfer is completed, the transfer transistor 6 is turned off, and the voltage of the signal level corresponding to the accumulated charge amount is read out to the subsequent circuit 23.

  The CDS circuit 23 takes the difference between the reset level read out earlier and the signal level, and cancels fixed pattern noise generated due to variations in the threshold voltage Vth of the amplifying transistor for each pixel. When the signal stored in the CDS circuit 23 is selected by the column selection means 22, it is read through a horizontal signal line 24 to a subsequent circuit such as AGC (automatic gain control) and processed.

  As described above, in the CMOS image sensor, in addition to the photoelectric conversion element 2 in one pixel, a plurality of transistors for reading out charges accumulated in the photoelectric conversion element 2, and a control signal for controlling each transistor Wiring is required. Therefore, it is difficult to reduce the pixels as compared with a CCD image sensor having a simple structure. Up to now, by changing the driving method as shown in FIG. 10, the selection transistor is eliminated and the pixel configuration is simplified (see Patent Document 1), or a plurality of photoelectric conversions as shown in FIG. A pixel in which one amplification transistor is used for reading from the element has been proposed.

  The pixel 33 in FIG. 9 includes one photoelectric conversion element (photodiode) 2 and three MOS transistors, that is, a transfer transistor 6, a reset transistor 7, and an amplification transistor 8. The transfer transistor 6 has a source connected to the photoelectric conversion element 2, a drain connected to the source of the reset transistor 7, and a gate of the amplification transistor 8. A transfer signal line 11 is connected to the gate of the transfer transistor 6. The reset transistor 7 has a drain connected to a selection signal line 34 shared with a power supply line connected to the drain of the amplifying transistor 8, and a gate connected to the pixel output line 14. The source of the amplifying transistor 8 is connected to the pixel output line 14.

  The unit cell 41 of FIG. 11 is configured to form transfer transistors corresponding to two photoelectric conversion elements corresponding to two pixels, and share a reset transistor and an amplification transistor. . That is, the unit cell 41 includes an upper photoelectric conversion element 42 and a lower photoelectric conversion element 43, and the respective photoelectric conversion elements 42 and 43 are connected to the sources of the transfer transistors 44 and 45. The drain of 45 is connected to the source of the resetting transistor shared by the drain and the gate of the amplifying transistor 47. The drain of the reset transistor 46 and the drain of the amplification transistor 47 are connected to the power supply line 53, and the source of the amplification transistor 47 is connected to the pixel output line 48. Transfer signal lines 48 and 49 are connected to the gates of the transfer transistors 44 and 45, respectively, and a gate of the reset transistor 46 is connected to the reset signal line 50. Further, a capacitor 52 is connected between the floating diffusion (FD) and the capacitor kick wiring 51.

Japanese Patent Laid-Open No. 2002-77731

  By sharing the reset transistor 46 and the amplifying transistor 47 as in the pixel configuration of FIG. 11, the number of elements in one pixel can be reduced, and the pixel size can be reduced. However, in the unit cells shown in FIGS. 8 and 10 (so-called one pixel 3, 33), all the pixels in the light receiving surface have one shape, but the unit cells 41 shown in FIG. 11 are arranged side by side. The received light receiving surface is composed of two types of pixels. That is, in FIG. 8 and FIG. 10, the photoelectric conversion elements are arranged at equal intervals, whereas in FIG. 11, the photoelectric conversion elements 42 and 43 are arranged at non-equal intervals in the vertical direction of the light receiving surface.

  Therefore, in the image sensor in which the unit cells 41 in FIG. 11 are arranged, characteristics such as sensitivity, saturation, color mixture, shading, and the like are different between the two types of pixels. For example, when color coding is performed by the Bayer method, even if pixels are coded with the same green color (G), the pixel characteristics differ depending on the row, so that there is a problem that horizontal stripes are generated when viewed as one image. This problem is not only a problem of the unit cell of FIG. 11, but a problem associated with sharing of the inter-pixel transistors regardless of the number of transistors and the configuration.

  FIG. 12 shows a layout of an imaging surface (light receiving surface) of a CMOS image sensor in which a plurality of unit cells 41 of FIG. 11 are arranged. As shown in FIG. 12, a transistor region 54 is formed between the upper and lower photoelectric conversion elements 42 and 43 in the unit cell 41. In this transistor region 54, a reset transistor 46 and an amplification transistor 47 are formed. Since the shared transistor region 54 is formed in this way, the photoelectric conversion elements 42 and 43 are arranged at unequal intervals in the vertical direction of the imaging surface. That is, the arrangement pitch P1 of the photoelectric conversion elements 42 and 43 in the unit cell 41 and the arrangement pitch P2 of the photoelectric conversion elements 42 and 43 between the unit cells 41 are different (P1> P2).

  Thus, the region adjacent to the lower side of the upper photoelectric conversion element 42 is the transistor region 54, and the region adjacent to the lower side of the transistor region 54 is the lower photoelectric conversion element 43. Therefore, the upper photoelectric conversion element 42 and the lower photoelectric conversion element 43 cannot be made to have exactly the same shape because the elements adjacent to the upper and lower sides are different. As described above, the sensitivity, saturation, color mixture, Characteristics such as shading will be different.

  In particular, color mixing when light is incident obliquely on the imaging surface will be described with reference to the schematic diagram of FIG. 13 showing the AA cross-sectional structure of FIG.

  In the configuration of FIG. 13, for example, a first p-type semiconductor well region 57 is formed on an n-type silicon semiconductor substrate 56, and upper and lower photoelectric conversion elements 42 and 43 are formed on the substrate surface side. Transistor region 54 is formed. Further, a second p-type semiconductor well region 58 for separating the photoelectric conversion elements 42 and 43 between the unit cells 41 so as to reach the first p-type semiconductor well region 57 from the substrate surface, and in the unit cell 41 The second p-type semiconductor well region 59 for separating the photoelectric conversion elements 42 and 43 and the transistor region 54 is formed.

  In the transistor region 54, a reset transistor 46 and an amplification transistor 47 are formed. The photoelectric conversion elements 42 and 43 are schematically shown as regions having a pn junction and an n-type charge accumulation region. The lower portions of the photoelectric conversion elements 42 and 43 are formed by n-type regions 42 a and 43 a that reach the first p-type semiconductor well region 57 continuously from the n-type charge accumulation region. Each of the second p-type semiconductor well regions 58 and 59 is formed at a portion deeper than the region of the photoelectric conversion elements 42 and 43 on the substrate surface with the same width w1 and at an equal interval W2. Although not shown, multilayer wiring, color filters, and on-chip lenses are formed on this substrate.

  In the CMOS image sensor having the layout of FIGS. 12 and 13, the light transmitted through each color filter is collected at the center of each photoelectric conversion element 42, 43, but the light having a long wavelength characteristic is the photoelectric conversion element 42, 43 is not absorbed by the surface portion 43 but has energy up to a deep portion of the silicon substrate. Electric charges (that is, electrons) collected and generated by the photoelectric conversion elements 42 and 43 are accumulated in the n-type accumulation regions of the photoelectric conversion elements 42 and 43. However, the electrons photoelectrically converted in the second p-type semiconductor well regions 58 and 59 are determined in the movement destination, that is, in the storage region of which photoelectric conversion element 42 or 43, depending on the potential gradient.

  As shown in FIG. 13, when oblique light L is incident on the upper photoelectric conversion element 42 and the lower photoelectric conversion element 43, the second p-type semiconductor well in the deep portion is caused by the light L incident on the upper photoelectric conversion element 42. Most of the electrons photoelectrically converted in the region 59 are accumulated in the upper photoelectric conversion element 42. On the other hand, the electrons photoelectrically converted in the deep second p-type semiconductor well region 58 by the light L incident on the lower photoelectric conversion element 43 move toward the adjacent upper photoelectric conversion element 42. The ratio to do increases.

  As a result, with respect to the incident light L at an angle as shown in FIG. 13, the color mixture amount from the upper photoelectric conversion element 42 to the lower photoelectric conversion element 43 is changed from the lower photoelectric conversion element 43 to the adjacent upper photoelectric. The amount of color mixture to the conversion element 42 is larger. Such a difference in color mixing characteristics between the upper photoelectric conversion element 42 and the lower photoelectric conversion element 43 causes image deterioration as horizontal stripes. Further, it has reverse color mixing characteristics for light having a reverse incident angle.

  In view of the above, the present invention provides a solid-state imaging device that suppresses characteristic differences such as color mixing characteristic differences and improves image quality.

The solid-state imaging device according to the present invention has an imaging region in which unit cells each having a plurality of photoelectric conversion elements and means for reading signal charges of the photoelectric conversion elements are arranged in a two-dimensional array, A semiconductor well region for separating elements is formed, and the semiconductor well region for separating deep portions of the photoelectric conversion element is formed of at least two types of semiconductor well regions having different widths. That is, a photoelectric conversion element arranged in a two-dimensional array and a region where a plurality of transistors are arranged, and is sandwiched between two photoelectric conversion elements arranged in one direction among the photoelectric conversion elements. A transistor region that constitutes a unit cell together with the two photoelectric conversion elements, and a region that separates the transistor region and the photoelectric conversion element, and is disposed deeper than the transistor region and the photoelectric conversion element. The portion of the lower portion of the photoelectric conversion element provided between the first conductivity type regions arranged continuously from the first conductivity type charge storage region constituting the photoelectric conversion element and separating the transistor region A second conductivity type semiconductor window in which the width in one direction is set to be larger than the width in the one direction at the portion separating the photoelectric conversion elements between the unit cells. And a cell area.

  In the solid-state imaging device of the present invention, element isolation semiconductor well regions in an imaging region in which unit cells having a plurality of photoelectric conversion elements are arranged in a two-dimensional array are formed by at least two types of semiconductor well regions having different widths. Thus, the amount of charge photoelectrically converted in the semiconductor well region is controlled, and characteristic differences such as color mixing characteristic differences between pixels are suppressed.

  According to the solid-state imaging device according to the present invention, it is possible to suppress a characteristic difference such as a color mixing characteristic difference between pixels, and to improve image quality.

  Embodiments of the present invention will be described below with reference to the drawings.

  The embodiment of the solid-state imaging device according to the present invention has a unit having a plurality of photoelectric conversion elements and means for reading signal charges of the photoelectric conversion elements, that is, signal charge reading means shared by the plurality of photoelectric conversion elements. This is a CMOS image sensor as a cell.

  1 to 3 show an embodiment of a solid-state imaging device according to the present invention. As shown in FIGS. 1 and 2, the solid-state imaging device 60 according to the present embodiment includes the unit cell shown in FIG. 3, that is, two photoelectric conversion elements 62 and 62, for example, photodiodes, and this photoelectric conversion element. A unit cell 61 that shares a reset transistor 66 and an amplification transistor 67 with respect to 62 and 63 is configured to have an imaging region 72 in which a plurality of unit cells 61 are arranged in a two-dimensional array. In this example, an apparent pixel is composed of one photoelectric conversion element and three MOS transistors, a transfer transistor, a reset transistor, and an amplification transistor. As described with reference to FIG. 8, the peripheral circuit of the imaging region 72 is formed with a vertical selection unit, a column selection unit, a CDS circuit, and the like, and a pixel signal is read out through a horizontal signal line.

  The unit cell 61 in FIG. 3 includes an upper photoelectric conversion element 62 and a lower photoelectric conversion element 63 made of photodiodes, two transfer transistors 64 corresponding to the upper photoelectric conversion element 62 and the lower photoelectric conversion element 63, and 65, and a reset transistor 66 and an amplification transistor 67 shared by two photoelectric conversion elements 62 and 63 (so-called two pixels). As described above, the upper photoelectric conversion element 62 and the lower photoelectric conversion element 63 are connected to the sources of the corresponding transfer transistors 64 and 65, respectively. The drains of the transfer transistors 64 and 65 are connected to the source of the shared reset transistor 66, and the floating point is a connection midpoint between the source of the reset transistor 66 and the drain of the transfer transistors 64 and 65. A diffusion (FD) is connected to the gate of the amplifying transistor 67. The drain of the reset transistor 66 and the drain of the amplification transistor 67 are connected to the power supply line 71, and the source of the amplification transistor 67 is connected to the pixel output line 73. The gates of the transfer transistors 64 and 65 are connected to transfer signal lines 68 and 69, respectively, and the gate of the reset transistor 66 is connected to a reset signal line 70. Note that, as shown in FIG. 11 described above, a capacitor kick wiring may be provided, and a capacitor may be connected between the capacitor kick wiring and the floating diffusion (FD).

  FIG. 1 is a layout schematically showing an imaging surface (light receiving surface) of an imaging region 72 in which a plurality of unit cells 61 are arranged in a two-dimensional array. The layout of this imaging surface is the same as that in FIG. That is, the unit cell 61 is separated by a semiconductor well region 76 to be described later, and is formed between the upper photoelectric conversion element 62, the lower photoelectric conversion element 63, and the upper and lower photoelectric conversion elements 62 and 63 in the unit cell 61. Transistor regions 74 are separated from each other by a semiconductor well region 76. The photoelectric conversion elements 62 and 63 and the transistor region 74 are arranged at equal intervals in the horizontal direction of the imaging surface. However, since the upper and lower photoelectric conversion elements 62 and 63 in the unit cell 61 are formed with the transistor region 74 interposed therebetween, the photoelectric conversion elements 62 and 63 are arranged at unequal intervals in the vertical direction of the imaging surface. That is, the arrangement pitch P3 of the photoelectric conversion elements 62 and 63 in the unit cell 61 is different from the arrangement pitch P4 of the photoelectric conversion elements 62 and 63 between the unit cells 61. That is, the arrangement pitch P3 is larger than the arrangement pitch P4 (P3> P4).

  In the present embodiment, the semiconductor well region 76 between the photoelectric conversion elements 62 and 63 [76A, 76B], particularly as shown in the cross-sectional structure of FIG. 2 (cross-sectional view along the line BB in FIG. 1). The widths W3 and W4 are made different according to the arrangement pitches P3 and P4 of the photoelectric conversion elements 62 and 63 on the surface. That is, as will be described later, the semiconductor well region 76 includes two types of semiconductor well regions 76A and 76B having different widths at portions deeper than the photoelectric conversion elements 62 and 63 on the substrate surface side.

  In FIG. 2, a first second conductivity type, for example, a p-type semiconductor well region 82 is formed deep in a first conductivity type semiconductor substrate, in this example, an n-type silicon semiconductor substrate 81. An upper photoelectric conversion element 62 and a lower photoelectric conversion element 63 are formed on the surface side, and a transistor region 74 sandwiched between the photoelectric conversion elements 62 and 63 in the unit cell 61 is formed. In addition, a second p-type semiconductor well region 76B that separates the photoelectric conversion elements 62 and 63 between the unit cells 61 so as to be continuous from the substrate surface to the first p-type semiconductor well region 82; The photoelectric conversion elements 62 and 63 and the second semiconductor well region 76A that separates the transistor region 74 are formed.

  In the transistor region 74, a reset transistor 66 and an amplification transistor 67 are formed. The photoelectric conversion elements 62 and 63 are schematically shown as regions having a pn junction and an n-type charge accumulation region. The lower portions of the photoelectric conversion elements 62 and 63 are formed of n-type regions 62a and 63a that reach the first p-type semiconductor well region 82 continuously from the n-type charge accumulation region. The transfer transistors 64 and 65 are formed across the photoelectric conversion elements 62 and 63 and the transistor region 74.

  The width of the second p-type semiconductor well region 76A corresponding to the transistor region 74 in the unit cell 61, that is, the width W3 of the portion deeper than the photoelectric conversion elements 62 and 63 on the substrate surface side is wide. The width of the corresponding second p-type semiconductor well region 76B, that is, the width W4 of the portion deeper than the photoelectric conversion elements 62 and 63 on the substrate surface side is formed narrow. That is, the width W3 is formed wider than the width W4 (W3> W4). In other words, the second p-type semiconductor well regions 76A and 76B are arranged at unequal intervals in the vertical direction of the imaging surface. The widths W5 of the second p-type semiconductor well regions 76 [76A, 76B] facing the surface are both formed to be the same. In addition, since the transistor region 74 is formed, the photoelectric conversion elements 62 and 63 are arranged at unequal intervals in the vertical direction of the imaging surface. The widths of the surface portions of the photoelectric conversion elements 62 and 63 are formed with the same width W6, and the deep portions of the n-type regions 62a and 63a are formed with the same width W7.

  Although not shown, multilayer wiring, color filters, on-chip lenses and the like are formed on the substrate of FIG.

  In the solid-state imaging device according to the present embodiment, the light that has passed through each color filter is collected at the centers of the photoelectric conversion elements 62 and 63. As described above, light having long wavelength characteristics is not absorbed by the surface portions of the photoelectric conversion elements 62 and 63, and has energy up to a deep portion of the silicon substrate. As shown in FIG. 2, when the oblique light L is incident, the light L incident on the upper photoelectric conversion element 62 reaches the second p-type semiconductor well region 76A, but the second p-type semiconductor well region 76A. As in the case described with reference to FIG. 13, most of the electric charges generated in (1) are accumulated in the upper photoelectric conversion element 62. Here, the light L incident on the second p-type semiconductor well region 76A is at a position close to the n-type region 62a of the second p-type semiconductor well region 76A. Therefore, most of the electrons photoelectrically converted here. Is accumulated in the photoelectric conversion element 62. Accordingly, there is little color mixing in the lower photoelectric conversion element 63.

  On the other hand, the light L incident on the lower photoelectric conversion element 63 reaches the second p-type semiconductor well region 76B. Since the p-type semiconductor well region 76B itself is a narrow region, the light L enters the second p-type semiconductor well region 76B. The amount of electrons subjected to photoelectric conversion is reduced, and the amount of electrons moving to the upper photoelectric conversion element 62 is small. Here, if the light L incident on the second p-type semiconductor well region 76B has the same distance as the light L incident on the upper photoelectric conversion element 62, in the case of FIG. Even in the vicinity of the center of 76B, since the width of the p-type semiconductor well region 76B itself is narrow, the amount of electrons photoelectrically converted here is reduced. Therefore, the amount of electrons moving to the upper photoelectric conversion element 62 is reduced. Electrons photoelectrically converted in a portion other than the second p-type semiconductor well region 76B (for example, the n-type region 63a) are accumulated in the lower photoelectric conversion element 63. As a result, the color mixing characteristic difference between the upper photoelectric conversion element 62 and the lower photoelectric conversion element 63 is suppressed, and the color mixing characteristics of both the photoelectric conversion elements 62 and 63 can be made uniform. Since leakage of charges to adjacent photoelectric conversion elements is suppressed in this way, characteristic differences such as sensitivity, saturation, color mixing, and shading can be suppressed.

  A method for forming the second p-type semiconductor well region 76 [76A, 76B] will be described. In the first method, after the first p-type semiconductor well region 82 is formed by ion implantation in the n-type semiconductor substrate 81, the second p-type semiconductor well region 76 [76A, 76B] is formed by ion implantation. Thereafter, photoelectric conversion elements 62 and 63 are formed, and a reset transistor 66 and an amplification transistor 67 are formed in the second p-type semiconductor well region 76A.

  In the second method, a first p-type semiconductor well region 82 is formed on an n-type semiconductor substrate 81 by ion implantation, and then a second semiconductor well region 76 is formed on the entire surface by ion implantation. Thereafter, n-type regions 62a and 63a, photoelectric conversion elements 62 and 63, and a transistor region 74 are formed through a resist mask so as to cancel the p-type impurities.

  In the above example, the unit cell is configured to have two photoelectric conversion elements on the upper and lower sides. However, a unit cell having three or more photoelectric conversion elements and a shared transistor can also be applied. For example, FIGS. 4 to 6 show an embodiment in which the present invention is applied to a solid-state imaging device in which unit cells sharing transistors with four photoelectric conversion elements are arranged in a two-dimensional array.

  FIG. 6 shows a unit cell. The unit cell 84 includes, for example, four photoelectric conversion elements 85, 86, 87, 88 made of photodiodes, four transfer transistors 89, 90, 91, 92, and a reset transistor shared by so-called four pixels. 93 and an amplifying transistor 94. The four photoelectric conversion elements 85 to 88 are connected to the sources of the corresponding transfer transistors 89 to 92, respectively. The drains of the transfer transistors 89 to 92 are connected to the source of the shared reset transistor 93, and are floating floating points that are connection midpoints between the source of the reset transistor 93 and the drains of the transfer transistors 85 to 88. A diffusion (FD) is connected to the gate of the amplifying transistor 94. The drain of the reset transistor 93 and the drain of the amplification transistor 94 are connected to the power supply line 95, respectively, and the source of the amplification transistor 94 is connected to the pixel output line 96. The gates of the transfer transistors 85 to 88 are connected to the transfer signal lines 101 to 104, and the gate of the reset transistor 93 is connected to the reset signal line 105.

  The solid-state imaging device 83 of the present embodiment is configured by arranging a plurality of unit cells 84 in a two-dimensional array. FIG. 4 schematically shows an imaging surface (light receiving surface) of the imaging region 106 in which the unit cells 84 are arranged in a two-dimensional array. The layout of the imaging surface is that two unit cells 84 each including a transistor region 107 and two upper photoelectric conversion elements 85 and 86 and two lower photoelectric conversion elements 87 and 88 arranged with the transistor region 107 interposed therebetween. Arranged in a dimensional array. The semiconductor well region 76 separates the unit cells 84, the transistor region 107 in the unit cell 84, and the four photoelectric conversion elements 85 to 88. The shared reset transistor 93 and amplifying transistor 94 are formed in the transistor region 107, and the transfer transistors 89 to 92 are respectively formed from the corresponding photoelectric conversion elements 85 to 88 across the transistor region 107. . The arrangement pitch of the photoelectric conversion elements 85 to 88 in the unit cell 84 is P5, and the arrangement pitch of the photoelectric conversion elements 85 to 88 between the unit cells 84 is P6, and P5> P6.

  FIG. 5 shows a cross-sectional structure taken along the line CC in FIG. 5 is basically the same as the configuration described with reference to FIG. 2 described above, the same reference numerals are given to portions corresponding to FIGS. The width of the second p-type semiconductor well region 76A corresponding to the transistor region 107 in the unit cell 84, that is, the width W8 of the portion deeper than the region of the photoelectric conversion element on the substrate surface side is wide. The width of the second p-type semiconductor well region 76B, that is, the width W9 of the portion deeper than the region of the photoelectric conversion element on the substrate surface side is formed narrow. Accordingly, the width W7 is formed wider than the width W9 (W8> W9). In other words, the second p-type semiconductor well regions 76A and 76B are arranged at unequal intervals in the vertical direction of the imaging surface. The second p-type semiconductor well region 76 [76A, 76B] facing the surface is formed to have the same width W10. In addition, since the transistor region 107 is formed, the photoelectric conversion elements 85 to 88 are arranged at unequal intervals in the vertical direction of the imaging surface. The widths of the surface portions of the photoelectric conversion elements 85 to 88 are formed with the same width W11, and the widths of the deep n-type regions 85a to 88a are formed with the same width W12.

  Also in the solid-state imaging device 83 of the present embodiment, the color mixing characteristics of the upper photoelectric conversion elements 85 and 86 and the lower photoelectric conversion elements 87 and 88 can be made uniform as described in the previous embodiment. Since leakage of charges to adjacent photoelectric conversion elements is suppressed in this way, characteristic differences such as sensitivity, saturation, color mixing, and shading can be suppressed.

  As described above, according to the solid-state imaging device according to the present embodiment, that is, the CMOS image sensor, the unit cell is configured by the resetting transistor and the amplifying transistor serving as charge reading means shared with the plurality of photoelectric conversion elements. Therefore, the pixel size can be reduced. Then, in the entire imaging region, two types of semiconductor well regions separating the photoelectric conversion elements are formed at non-equal intervals in the same manner as the photoelectric conversion elements on the surface side, so that the photoelectric conversion elements are separated in the semiconductor well region. The amount of converted electrons that flow into the adjacent photoelectric conversion element and become mixed colors can be suppressed. This makes it possible to align color mixing characteristics between adjacent pixels. Since leakage of charges to adjacent photoelectric conversion elements is suppressed in this way, characteristic differences such as sensitivity, saturation, color mixing, and shading can be suppressed. As a result, high image quality can be achieved.

  In addition, it is possible to suppress deterioration of an image such as coloring expected at a portion where the incident angle is tight at the edge of the screen and horizontal stripes that are linear defects.

  In the above example, the apparent one pixel is applied to a three-transistor structure as a unit cell having a plurality of photoelectric conversion elements, but it can also be applied to other multiple-transistor structures, such as a four-transistor structure.

  In the above example, two types of second p-type semiconductor well regions having different widths are formed. However, three or more types of second p-type semiconductor well regions having different widths are formed according to the configuration and layout of the unit cell. It is possible that

  The solid-state imaging device of this embodiment can be applied to an electronic device module and a camera module. FIG. 7 shows a schematic configuration of an embodiment of the electronic device module and the camera module. The module configuration in FIG. 7 is applicable to both an electronic device module and a camera module. The module 110 includes a solid-state imaging device according to any of the above-described embodiments, for example, the CMOS image sensor 60, 83 optical lens 111, input / output unit 112, signal processing device (Digital Signal Processors) 113, and optical lens system control. A central processing unit (CPU) 114 is incorporated into one to form a module. In addition, as the electronic device module or the camera module 115, a module can be formed only by the CMOS image sensors 60 and 83, the optical lens system 111 and the input / output unit 112. A module including the CMOS image sensors 60 and 83, the optical lens system 111, the input / output unit 112, and the signal processing device 113 can also be configured.

  According to the electronic device module and the camera module, a color mixing characteristic difference between pixels in the CMOS image sensor can be suppressed, and a characteristic difference such as sensitivity, saturation, color mixing, and shading can be suppressed. As a result, high image quality can be achieved.

1 is a schematic imaging surface layout diagram showing an embodiment of a solid-state imaging device according to the present invention. It is sectional drawing on the BB line of FIG. 1 is an equivalent circuit diagram of a unit cell of a solid-state imaging device according to an embodiment of the present invention. It is a typical image pick-up surface layout figure showing other embodiments of a solid-state image sensing device concerning the present invention. It is sectional drawing on the CC line of FIG. It is an equivalent circuit schematic of the unit cell of the solid-state imaging device concerning other embodiments of the present invention. It is a circuit block diagram which shows the example of the module using the solid-state imaging device which concerns on this invention. It is a circuit diagram of a general CMOS image sensor. It is a wave form diagram of the control signal of the CMOS image sensor of FIG. It is an equivalent circuit diagram which shows the example of the unit pixel of the conventional CMOS image sensor. It is an equivalent circuit diagram which shows the example of the unit cell of the conventional CMOS image sensor. FIG. 12 is a schematic imaging surface layout diagram of a CMOS image sensor in which the unit cells of FIG. 11 are arranged. It is sectional drawing on the AA line of FIG.

Explanation of symbols

60..Solid-state imaging device, 61..Unit cell, 62, 63..Photoelectric conversion element, 64, 65..Transistor for transfer, 66..Transistor for reset, 67..Transistor for amplification, 68, 69 .. Transfer signal wiring, 70... Reset signal wiring, 71... Power supply line, 72 .. Imaging region, 73 .. Pixel output line, 76 [76A, 76B] .. Second semiconductor well region, 81. Substrate, 82... First semiconductor well region

Claims (8)

Photoelectric conversion elements arranged in a two-dimensional array;
A region in which a plurality of transistors are arranged, and is arranged between two photoelectric conversion elements arranged in one direction among the photoelectric conversion elements, and constitutes a unit cell together with the two photoelectric conversion elements Area,
A region that separates the transistor region and the photoelectric conversion element, and is disposed deeper than the transistor region and the photoelectric conversion element, and forms a first conductive element that forms the photoelectric conversion element below the photoelectric conversion element. A portion that is provided between regions of the first conductivity type that are continuously arranged from the charge storage region of the type, and that the width in one direction of the portion that separates the transistor region separates the photoelectric conversion elements between the unit cells A solid-state imaging device comprising: a second conductivity type semiconductor well region set larger than the width in the one direction. The solid-state imaging device according to claim 1, wherein the semiconductor well region is formed in the same process and has the same depth. The solid-state imaging device according to claim 1, wherein a reset transistor and an amplifying transistor are arranged in the transistor region. The solid-state imaging device according to claim 1, wherein an interval between the semiconductor well regions has the same width in the one direction. The solid-state imaging device according to claim 1, wherein the photoelectric conversion elements have the same width in the one direction. In the unit cell, means for reading the signal charge of the photoelectric conversion element is provided,
The solid-state imaging device according to any one of claims 1 to 5, wherein means for reading out the signal charge is shared by a plurality of photoelectric conversion elements in the unit cell. Said transistor region, the one direction is extended across between a plurality of photoelectric conversion elements arranged in a vertical other direction Rutotomoni, a plurality of the photoelectric conversion disposed across the transistor region of the photoelectric conversion element Transistors shared by the elements are provided ,
The solid-state imaging device according to claim 1, wherein the unit cell includes the transistor region and a plurality of photoelectric conversion elements arranged with the transistor region interposed therebetween. The solid-state imaging device according to claim 1, wherein each color filter is provided on a substrate on which the photoelectric conversion element is provided.

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